CN116978927A - 宽带隙半导体器件 - Google Patents
宽带隙半导体器件 Download PDFInfo
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- CN116978927A CN116978927A CN202310474801.0A CN202310474801A CN116978927A CN 116978927 A CN116978927 A CN 116978927A CN 202310474801 A CN202310474801 A CN 202310474801A CN 116978927 A CN116978927 A CN 116978927A
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- semiconductor device
- wide bandgap
- bandgap semiconductor
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- Electrodes Of Semiconductors (AREA)
Abstract
提出一种宽带隙半导体器件。宽带隙半导体器件包括:半导体本体,具有第一表面和沿着垂直方向与第一表面相对的第二表面。多个沟槽栅极结构从第一表面延伸到半导体本体中。多个沟槽栅极结构包括栅电极结构和布置在栅电极结构与半导体本体之间的栅极介电结构。栅极介电结构包括高k介电层。宽带隙半导体器件还包括多个台面区。多个沟槽栅极结构中的沟槽栅极结构的第一侧壁邻接多个台面区中的第一台面区,并且沟槽栅极结构的第二侧壁邻接多个台面区中的第二台面区。第一台面区包括邻接第一侧壁的第一导电类型的本体区。第二台面区包括第一导电类型的屏蔽区。屏蔽区的底侧具有比第一台面区中的本体区的底侧更大的到第一表面的第一垂直距离。
Description
技术领域
本公开涉及宽带隙半导体器件,特别地涉及包括多个沟槽栅极结构的宽带隙半导体器件。
背景技术
新各代宽带隙半导体器件(例如绝缘栅场效应晶体管(IGFET)诸如金属氧化物半导体场效应晶体管(MOSFET)或绝缘栅双极晶体管(IGBT))的技术发展旨在通过缩小器件几何形状来改善电器件特性和降低成本。虽然可以通过缩小器件几何形状来降低成本,但是当增加每单位面积的器件功能性时,必须满足各种折衷和挑战。例如,降低面积比导通状态电阻RonxA可能对其它电器件特性(诸如例如,可能受沟槽电介质(例如,栅极氧化物)中的高电场限制的器件可靠性)具有影响。
存在对改善宽带隙半导体器件的电特性的需要。
发明内容
本公开的示例涉及宽带隙半导体器件,该宽带隙半导体器件包括:半导体本体,具有第一表面和沿着垂直方向与第一表面相对的第二表面。宽带隙半导体器件还包括从第一表面延伸到半导体本体中的多个沟槽栅极结构。多个沟槽栅极结构包括栅电极结构和布置在栅电极结构与半导体本体之间的栅极介电结构。栅极介电结构包括高k介电层。宽带隙半导体器件还包括多个台面区。多个沟槽栅极结构中的沟槽栅极结构的第一侧壁邻接多个台面区中的第一台面区。沟槽栅极结构的第二侧壁邻接多个台面区中的第二台面区。第一台面区包括邻接第一侧壁的第一导电类型的本体区。第二台面区包括第一导电类型的屏蔽区。屏蔽区的底侧具有比第一台面区中的本体区的底侧更大的到第一表面的第一垂直距离。
本领域技术人员在阅读以下详细描述时并在查看附图时将会认识到另外的特征和优点。
附图说明
附图被包括以提供对实施例的进一步理解,并且被并入在本说明书中并构成本说明书的一部分。附图示出宽带隙半导体器件的实施例,并且与描述一起用于解释实施例的原理。在以下详细描述和权利要求中描述进一步的实施例。
图1A和1B是用于示出包括沟槽栅极结构的示例宽带隙半导体器件的示意截面图。
图2A至2C是用于示出宽带隙半导体器件的示例性栅极介电结构的示意截面图。
图3是用于示出宽带隙半导体器件的漂移结构的示例性特征的示意图。
具体实施方式
在以下详细描述中,参考附图,所述附图形成该详细描述的一部分,并且在所述附图中作为说明示出了其中可以处理半导体衬底的特定示例。要理解,在不偏离本公开范围的情况下,可以利用其它示例并且可以进行结构或逻辑的改变。例如,针对一个示例示出或描述的特征可以在其它示例上使用或结合其它示例使用,以产生又一示例。旨在本公开包括这种修改和变化。使用特定语言来描述这些示例,所述语言不应被解释为限制所附权利要求的范围。附图没有按比例绘制并且仅用于说明性目的。如果没有另外陈述,则在不同附图中对应的元件由相同的附图标记指定。
术语“具有”、“含有”、“包含”、“包括”等是开放的,并且术语指示所陈述结构、元件或特征的存在,但不排除另外的元件或特征的存在。冠词“一”、“一个”和“该”旨在包括复数以及单数,除非上下文另外明确指示。
术语“电连接”描述电连接元件之间的永久性低电阻连接,例如相关元件之间的直接接触或经由金属和/或重掺杂半导体材料的低电阻连接。术语“电耦合”包括适于信号和/或功率传输的一个或多个中间元件可以连接在电耦合元件之间,例如,可控制以在第一状态中临时提供低电阻连接和在第二状态中临时提供高电阻电去耦的元件。
如果两个元件A和B使用“或”来组合,则这要被理解为公开所有可能的组合,即,如果没有明确地或隐含地另外定义,则仅A、仅B以及A和B。相同组合的替选措词是“A和B中的至少一个”或“A和/或B”。加以必要的变更后,这同样适用于多于两个元件的组合。
针对物理尺寸给定的范围包括边界值。例如,参数y从a到b的范围写为a≤y≤b。对于具有一个边界值的范围(比如“至多”和“至少”),这同样成立。
来自化合物或合金的层或结构的主要成分是其原子形成化合物或合金的元素。例如,硅(Si)和碳(C)是碳化硅(SiC)层的主要成分。
术语“在......上”不要被解释为仅意味着“直接在......上”。相反,如果一个元件位于另一元件“上”(例如,层在另一层“上”或在衬底“上”),则另一组件(例如,另一层)可以位于两个元件之间(例如,如果层在衬底“上”,则另一层可以位于该层和该衬底之间)。
本公开的示例涉及宽带隙半导体器件。宽带隙半导体器件包括半导体本体,该半导体本体具有第一表面和沿着垂直方向与第一表面相对的第二表面。多个沟槽栅极结构从第一表面延伸到半导体本体中。多个沟槽栅极结构包括栅电极结构和布置在栅电极结构与半导体本体之间的栅极介电结构。栅极介电结构可以包括高k介电层。宽带隙半导体器件还可以包括多个台面区。多个沟槽栅极结构中的沟槽栅极结构的第一侧壁可以邻接多个台面区中的第一台面区。沟槽栅极结构的第二侧壁可以邻接多个台面区中的第二台面区。第一台面区可以包括邻接第一侧壁的第一导电类型的本体区。第二台面区可以包括第一导电类型的屏蔽区。屏蔽区的底侧可以具有比第一台面区中的本体区的底侧更大的到第一表面的第一垂直距离。
例如,宽带隙半导体器件可以是集成电路的一部分,或者可以是分立半导体器件或半导体模块。例如,宽带隙半导体器件可以是或可以包括绝缘栅场效应晶体管(IGFET),诸如金属氧化物半导体场效应晶体管(MOSFET)或绝缘栅双极晶体管(IGBT)。宽带隙半导体器件可以是在第一表面和与第一表面相对的第二表面之间具有负载电流流动的垂直半导体器件。垂直功率半导体器件可以被配置成传导大于1A、或大于10A、或大于30A、或大于50A、或大于75A、或甚至大于100A的电流,并且还可以被配置成阻断负载电极之间(例如,IGBT上的集电极和发射极之间,或MOSFET的漏极和源极之间)的电压,所述电压在几百上到几千伏特的范围内,例如400V、650V、1.2kV、1.7kV、3.3kV、4.5kV、5.5kV、6kV、6.5kV、10kV。例如,阻断电压可以对应于在功率半导体器件的数据表中指定的电压等级。
宽带隙半导体器件可以基于来自晶体宽带隙半导体材料的半导体本体,该晶体宽带隙半导体材料具有大于硅的带隙(即大于1.12eV)的带隙。作为示例,宽带隙半导体材料可以具有六方晶格并且可以是碳化硅(SiC)或氮化镓(GaN)。例如,半导体材料可以是2H-SiC(2H多型的SiC)、6H-SiC或15R-SiC。根据示例,半导体材料是4H多型的碳化硅(4H-SiC)。半导体本体可以包括半导体衬底或由半导体衬底组成,该半导体衬底在其上没有半导体层、具有一个或多于一个半导体层,例如外延生长层。
例如,第一表面可以是半导体本体的前表面或顶表面,而第二表面可以是半导体本体的背表面或后表面。例如,半导体本体可以经由第二表面附着到引线框架。例如,在半导体本体的第一表面上可以布置接合焊盘,并且接合线可以接合在接合焊盘上。
例如,沟槽栅极结构可以是条带形的,并且第一横向方向可以例如是条带形沟槽栅极结构的纵向方向。沟槽栅极结构在平面图中也可以具有另一布局或几何形状,例如六边形、正方形、圆形、椭圆形。例如,沟槽栅极结构的侧壁可以是非锥形的或略微锥形的。在沟槽栅极结构的略微锥形侧壁的情况下,沟道长度可以略微大于沟道区的垂直范围。沟槽栅极结构的锥角可以由工艺技术(例如沟槽蚀刻工艺的纵横比)引起,并且也可以用于最大化沟道区中的电荷载流子迁移率,该迁移率取决于沟道电流流动的方向。锥形沟槽栅极结构的另一示例是V形沟槽栅极结构。
栅电极结构可以包括一种或多种导电材料,例如金属、金属合金(例如Cu、Au、A1Cu、Ag或其合金)、金属化合物(例如TiN)、高掺杂半导体材料(诸如高掺杂多晶硅)。例如,所述一种或多种导电材料可以形成层堆叠。例如,栅电极结构可以电连接到栅极焊盘。栅极焊盘和例如第一负载电极焊盘(例如MOSFET的源极焊盘或IGBT的发射极焊盘)可以是宽带隙半导体本体上的布线区域的一部分。布线区域可以包括一个或多于一个(例如两个、三个、四个或甚至更多个)布线级。每个布线级可以由单个导电层或导电层的堆叠(例如,(一个或多个)金属层)形成。例如,可以光刻地图案化布线级。在堆叠的布线级之间,可以布置层间介电结构。可以在层间介电结构的开口中形成(一个或多个)接触插塞和/或(一个或多个)接触线,以将不同布线级的部分(例如金属线或接触区域)彼此电连接。
例如,每个台面区可以由多个沟槽栅极结构中的相对的沟槽栅极结构横向地限制。
邻接第一侧壁的本体区的一部分可以限定沟道区,该沟道区可以在导电性方面由例如通过场效应施加到栅电极结构的电势来控制。例如,施加到n沟道MOSFET中的沟槽栅极结构的正电压可以例如在邻接第一侧壁的p掺杂本体区的一部分中引发n反型沟道。该本体区可以例如通过本体区的顶表面上的接触插塞和/或沟槽接触部经由第一表面电连接,该沟槽接触部可以延伸到半导体本体中并且可以经由沟槽接触部的侧壁电连接到本体区。例如,本体区的沟道区部分可以包括由第二导电类型的掺杂剂(例如在p掺杂本体区的情况下为n型掺杂剂)进行的部分补偿以用于调整阈值电压。例如,可以通过穿过沟槽侧壁的倾斜离子注入来实现部分补偿。
屏蔽区可以与第二导电类型的漂移结构形成pn结。宽带隙半导体器件的阻断电压可以通过半导体本体中的漂移结构的杂质或掺杂浓度和/或垂直延伸来调整。漂移结构的掺杂浓度可以至少在其垂直延伸的部分中随着到第一表面的增加距离而逐渐地或逐步地增加或降低。根据其它示例,漂移结构中的杂质浓度可以是近似均匀的。对于基于SiC的宽带隙功率半导体器件来说,漂移结构中的平均杂质浓度可以在5×1014cm-3和1×1017cm-3之间,例如在从1×1015cm-3至2×1016cm-3的范围内。漂移结构的垂直范围可以取决于宽带隙半导体器件的电压阻断要求,例如指定的电压等级。当在电压阻断模式中操作宽带隙半导体器件时,空间电荷区可以部分或全部垂直延伸通过漂移结构,这取决于施加到宽带隙半导体器件的阻断电压。当在指定的最大阻断电压或接近指定的最大阻断电压操作宽带隙半导体器件时,空间电荷区可以到达或穿透到漂移结构的缓冲区中,该缓冲区被配置成防止空间电荷区进一步到达第二表面处的第二负载电极的接触部。例如,第二负载电极可以是IGBT的集电极或者MOSFET的漏电极。
为了实现期望的电流承载能力,宽带隙半导体器件可以由多个并联连接的宽带隙半导体器件单元来设计。并联连接的宽带隙半导体器件单元可以例如是以条带或条带区段的形状形成的宽带隙半导体器件单元。当然,宽带隙半导体器件单元也可以具有任何其它形状,例如圆形、椭圆形、诸如六边形或八面体的多边形。宽带隙半导体器件单元可以布置在半导体本体的有源区域中。有源区域可以是其中IGBT的发射极区(或MOSFET的源极区)和IGBT的集电极区(或MOSFET的漏极区)沿着垂直方向彼此相对布置的区域。在有源区域中,负载电流可以例如经由半导体本体的第一表面上的接触插塞而进入或离开宽带隙半导体器件的半导体本体。宽带隙半导体器件还可以包括边缘终端区域,该边缘终端区域可以包括终端结构。在宽带隙半导体器件的阻断模式中或反向偏置模式中,有源区域和无场区之间的阻断电压跨越终端结构横向下降。终端结构可以具有比有源区域更高或略微更低的电压阻断能力。例如,终端结构可以包括具有或没有横向掺杂变化(VLD)的结终端延伸(JTE)、一个或多个横向分离的保护环,或者它们的任何组合。
屏蔽区和包括高k介电层的栅极介电结构的提供可以允许增加栅极-源极电容(CGS),而不使宽带隙半导体器件的导通状态中的栅极介电结构的可靠性劣化。这可以允许降低面积比导通状态电阻RonxA和漏极引发的势垒降低(DIBL)。例如,由于栅极电介质中的高k介电层而降低的DIBL可以允许使用较短的MOS沟道(例如,在100nm至300nm的范围内)。鉴于高k介电层,与SiO2栅极电介质相比,可以降低屏蔽区对栅极介电层的屏蔽作用(effort)。这可以允许降低归因于基于屏蔽区的所谓JFET(结型场效应晶体管)的导通状态电阻分量。例如,缩小屏蔽区的垂直和/或横向尺寸可以允许更小的单元间距。与基于SiO2栅极电介质和屏蔽区的沟槽晶体管相比,可以实现许多技术益处,尤其包括避免要求高离子注入能量的深注入,因为可以允许更接近栅极介电结构的较高电场强度,屏蔽区的降低的横向距离使得能够实现单元缩小,由于高k介电层中降低的DIBL和/或负的内建电荷而导致的本体区的较低离子注入剂量使得能够实现由于导通状态中更少的离子杂质散射而导致的较高沟道迁移率。鉴于由于高k介电层而导致的较高栅极-源极电容,可以实现较低的DIBL;鉴于较高电场,可以实现电流扩散区的较高离子注入剂量,其中,鉴于高k介电层,所述较高电场被允许接近栅极介电层。对接近栅极介电层的较高电场的容忍可以允许降低形成沟槽MOSFET的JFET状屏蔽区通常所需的第一导电类型的所有离子注入能量/深度/剂量,从而降低JFET电阻并允许显著制造成本和复杂性降低以及允许间距降低(较浅的注入通常具有较少的“横向蔓延”)。同时,第二导电类型的较高离子注入剂量和/或能量可以用于形成允许更好的电流扩散和RonxA的进一步降低的优化电流扩散区。
例如,介电结构(缩写为DS)可以代替SiC MOSFET的已知SiO2栅极电介质,并且可以满足以下属性中的一个或多个,例如全部:i)相对介电常数:εr,AGI>>εr,SiO2,例如εr,AGI≥εr,SiC;ii)导带偏移:EC,DS-EC,SiC>>0,例如EV,SiC-EV,DS≥1eV;iii)价带偏移:EV,SiC-EV,DS>>0,例如EV,siC-EV,Ds≥1eV;iv)击穿强度EBD,DS>EBD,SiC,例如EBD,DS≥4MV/cm;v)是非铁电的。属性(i)使得能够实现以下益处:(1)在导通状态下增加栅极-源极电容而基本上不使栅极电介质可靠性劣化,从而降低沟道电阻和漏极引发的势垒降低(DIBL),以及(2)在截止状态下降低栅极电介质的屏蔽作用而基本上不使栅极电介质可靠性劣化,从而降低JFET电阻并允许较小间距。属性(ii)、(iii)和(iv)使介电结构的材料有资格作为SiC的栅极绝缘体。满足上面属性的材料例如是Al2O3、HfO2、ZrO2、A1N。属性(v)确保介电常数不随施加的栅极偏压而改变。
例如,宽带隙半导体器件的高k介电层可以包括Al2O3、ZrO2、HfO2、AlN、硅酸铝AlSiOx、硅La掺杂或Si掺杂的HfO2、TiO2、Y2O3或Si3N4中的至少一种。
例如,介电结构还可以包括布置在高k介电层和本体区之间的第一介电层。第一介电层可以具有比高k介电层的介电常数更小并且等于SiO2的介电常数或比SiO2的介电常数更大的介电常数。例如,第一介电层可以包括例如SiO2、A1N或Si3N4中的至少一种。
例如,第一介电层可以是第一SiO2层。高k介电层的厚度可以是第一介电层的第一厚度的2至200倍。这可以允许取得SiO2和宽带隙半导体本体例如SiC之间的界面属性的益处,同时利用高k介电层的高介电常数来降低沟道电阻和JFET屏蔽。
例如,第一SiOg层和半导体本体例如SiC之间的界面可以由氮钝化。例如,可以通过在半导体本体上形成薄SiO2层、随后在一氧化氮NO中退火来实现氮钝化。作为替选或另外,例如,也可以通过在一氧化氮气氛中在半导体本体上沉积薄SiO2层以及然后在一氧化氮气氛中钝化该层与半导体本体的界面来实现氮钝化。
作为替选或另外,例如,也可以通过在含氮气氛(例如一氧化氮NO或一氧化二氮N2O)中氧化碳化硅表面来实现氮钝化。为了进一步降低第一氮钝化氧化物层的厚度,在含氮气氛中氧化碳化硅表面之后,可以使用湿法氧化物蚀刻,例如含有氢氟酸的溶液。在湿法蚀刻之后,可以在SiC/SiO2界面处仅保留非常薄的含氮及氧层。
例如,第一厚度可以在从1nm至10nm的范围内。例如,第一介电层可以具有对应于少量单层的厚度。在一些示例中,第一介电层可以具有低于1nm的第一厚度。
例如,介电结构还可以包括布置在高k介电层和栅电极结构之间的第二介电层。第二介电层可以具有比高k介电层的介电常数更小并且等于SiO2的介电常数或比SiO2的介电常数更大的介电常数。例如,第二介电层可以包括例如SiO2、AlN或Si3N4中的至少一种。
例如,第二介电层可以是第二SiO2层。高k介电层的厚度可以是第一SiO2层的第一厚度、或第二SiO2层的第二厚度、或第一厚度与第二厚度的总和中的每个的2至200倍。厚度之间的这种关系可以取决于堆叠中的每个介电层的击穿电压和介电常数,并且可以针对目标可靠性和低沟道电阻进行优化,从而考虑高k介电层的击穿电压和高介电常数以及高k介电层与较低介电常数的其它介电层的比率。这可以允许取得SiO2和宽带隙半导体本体例如SiC之间的界面属性的进一步益处,同时利用高k介电层的高介电常数来降低沟道电阻。
例如,屏蔽区可以邻接沟槽栅极结构的第二侧壁的至少一部分和底侧的一部分。第一垂直距离可以在从沟槽栅极结构的底侧到第一表面的第二垂直距离的101%至150%的范围内。作为替选或另外,屏蔽区和漂移结构之间的pn结的底侧可以具有到沟槽栅极结构的底侧的垂直距离,该垂直距离例如在从10nm至500nm的范围内。与具有较深屏蔽区和SiO2栅极电介质的单元布局相比,这可以允许关于缩小单元布局尺寸和降低RonxA的改善。
例如,屏蔽区可以邻接第二侧壁的至少一部分。第一垂直距离可以在从沟槽栅极结构的底侧到第一表面的第二垂直距离的60%至100%的范围内。例如,第一垂直距离可以在从沟道区的端部(例如,本体区的底侧)到沟槽栅极结构的底侧的范围内。
例如,在第二导电类型的源极区的底侧的垂直水平处,屏蔽区的宽度可以在第二台面区的宽度的60%至90%的范围内。作为替选或另外,屏蔽区的宽度可以例如在从50nm至300nm的范围内。由于屏蔽区的深度可以相对于具有SiO2栅极氧化物的沟槽MOSFET的屏蔽区而降低,因此可以降低在屏蔽区的离子注入期间的横向蔓延。例如,这可以允许更好地控制水平注入轮廓(“更像盒形”)并且因此允许进一步降低单元布局尺寸。
例如,第二台面区可以包括邻接沟槽栅极结构的第二侧壁的本体区。例如,沟槽栅极结构的栅电极可以被配置成例如通过场效应来控制在沟槽栅极结构的相对侧壁处的沟道导电性。
例如,屏蔽区可以由本体区的部分横向地限制。例如,邻接沟槽栅极结构侧壁的本体区的部分可以限定沟道区,所述沟道区可以在导电性方面经由施加到沟槽栅极结构的栅电极的电势来控制。
例如,第一垂直距离可以在从沟槽栅极结构的底侧到第一表面的第二垂直距离的101%至150%的范围内。作为替选或另外,屏蔽区和漂移结构之间的pn结的底侧可以具有到沟槽栅极结构的底侧的垂直距离,该垂直距离例如在从10nm至500nm的范围内。与具有较深屏蔽区和SiO2栅极电介质的单元布局相比,这可以允许关于缩小单元布局尺寸和降低RonxA的改善。
例如,宽带隙半导体器件还可以包括第二导电类型的漂移区和第二导电类型的电流扩散区。电流扩散区可以布置在漂移区和本体区之间,并且可以具有沿着电流扩散区的垂直范围平均的掺杂浓度,该掺杂浓度是沿着漂移区的一部分平均的掺杂浓度的10至1000倍。漂移区的该部分可以邻接电流扩散区,并且可以具有与电流扩散区的垂直范围相对应的垂直范围。例如,电流扩散区和漂移区可以是漂移结构的部分。
例如,沟槽栅极结构可以沿着纵向方向平行延伸。屏蔽区可以具有沿着纵向方向彼此间隔开的多个子区。例如,沿着纵向方向的子区之间的横向间隔可以是恒定的或变化的。同样,例如,沿着纵向方向的子区的横向尺寸可以是恒定的或变化的。
例如,屏蔽区的垂直掺杂轮廓可以被配置成将在宽带隙半导体器件的负载电极(例如源极和漏极)之间的电击穿电压的99%处的电场强度的峰值设置在沟槽栅极结构的底侧或拐角处的在沟槽介电结构与半导体本体之间的界面处或接近该界面。
可以组合以上和以下描述的示例和特征。
结合碳化硅衬底描述以上和以下示例中的一些。替选地,可以处理宽带隙半导体衬底,例如宽带隙晶片,例如包括不同于碳化硅的宽带隙半导体材料。宽带隙半导体晶片可以具有比硅的带隙(1.12eV)大的带隙。例如,宽带隙半导体晶片可以是碳化硅(SiC)晶片、或砷化镓(GaAs)晶片、或氮化镓(GaN)晶片。
更多细节和方面结合以上或以下描述示例来提及。处理宽带隙半导体晶片可以包括与结合所提出的构思或以上或以下描述的一个或多个示例提及的一个或多个方面相对应的一个或多个可选的另外特征。
本描述和附图仅仅示出本公开的原理。此外,本文中叙述的所有示例主要明确地旨在仅用于说明性目的,以辅助读者理解本公开的原理和由(一个或多个)发明人为推动技术所贡献的构思。本文中叙述本公开的原理、方面和示例的所有陈述及其特定示例旨在涵盖其等同物。
在下文中,结合附图解释场效应晶体管FET的进一步示例。关于以上示例描述的功能和结构的细节应当同样适用于附图中示出的和以下进一步描述的示例性实施例。在所示出的示例中,对于n沟道FET,第一导电类型是p型而第二导电类型是n型。然而,对于p沟道FET,第一导电类型也可以是n型而第二导电类型可以是p型。
关于结构或功能的细节或者以上描述的特征的技术益处同样适用于以下的示例,反之亦然。
图1A示意性且示例性地示出宽带隙半导体器件100的有源区域的部分截面图。宽带隙半导体器件100可以是垂直功率半导体器件,该垂直功率半导体器件还包括至少部分地围绕有源区域的边缘终端区域(图1A中未示出)。宽带隙半导体器件100包括SiC半导体本体102,该SiC半导体本体102具有第一表面104和沿着垂直方向y与第一表面104相对的第二表面106。多个沟槽栅极结构108从第一表面104延伸到半导体本体102中。多个沟槽栅极结构108包括栅电极结构1081和布置在栅电极结构1081与半导体本体102之间的栅极介电结构1082。栅极介电结构1082包括高k介电层1083。宽带隙半导体器件100还包括多个台面区110。多个沟槽栅极结构108的沟槽栅极结构108的第一侧壁1091邻接多个台面区110的第一台面区1101。沟槽栅极结构108的第二侧壁1092邻接多个台面区110的第二台面区1102。第一台面区1101包括邻接第一侧壁1091的p掺杂本体区112。第二台面区1102包括p掺杂屏蔽区114,并且屏蔽区114的底侧1141具有比第一台面区1101中的本体区112的底侧1121更大的到第一表面104的第一垂直距离。底侧1121可以位于沟槽栅极结构108的底侧1087下方(如图1A中示出的),或者可以位于底侧1087上方(图1A中未示出)。屏蔽区可以沿着垂直于图1A的绘图平面延伸的横向方向是连续的,或者可以沿着垂直于图1A的绘图平面延伸的横向方向被细分成彼此间隔的屏蔽子区。第一台面区1101还包括邻接第一侧壁1091的n+掺杂源极区或发射极区122。宽带隙半导体器件100还包括在本体区112/屏蔽区114与第二表面106之间的n掺杂漂移结构124。漂移结构124可以包括一个或多个子区,所述一个或多个子区可以例如关于掺杂浓度和垂直范围不同(图1A中未示出)。漂移结构124的子区可以尤其包括n-掺杂漂移区、漂移区和第二表面106之间的n掺杂电流扩散区。n+掺杂漏极接触区(对于宽带隙MOSFET)或p+掺杂集电极区(对于宽带隙IGBT)布置在漂移结构124和第二表面106之间(图1A中未示出)。
第一负载电极L1经由宽带隙半导体本体102的第一表面104电连接到源极区122、屏蔽区114和本体区112。第二负载电极L2经由半导体本体102的第二表面106电连接到漂移结构124。例如,第一负载电极L1和第二负载电极L2之间的宽带隙半导体器件100的阻断电压可以由屏蔽区112和漂移结构124之间的pn结的击穿电压来确定。
第一负载电极L1和栅电极结构1081通过中间电介质126电绝缘。
在图1A的示例中,宽带隙半导体器件100包括在沟槽栅极结构108的相对侧壁的一个侧壁处的沟道区。沟道区由邻接沟槽栅极结构108的本体区112的一部分限定。
图1B示意性且示例性地示出在沟槽栅极结构108的相对侧壁处具有沟道区的宽带隙半导体器件100的另一示例的有源区域的部分截面图。在图1B中示出的示例中,第二台面区1102包括邻接沟槽栅极结构108的第二侧壁1092的本体区112。
为了实现图1A和1B中示出的宽带隙半导体器件100的期望电流承载能力,宽带隙半导体器件100可以由多个并联连接的宽带隙半导体器件单元1001来设计。并联连接的宽带隙半导体器件单元1001可以例如是以条带或条带区段的形状形成的宽带隙半导体器件单元。
图2A至2C示意性且示例性地示出用于示出布置在本体区112与栅极结构1081之间的栅极介电结构1082的示例的部分截面图。
参考图2A的截面图,本体区112与栅电极结构1081之间的栅极介电结构1082由高k介电层1083组成。
参考图2B的截面图,本体区112与栅电极结构1081之间的栅极介电结构1082包括高k介电层1083和布置在高k介电层1083与本体区112之间的第一介电层1084。第一介电层1084可以具有比高k介电层1083的介电常数小并且等于SiO2的介电常数或比SiO2的介电常数大的介电常数。例如,第一介电层1084可以包括例如SiO2、A1N或Si3N4中的至少一种。例如,第一介电层1084可以是第一SiO2层。高k介电层1083的厚度t0可以是第一介电层1084的第一厚度t1的2至200倍。第一SiO2层1084和半导体本体102例如SiC之间的界面130可以由氮钝化。
参考图2C的截面图,本体区112与栅电极结构1081之间的栅极介电结构1082包括:除了高k介电层1083和布置在高k介电层1083与本体区112之间的第一介电层1084之外,布置在高k介电层1083与栅电极结构1081之间的第二介电层1085。第二介电层1085可以具有比高k介电层1083的介电常数小并且等于SiO2的介电常数或比SiO2的介电常数大的介电常数。例如,第二介电层1085可以包括例如SiO2、AlN或Si3N4中的至少一种。高k介电层1083的厚度可以是具有较低介电常数的每个单个介电层或总和的2至200倍,例如是第一SiO2层1084的第一厚度t1或第二SiO2层1085的第二厚度t2或其总和的2至200倍。
图3示意性且示例性地示出用于示出漂移结构124的示例性子区的宽带隙半导体器件100的有源区域的部分截面图。漂移结构124可以包括n-掺杂漂移区1241和n掺杂电流扩散区1242。电流扩散区1242布置在漂移区1241和本体区112之间,并且具有沿着电流扩散区1242的垂直范围平均的掺杂浓度,该掺杂浓度是沿着漂移区1241的一部分平均的掺杂浓度的例如10至1000倍。例如,漂移区1241的该部分可以邻接电流扩散区1242并且可以具有与电流扩散区1242的垂直范围相对应的垂直范围。漂移结构124还可以包括漂移区1241与第二表面106之间的n掺杂缓冲区1243。漂移结构124经由第二表面106处的n+掺杂漏极接触区128电连接到第二负载电极L2(例如漏电极)。
连同先前描述的示例和附图中的一个或多个一起提及和描述的方面和特征也可以与其它示例中的一个或多个组合,以便代替其它示例的相似特征或者以便向其它示例另外引入该特征。
尽管本文中示出和描述了特定实施例,但是本领域普通技术人员将会理解,在不偏离本发明范围的情况下,可以用各种替选和/或等同实施方式来替代所示出和描述的特定实施例。本申请旨在覆盖本文中讨论的特定实施例的任何适配或变化。因此,旨在本发明仅由权利要求及其等同物来限制。
Claims (20)
1.一种宽带隙半导体器件(100),包括:
半导体本体(102),具有第一表面(104)和沿着垂直方向(y)与所述第一表面(104)相对的第二表面(106);
多个沟槽栅极结构(108),从所述第一表面(104)延伸到所述半导体本体(102)中,所述多个沟槽栅极结构(108)包括栅电极结构(1081)和布置在所述栅电极结构(1081)与所述半导体本体(102)之间的栅极介电结构(1082),所述栅极介电结构(1082)包括高k介电层(1083);
多个台面区(110),其中,所述多个沟槽栅极结构(108)中的沟槽栅极结构(108)的第一侧壁(1091)邻接所述多个台面区(110)中的第一台面区(1101),并且所述沟槽栅极结构(108)的第二侧壁(1092)邻接所述多个台面区(110)中的第二台面区(1102),其中,
所述第一台面区(1101)包括邻接所述第一侧壁(1091)的第一导电类型的本体区(112);以及
所述第二台面区(1102)包括所述第一导电类型的屏蔽区(114),并且所述屏蔽区(114)的底侧(1141)具有比所述第一台面区(1101)中的所述本体区(112)的底侧(1121)更大的到所述第一表面(104)的第一垂直距离。
2.根据前一权利要求所述的宽带隙半导体器件(100),其中,所述高k介电层(1083)包括Al2O3、ZrO2、HfO2、A1N、硅酸铝AlSiOx、硅掺杂HfO2、TiO2、Y2O3或Si3N4中的至少一种。
3.根据前述权利要求中任一项所述的宽带隙半导体器件(100),其中,所述介电结构(1082)还包括布置在所述高k介电层(1083)与所述本体区(112)之间的第一介电层(1084),所述第一介电层(1084)具有比所述高k介电层(1083)的介电常数小并且等于SiO2的介电常数或比SiO2的介电常数大的介电常数。
4.根据前一权利要求所述的宽带隙半导体器件(100),其中,所述第一介电层(1084)是第一SiO2层,并且所述高k介电层(1083)的厚度(t0)是所述第一介电层(1084)的第一厚度(t1)的2至200倍。
5.根据前一权利要求所述的宽带隙半导体器件,其中,所述第一SiO2层与所述半导体本体(102)之间的界面由氮钝化。
6.根据前一权利要求所述的宽带隙半导体器件(100),其中,所述第一厚度(t1)在从1nm至10nm的范围内。
7.根据权利要求5所述的宽带隙半导体器件(100),其中,所述第一厚度(t1)小于1nm。
8.根据前三项权利要求中任一项所述的宽带隙半导体器件(100),其中,所述介电结构(1082)还包括布置在所述高k介电层(1083)和所述栅电极结构(1081)之间的第二介电层(1085),所述第二介电层(1085)具有比所述高k介电层(1083)的介电常数小并且等于SiO2的介电常数或比SiO2的介电常数大的介电常数。
9.根据前一权利要求所述的宽带隙半导体器件(100),其中,所述第二介电层是第二SiO2层,并且所述高k介电层(1083)的厚度(t0)是所述第一SiO2层(1084)的第一厚度(t1)、或所述第二SiO2层(1085)的第二厚度(t2)、或所述第一厚度与所述第二厚度的总和中的每个的2至200倍。
10.根据前述权利要求中任一项所述的宽带隙半导体器件(100),其中,所述屏蔽区(114)邻接所述第二侧壁(1092)的至少一部分和所述沟槽栅极结构(108)的底侧的一部分,并且所述第一垂直距离在从所述沟槽栅极结构(108)的底侧(1087)到所述第一表面(104)的第二垂直距离的101%至150%的范围内。
11.根据权利要求1至9中任一项所述的宽带隙半导体器件(100),其中,所述屏蔽区(114)邻接所述第二侧壁(1092)的至少一部分,并且所述第一垂直距离在从所述沟槽栅极结构(108)的底侧(1087)到所述第一表面(104)的第二垂直距离的60%至100%的范围内。
12.根据前两项权利要求中任一项所述的宽带隙半导体器件(100),其中,在所述第二导电类型的源极区(122)的底侧的垂直水平处,所述屏蔽区(114)的宽度在所述第二台面区(1102)的宽度的60%至90%的范围内。
13.根据前述权利要求中任一项所述的宽带隙半导体器件(100),其中,所述第二台面区(1102)包括邻接所述沟槽栅极结构(108)的所述第二侧壁(1092)的所述本体区(112)。
14.根据前一权利要求所述的宽带隙半导体器件(100),其中,所述屏蔽区(114)由所述本体区(112)的部分横向地限制。
15.根据前两项权利要求中任一项所述的宽带隙半导体器件(100),其中,所述第一垂直距离在从所述沟槽栅极结构(108)的底侧(1087)到所述第一表面(104)的第二垂直距离的101%至110%的范围内。
16.根据前述权利要求中任一项所述的宽带隙半导体器件(100),还包括第二导电类型的漂移区(116)和所述第二导电类型的电流扩散区(118),其中,所述电流扩散区(118)布置在所述漂移区(116)和所述本体区(112)之间并且具有沿着所述电流扩散区(118)的垂直范围平均的掺杂浓度,所述掺杂浓度是沿着所述漂移区(116)的一部分平均的掺杂浓度的10至1000倍,其中,所述漂移区(116)的所述部分邻接所述电流扩散区(118)并且具有与所述电流扩散区(118)的垂直范围相对应的垂直范围。
17.根据前述权利要求中任一项所述的宽带隙半导体器件(100),其中,所述沟槽栅极结构(108)沿着纵向方向平行延伸,并且所述屏蔽区(114)具有沿着所述纵向方向彼此间隔的多个子区。
18.根据前述权利要求中任一项所述的宽带隙半导体器件(100),其中,所述半导体本体(102)是4H-SiC半导体本体。
19.根据前述权利要求中任一项所述的宽带隙半导体器件(100),其中,所述屏蔽区(114)的垂直掺杂轮廓被配置成将在所述宽带隙半导体器件(100)的负载电极(L1、L2)之间的电击穿电压的99%处的电场强度的峰值设置在所述沟槽栅极结构(108)的底侧处的在所述沟槽介电结构(1082)与所述半导体本体(102)之间的界面处或者接近所述界面。
20.根据前述权利要求中任一项所述的宽带隙半导体器件(100),其中,所述沟槽栅电极结构(108)包括金属或金属化合物。
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