CN116755507A - Voltage stabilizing circuit and power supply device - Google Patents
Voltage stabilizing circuit and power supply device Download PDFInfo
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- CN116755507A CN116755507A CN202311061747.3A CN202311061747A CN116755507A CN 116755507 A CN116755507 A CN 116755507A CN 202311061747 A CN202311061747 A CN 202311061747A CN 116755507 A CN116755507 A CN 116755507A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
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Abstract
The application provides a voltage stabilizing circuit and a power supply device, which are provided with an input node for being connected to an input voltage source and an output node for being connected to a load, and comprise: the device comprises a constant current module, a current mirror module and a negative feedback output module. The current mirror module is connected with the constant current module and the negative feedback output module, both the current mirror module and the negative feedback output module are connected with the input node, and the negative feedback output module is also connected with the output node. The constant current module outputs reference current to the current mirror module. The current mirror module outputs a constant first voltage and mirror current to the negative feedback output module based on the input voltage source and the reference current. The negative feedback output module provides a second voltage for the load based on the input voltage source and keeps the second voltage stable according to the first voltage and the mirror current. In the voltage stabilizing circuit, the output current is regulated according to the first voltage and the mirror current through the negative feedback output module, so that the stability of the second voltage is improved.
Description
Technical Field
The embodiment of the application relates to the technical field of electronic power, in particular to a voltage stabilizing circuit and a power supply device.
Background
As the process matures, the minimum size of semiconductor devices is decreasing, the threshold voltage of the devices is also decreasing, and the minimum operating voltage of the corresponding circuits is also decreasing. Low voltage means low power consumption and the standby capability of the system is enhanced. Meanwhile, the ideal voltage source does not change along with the change of input voltage, process and temperature, and the post-stage circuit can obtain a stable working state.
However, the voltage source in the prior art has an open loop structure, does not have an output clamping function, and can change the output voltage when the load current changes, so that the output voltage is unstable.
Disclosure of Invention
The embodiment of the application provides a voltage stabilizing circuit and a power supply device, which can utilize a negative feedback output module to adjust output voltage and improve the stability of the output voltage.
In a first aspect, an embodiment of the present application provides a voltage stabilizing circuit, having an input node for connecting to an input voltage source and an output node for connecting to a load, including: the device comprises a constant current module, a current mirror module and a negative feedback output module. The current mirror module is connected with the constant current module and the negative feedback output module, the current mirror module and the negative feedback output module are both connected with the input node, and the negative feedback output module is also connected with the output node. The constant current module outputs reference current to the current mirror module; the current mirror module outputs a constant first voltage and mirror current to the negative feedback output module based on the input voltage source and the reference current; the negative feedback output module provides a second voltage for the load based on the input voltage source, and keeps the second voltage stable according to the first voltage and the mirror current.
In some embodiments, the negative feedback output module includes a first switching tube, a second switching tube, and a switching tube series group including at least two third switching tubes connected in series. The control end of the first switching tube is connected with the first end of the current mirror module, the first end of the first switching tube and the control end of the second switching tube are both connected with the second end of the current mirror module, the second end of the first switching tube is connected with the third end of the current mirror module, the first end of the second switching tube is connected with the input node, the switching tube series group is connected between the second end of the second switching tube and the second end of the first switching tube, and the connection point of the second switching tube and the switching tube series group is also connected with the output node. The first switching tube adjusts the voltage of the control end of the second switching tube based on the first voltage, the second voltage and the mirror current. The second switching tube adjusts the second voltage based on the voltage of the control end of the second switching tube and the input voltage source.
In some embodiments, the second switching tube is a PMOS tube. The grid electrode of the PMOS tube is respectively connected with the first end of the first switch tube and the second end of the current mirror module, the source electrode of the PMOS tube is connected with the input node, and the drain electrode of the PMOS tube is respectively connected with the output node and the switch tube series group.
In some embodiments, the negative feedback output module further comprises a capacitor. The capacitor is connected between the control end of the second switching tube and the second end of the second switching tube.
In some embodiments, the at least two third switching tubes connected in series include a third a switching tube and a third B switching tube. The first end of the third A switch tube is connected with the second end of the second switch tube, the control end of the third A switch tube is respectively connected with the second end of the third A switch tube, the control end of the third B switch tube and the first end of the third B switch tube, and the second end of the third B switch tube is respectively connected with the second end of the first switch tube and the third end of the current mirror module.
In some embodiments, the at least two third switching tubes connected in series further comprise a third C-switching tube. The third C switch tube is connected between the second end of the second switch tube and the first end of the third A switch tube.
In some embodiments, the current mirror module includes a first current mirror unit and a second current mirror unit. The first end of the first current mirror unit is connected with the input node, the second end of the first current mirror unit is connected with the constant current module, the third end of the first current mirror unit is connected with the first end of the second current mirror unit, the fourth end of the first current mirror unit is connected with the first end of the negative feedback output module, the second end of the second current mirror unit is connected with the second end of the negative feedback output module, and the third end of the second current mirror unit is connected with the third end of the negative feedback output module. The first current mirror unit outputs the mirror current to the negative feedback output module and the second current mirror unit based on the input voltage source and the reference current. The second current mirror unit outputs the first voltage to the negative feedback output module based on the mirror current.
In some embodiments, the first current mirror unit comprises a PMOS current mirror unit or a cascode current mirror unit.
In some embodiments, the second current mirror unit comprises an NMOS current mirror unit.
In a second aspect, an embodiment of the present application further provides a power supply device, where the power supply device includes a voltage stabilizing circuit according to any one of the embodiments of the first aspect.
Compared with the prior art, the application has the beneficial effects that: in contrast to the prior art, the present application provides a voltage stabilizing circuit and a power supply device having an input node for connection to an input voltage source and an output node for connection to a load, comprising: the device comprises a constant current module, a current mirror module and a negative feedback output module. The current mirror module is connected with the constant current module and the negative feedback output module, both the current mirror module and the negative feedback output module are connected with the input node, and the negative feedback output module is also connected with the output node. The constant current module outputs reference current to the current mirror module. The current mirror module outputs a constant first voltage and mirror current to the negative feedback output module based on the input voltage source and the reference current. The negative feedback output module provides a second voltage for the load based on the input voltage source and keeps the second voltage stable according to the first voltage and the mirror current. In the voltage stabilizing circuit, the output current is regulated according to the first voltage and the mirror current through the negative feedback output module, so that the stability of the second voltage is improved.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements/modules and steps, and in which the figures do not include the true to scale unless expressly indicated by the contrary reference numerals.
Fig. 1 is a circuit configuration diagram of a power supply circuit provided in the prior art;
FIG. 2 is a block diagram of a voltage stabilizing circuit according to an embodiment of the present application;
FIG. 3 is a block diagram of another voltage stabilizing circuit according to an embodiment of the present application;
FIG. 4 is a circuit configuration diagram of a first voltage stabilizing circuit according to an embodiment of the present application;
FIG. 5 is a circuit configuration diagram of a second voltage stabilizing circuit according to an embodiment of the present application;
fig. 6 is a circuit configuration diagram of a third voltage stabilizing circuit according to an embodiment of the present application.
Detailed Description
The present application will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the present application, but are not intended to limit the application in any way. It should be noted that variations and modifications could be made by those skilled in the art without departing from the inventive concept. These are all within the scope of the present application.
In order that the application may be readily understood, a more particular description thereof will be rendered by reference to specific embodiments that are illustrated in the appended drawings. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used in this specification includes any and all combinations of one or more of the associated listed items.
It should be noted that, if not in conflict, the features of the embodiments of the present application may be combined with each other, which is within the protection scope of the present application. In addition, although functional block division is performed in the device schematic, in some cases, block division may be different from that in the device. Moreover, the words "first," "second," and the like as used herein do not limit the data and order of execution, but merely distinguish between identical or similar items that have substantially the same function and effect.
Referring to fig. 1, in one implementation of a power supply circuit, an NMOS Q4 is used as an output load tube, an input node in of the NMOS Q is connected to an input voltage source, and an output node out of the NMOS Q is connected to a load. In this power supply circuit, since the constant current source ib flows through the switching transistor Q1, the switching transistor Q2, and the switching transistor Q3, the gate voltage vx input to the NMOS transistor Q4 is about V GS_Q1 +V GS_Q2 +V GS_Q3 Wherein V is GS_Q1 Is the gate-source voltage, V of the switch tube Q1 GS_Q2 Is the gate-source voltage, V of the switch tube Q2 GS_Q3 For the gate-source voltage of the switching tube Q3, if V GS_Q1 =V GS_Q2 =V GS_Q3 =vgs, i.e. vx≡3VGS, then the output voltage vout=v GS_Q1 +V GS_Q2 +V GS_Q3 -V GS_Q4 If V GS_Q4 =vgs, then vout≡2VGS.
However, in the circuit shown in fig. 1, the input voltage vin needs to be at least 3VGS to enable the output voltage vout to reach the theoretical value (2 VGS), and if the input voltage vin is lower than 3VGS, the output voltage vout will be lower than 2VGS, and the subsequent circuit will likely not work. In addition, in the circuit shown in fig. 1, the NMOS transistor Q4 needs to be larger in size to enable the output voltage vout to have a certain load capacity, but still has the following drawbacks: because the output voltage of the power supply circuit is in an open loop structure and does not have an output embedded voltage function, if the load current is large, the voltage between the grid electrode and the source electrode of the NMOS tube Q4 is large, so that the output voltage vout is low, if the load current is changed from 0uA to 100uA, the change amplitude of the output voltage may reach 0.6V, namely the output voltage of the circuit is unstable. In summary, the power supply circuit shown in fig. 1 is not suitable for low input voltage operation, and its output voltage is unstable.
In order to solve the above technical problems, an embodiment of the present application provides a voltage stabilizing circuit and a power supply device, where the voltage stabilizing circuit adjusts an output voltage through a negative feedback output module, improves stability of the output voltage, and is subsequently applicable to low input voltage operation.
IN a first aspect, referring to fig. 2, a voltage stabilizing circuit is provided, which has an input node IN for connecting to an input voltage source and an output node OUT for connecting to a load, the voltage stabilizing circuit includes: a constant current module 10, a current mirror module 20 and a negative feedback output module 30.
The current mirror module 20 is connected with the constant current module 10 and the negative feedback output module 30, the current mirror module 20 and the negative feedback output module 30 are both connected with the input node IN, and the negative feedback output module 30 is also connected with the output node OUT. Wherein the constant current module 10 outputs a reference current to the current mirror module 20. The current mirror module 20 outputs a constant first voltage and mirror current to the negative feedback output module 30 based on the input voltage source and the reference current. The negative feedback output module 30 provides a second voltage to the load based on the input voltage source and stabilizes the second voltage according to the first voltage and the mirrored current.
Specifically, referring to fig. 3, a first end of the current mirror module 20 is connected to a second end of the negative feedback output module 30, a second end of the current mirror module 20 is respectively connected to the first end of the negative feedback output module 30, a third end of the current mirror module 20 is connected to a third end of the negative feedback output module 30, a fourth end of the current mirror module 20 is connected to the constant current module 10, a fifth end of the current mirror module 20 and a fourth end of the negative feedback output module 30 are both connected to the input node IN, and a fifth end of the negative feedback output module 30 is connected to the output node OUT.
The constant current module 10 may be a constant current source circuit, or may be a constant current source provided by a pre-stage circuit, which can make the output reference current not change with the voltage change of the input voltage source, that is, the reference current remains constant, and the specific circuit structure may refer to the prior art and is not limited herein.
The mirror current output by the current mirror module 20 has a certain ratio relationship with the reference current output by the constant current module 10, and in this context, the ratio is 1:1, that is, the mirror current and the reference current are equal in magnitude, which is not limited in practical application.
IN the voltage stabilizing circuit, after the constant current module 10 outputs a constant reference current to the current mirror module 20, and after the current mirror module 20 receives an input voltage source through the input node IN, a constant mirror current is output to the negative feedback output module 30 through the second end, and a constant first voltage is output to the negative feedback output module 30 through the first end, and after the negative feedback output module 30 receives the input voltage source through the input node IN, a second voltage is output to a load through the output node OUT, and meanwhile, the negative feedback output module 30 adjusts the output current of the output node OUT according to the second voltage, the first voltage and the mirror current, so that the amplitude of the second voltage is adjusted, and the second voltage is kept stable. Specifically, if the second voltage decreases, the negative feedback output module 20 will raise the output current of the output node OUT according to the second voltage, the first voltage and the mirror current, so as to raise the second voltage, and if the second voltage increases, the negative feedback output module 20 will reduce the output current of the output node OUT according to the second voltage, the first voltage and the mirror current, so as to lower the second voltage, thereby ensuring the stability of the second voltage.
It can be seen that in the voltage stabilizing circuit, the negative feedback output module 30 not only can provide the second voltage for the load according to the input voltage source, but also can keep the second voltage stable according to the first voltage and the mirror current, and the voltage stabilizing circuit can utilize the negative feedback output module 30 to adjust the output current, thereby adjusting the second voltage (i.e. the output voltage) and providing stability of the output voltage.
In some embodiments, referring to fig. 4, the negative feedback output module 30 includes a first switching tube 31, a second switching tube 32, and a switching tube series group 33, where the switching tube series group 33 includes at least two third switching tubes connected in series. The control end of the first switching tube 31 is connected with the first end of the current mirror module 20, the first end of the first switching tube 31 and the control end of the second switching tube 32 are both connected with the second end of the current mirror module 20, the second end of the first switching tube 31 is connected with the third end of the current mirror module 20, the first end of the second switching tube 32 is connected with the input node IN, the switching tube series group 33 is connected between the second end of the second switching tube 32 and the second end of the first switching tube 31, and the connection point of the second switching tube 32 and the switching tube series group 33 is also connected with the output node OUT. Wherein the first switching tube 31 adjusts the voltage of the control terminal of the second switching tube 32 based on the first voltage, the second voltage and the mirror current. The second switching tube 32 adjusts the second voltage based on the voltage of the control terminal of the second switching tube 32 and the input voltage source.
In this voltage stabilizing circuit, if the load current suddenly increases, the output voltage at the output node OUT drops, and the output voltage vout=v 33 +Vx, where V 33 As the voltage drop across the series group 33 of switching tubes Vx is the voltage between the second end of the first switching tube 31 and ground, vx will also drop, since the first end of the current mirror module 20 outputs a first voltage to the control end of the first switching tube 31, i.e. the voltage at the control end of the first switching tube 31 is the first voltage, the voltage between the control end and the second end of the first switching tube 31 will increase, the current flowing through the first switching tube 31 will increase, since the second end of the current mirror module 20 outputs a mirrored current to the first end of the first switching tube 31, the voltage at the control end of the second switching tube 32 will drop, and the voltage at the control end of the second switching tube 32 will be the input voltage source, the voltage between the control end and the first end of the second switching tube 32 will increase, resulting in an increase in the current output at the output node OUT. If the load current suddenly decreases, the output voltage at the output node OUT increases, vx also increases, since the voltage at the control terminal of the first switching tube 31 is the first voltage, the voltage between the control terminal and the second terminal of the first switching tube 31 decreases, so that the current flowing through the first switching tube 31 decreases, since the second terminal of the current mirror module 20 outputs the mirror current to the first terminal of the first switching tube 31, the voltage at the control terminal of the second switching tube 32 increases, and the voltage at the control terminal of the second switching tube 32 is the input voltage source, so that the voltage between the control terminal and the first terminal of the second switching tube 32 decreases, resulting in a decrease in the current output by the second switching tube 32, and thus in a decrease in the output voltage at the output node OUT.
It can be seen that in this voltage regulator circuit, the negative feedback output module 30 can ensure that the output voltage at the output node OUT remains constant as the load current increases or decreases.
Specifically, in some embodiments, as shown in fig. 4, the first switching tube 31 may include an NMOS tube M5, where the control end of the first switching tube 31 is a gate of the NMOS tube M5, the first end is a drain of the NMOS tube M5, and the second end is a source of the NMOS tube M5. In the present embodiment, the NMOS transistor M5 is used as the first switching transistor 31, and the voltage of the control terminal of the second switching transistor 32 can be adjusted based on the second voltage, the first voltage and the mirror current.
In some embodiments, the at least two third switching tubes connected in series include a third a switching tube and a third B switching tube. The first end of the third A switch tube is connected with the second end of the second switch tube 32, the control end of the third A switch tube is respectively connected with the second end of the third A switch tube, the control end of the third B switch tube and the first end of the third B switch tube, and the second end of the third B switch tube is respectively connected with the second end of the first switch tube 31 and the third end of the current mirror module 20.
Specifically, referring to fig. 4, the third a switch tube is a PMOS tube M8, the third B switch tube is an NMOS tube M9, wherein the control end of the third a switch tube is a gate of the PMOS tube M8, the first end is a source of the PMOS tube M8, the second end is a drain of the PMOS tube M8, the control end of the third B switch tube is a gate of the NMOS tube M9, the first end is a drain of the NMOS tube M9, the second end is a source of the NMOS tube M9, if the voltage between the source and the drain of the PMOS tube M8 is V GS_M8 The voltage between the drain and the source of the NMOS tube M9 is V GS_M9 And V is GS_M8 =V GS_M9 When the voltage Vx is smaller, the second voltage vout=v is the voltage vout=2vgs GS_M8 +V GS_M9 +Vx≈2VGS。
In other embodiments, the at least two third switching tubes connected in series further comprise a third C-switching tube. The third C-switch is connected between the second end of the second switch 32 and the first end of the third a-switch. Specifically, referring to fig. 5, the third C-switch tube is a PMOS tube M10, wherein a control end of the PMOS tube M10 is connected to the first end of the third a-switch tube and the drain electrode of the PMOS tube M10, respectively, and a source electrode of the PMOS tube M10 is connected to the second end of the second switch tube 32. At this time, if the voltage between the drain and the source of the PMOS transistor M10 is V GS_M10 The second voltage output by the voltage stabilizing circuit is vout=v GS_M8 +V GS_M9 +V GS_M10 +Vx≈3VGS。
In summary, in the voltage stabilizing circuit, the number of the third switching transistors in the switching transistor series group 33 has a certain relationship with the second voltage, so that the magnitude of the output voltage of the voltage stabilizing circuit can be adjusted by selecting the number of the third switching transistors in the switching transistor series group. In practical applications, the number and types of the third switching tubes in the switching tube series group 33 may be set according to practical needs, which is not limited in the above embodiments.
In some embodiments, referring to fig. 4, the second switching tube 32 is a PMOS tube M7. The grid electrode of the PMOS tube M7 is respectively connected with the first end of the first switch tube 31 and the second end of the current mirror module 20, the source electrode of the PMOS tube M7 is connected with the input node IN, and the drain electrode of the PMOS tube M7 is respectively connected with the output node OUT and the switch tube serial group 33.
In the voltage stabilizing circuit, a PMOS tube M7 is used as a load output tube, and the input voltage VIN of an input voltage source at least needs V GS_M8 +V GS_M9 +V dast_p Wherein V is dast_p The overdrive voltage of the PMOS transistor M7 is smaller than that of the NMOS transistor Q4 in FIG. 1, so that the input voltage VIN in FIG. 4 is at least 2VGS+V dast_p In contrast to the input voltage of 3VGS in fig. 1, the present embodiment uses the NMOS Q4 as the load output tube in fig. 1, which makes the circuit suitable for low operating voltages. In addition, in the embodiment, the output current of the output node OUT can be adjusted by adjusting the gate voltage of the PMOS transistor M7 through negative feedback, so as to adjust the second voltage, and keep the second voltage stable.
In some embodiments, referring to fig. 4, the negative feedback output module 30 further includes a capacitor CO. The capacitor CO is connected between the control terminal of the second switching tube 32 and the second terminal of the second switching tube 32. Specifically, the capacitor C0 is connected between the gate of the PMOS transistor M7 and the drain of the PMOS transistor M7.
In the voltage stabilizing circuit, the gain of the negative feedback output module 30 is about gm5 x ros3 x gm7 (1/gm 8+1/gm 9), wherein gm5 is the transconductance of the NMOS transistor M5, gm7 is the transconductance of the PMOS transistor M7, gm8 is the transconductance of the PMOS transistor M8, gm9 is the transconductance of the NMOS transistor M9, ros3 is the output impedance of the PMOS transistor M3, and therefore, the gain of the negative feedback output module 30 is larger, and the accuracy of the output voltage can be improved.
In addition, in the voltage stabilizing circuit, the main pole of the negative feedback output module 30 is the grid electrode Vy of the PMOS transistor, and the main pole formula is: 1/(2 pi ro3 gm7 ro6 c) 0 ) The method comprises the steps of carrying out a first treatment on the surface of the The secondary pole of the negative feedback output module 30 is the output node OUT, and the formula is: gm 7/(2 pi C) 0 )，C 0 For the capacitance value of the capacitor CO, ros6 is the output impedance of the NMOS transistor M6, and since the capacitor CO is a miller capacitor, the primary pole and the secondary pole of the negative feedback output module 30 can be separated, so that the stability is improved, and the working stability of the circuit can be ensured by using the small-sized C0.
In some of these embodiments, referring to fig. 4, the current mirror module 20 includes a first current mirror unit 21 and a second current mirror unit 22. The first end of the first current mirror unit 21 is connected with the input node IN, the second end of the first current mirror unit 21 is connected with the constant current module 10, the third end of the first current mirror unit 21 is connected with the first end of the second current mirror unit 22, the fourth end of the first current mirror unit 21 is connected with the first end of the negative feedback output module 30, the second end of the second current mirror unit 22 is connected with the second end of the negative feedback output module 30, and the third end of the second current mirror unit 22 is connected with the third end of the negative feedback output module 30.
Wherein the first current mirror unit 21 outputs a mirror current to the negative feedback output module 30 and the second current mirror unit 22, respectively, based on the input voltage source and the reference current. The second current mirror unit 22 outputs the first voltage to the negative feedback output module 30 based on the mirror current.
Specifically, the first current mirror unit 21 includes a PMOS current mirror unit or a cascode current mirror unit.
If the first current mirror unit 21 includes a PMOS current mirror unit, referring to fig. 4 and 5, the PMOS current mirror unit includes a PMOS transistor M1, a PMOS transistor M2, and a PMOS transistor M3, sources of the PMOS transistor M1, the PMOS transistor M2, and the PMOS transistor M3 are all connected to the input node IN, drains of the PMOS transistor M1 are respectively connected to the first end of the constant current module 10, a gate of the PMOS transistor M1, a gate of the PMOS transistor M2, and a gate of the PMOS transistor M3, a drain of the PMOS transistor M2 is connected to the first end of the second current mirror unit 22, a drain of the PMOS transistor M3 is connected to the first end of the negative feedback output module 30, and a second end of the constant current module 10 is grounded to GND. In the first current mirror unit 21, the constant current module 10 is configured to generate a reference current flowing through the PMOS transistor M1, and then, the PMOS transistor M2 and the PMOS transistor M3 form mirror images with the PMOS transistor M1, so that the mirror current flowing through the PMOS transistor M2 and the mirror current flowing through the PMOS transistor M3 are consistent with the current of the constant current module 10.
If the first current mirror unit 21 includes a cascode current mirror unit, referring to fig. 6, the cascode current mirror unit includes a PMOS transistor M1, a PMOS transistor M2, a PMOS transistor M3, a PMOS transistor M11, a PMOS transistor M12, and a PMOS transistor M13, sources of the PMOS transistor M1, the PMOS transistor M2, and the PMOS transistor M3 are all connected to the input node IN, drains of the PMOS transistor M1 are respectively connected to sources of the PMOS transistor M11, gates of the PMOS transistor M1, gates of the PMOS transistor M2, and gates of the PMOS transistor M3, drains of the PMOS transistor M2 are connected to sources of the PMOS transistor M12, drains of the PMOS transistor M3 are connected to gates of the PMOS transistor M13, gates of the PMOS transistor M11 are respectively connected to drains of the PMOS transistor M11, gates of the PMOS transistor M12, and a first end of the constant current module 10, drains of the PMOS transistor M12 are connected to a first end of the second current mirror unit 22, drains of the PMOS transistor M13 are connected to a first end of the negative feedback output module 30, and a second end of the constant current module 10 is grounded GND. Similarly, in the first current mirror unit 21, the mirror current flowing through the PMOS transistor M2 and the mirror current flowing through the PMOS transistor M3 are identical to the current of the constant current module 10.
In practical application, a PMOS current mirror unit or a cascode current mirror unit may be used as the first current mirror unit 21 to generate the mirror current, so that the design freedom of the voltage stabilizing circuit is improved.
In addition, the second current mirror unit 22 may include an NMOS current mirror unit. Specifically, referring to fig. 4, the NMOS current mirror unit includes an NMOS transistor M4 and an NMOS transistor M6, wherein the drain of the NMOS transistor M4 is connected to the drain of the PMOS transistor M2, the gate of the NMOS transistor M4, the gate of the NMOS transistor M6 and the gate of the NMOS transistor M5, respectively, the source of the NMOS transistor M4 is grounded GND, the drain of the NMOS transistor M6 is connected to the source of the NMOS transistor M5, and the source of the NMOS transistor M6 is grounded GND. In the second current mirror unit 22, after the NMOS transistor M4 and the NMOS transistor M6 receive the mirror current, a constant first voltage may be provided to the NMOS transistor M5.
The specific circuit structures of the first current mirror unit 21 and the second current mirror unit 22 provided herein can be freely combined and built in application, so that the degree of freedom of design of the voltage stabilizing circuit is improved.
The specific operation of the voltage stabilizing circuit provided by the present application is described in detail below with reference to the embodiment shown in fig. 4.
First, the constant current module 10 generates a mirror current equal to the reference current outputted from the constant current module 10 to the NMOS transistor M5 and V via the first current mirror unit 21 GS_M5 ＞V TH_M5 ≈V TH_M6 ，V DS_M6 =V GS_M6 -V GS_M5 ＜V GS_M6 -V TH_M6 Therefore, the NMOS transistor M6 must operate in the linear region to make the voltage at Vx very low, and the output voltage is vout=v GS_M8 +V GS_M9 +Vx≈V GS_M8 +V GS_M9 The output voltage is still 2VGS, where V GS_M5 Is the gate-source voltage of NMOS tube M5, V TH_M5 Is the gate threshold voltage, V, of the NMOS transistor M5 TH_M6 Is the gate threshold voltage of the NMOS tube M6, V DS_M6 Is the drain-source voltage of NMOS tube M6, V GS_M6 Is the gate-source voltage of the NMOS transistor M6.
It can be seen that the minimum input operating voltage of the voltage stabilizing circuit is about 2VGS+V dsat_p The voltage stabilizing circuit is smaller than the minimum input working voltage of the circuit shown in fig. 1, so that the voltage stabilizing circuit provided by the application is more suitable for working of a low-voltage input power supply, and meanwhile, compared with the circuit shown in fig. 1, the size of an output load tube (NMOS tube Q4) is larger, the size requirement on the output load tube (PMOS tube M7) can be reduced.
In this voltage stabilizing circuit, when the load current suddenly increases, the output voltage at the output node OUT decreases, and the output voltage vout=v GS_M8 +V GS_M9 If +vx, vx also decreases, since the gate voltage of the NMOS transistor M5 is the constant first voltage, the gate-source voltage of the NMOS transistor M5 increases, so the current flowing through the NMOS transistor M5 increases, and the current flowing through the PMOS transistor M3 is the constant mirror current, then the gate voltage of the PMOS transistor M7 decreases, and the source of the PMOS transistor M7 is connected to the input voltage source, so the gate-source voltage of the PMOS transistor M7 increases, resulting in an increase in the current output by the PMOS transistor M7, and thus an increase in the output voltage at the output node OUT. If negativeWhen the load current suddenly decreases, the output voltage on the output node OUT increases, then Vx also increases, since the gate voltage of the NMOS transistor M5 is the first voltage, the gate-source voltage of the NMOS transistor M5 decreases, so that the current flowing through the NMOS transistor M5 decreases, and the current flowing through the PMOS transistor M3 is a constant mirror current, then the gate voltage of the PMOS transistor M7 increases, and the source of the PMOS transistor M7 is connected to the input voltage source, so that the gate-source voltage of the PMOS transistor M7 decreases, resulting in a decrease in the current output by the PMOS transistor M7, thereby decreasing the output voltage on the output node OUT.
Therefore, in the application, the negative feedback loop is added, so that the output voltage of the voltage stabilizing circuit is not changed along with the input voltage and the load current, and the stability of the output voltage is improved.
In a second aspect, an embodiment of the present application provides a power supply device, which includes a voltage stabilizing circuit according to any one of the embodiments of the first aspect. In this embodiment, the voltage stabilizing circuit has the same structure and function as those of the voltage stabilizing circuit according to any one of the embodiments of the first aspect, and will not be described herein. The power supply device can be a voltage stabilizing source, a charger and the like.
It should be noted that the above-described apparatus embodiments are merely illustrative, and the units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting; the technical features of the above embodiments or in the different embodiments may also be combined within the idea of the application, the steps may be implemented in any order, and there are many other variations of the different aspects of the application as described above, which are not provided in detail for the sake of brevity; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.
Claims (10)
1. A voltage regulator circuit having an input node for connection to an input voltage source and an output node for connection to a load, comprising: the device comprises a constant current module, a current mirror module and a negative feedback output module;
the current mirror module is connected with the constant current module and the negative feedback output module, the current mirror module and the negative feedback output module are both connected with the input node, and the negative feedback output module is also connected with the output node;
the constant current module outputs reference current to the current mirror module;
the current mirror module outputs a constant first voltage and mirror current to the negative feedback output module based on the input voltage source and the reference current;
the negative feedback output module provides a second voltage for the load based on the input voltage source, and keeps the second voltage stable according to the first voltage and the mirror current.
2. The voltage regulator circuit of claim 1, wherein the negative feedback output module comprises a first switching tube, a second switching tube, and a switching tube series group comprising at least two third switching tubes connected in series;
the control end of the first switching tube is connected with the first end of the current mirror module, the first end of the first switching tube and the control end of the second switching tube are both connected with the second end of the current mirror module, the second end of the first switching tube is connected with the third end of the current mirror module, the first end of the second switching tube is connected with the input node, the switching tube series group is connected between the second end of the second switching tube and the second end of the first switching tube, and the connection point of the second switching tube and the switching tube series group is also connected with the output node;
the first switching tube adjusts the voltage of the control end of the second switching tube based on the first voltage, the second voltage and the mirror current;
the second switching tube adjusts the second voltage based on the voltage of the control end of the second switching tube and the input voltage source.
3. The voltage stabilizing circuit according to claim 2, wherein the second switching tube is a PMOS tube;
the grid electrode of the PMOS tube is respectively connected with the first end of the first switch tube and the second end of the current mirror module, the source electrode of the PMOS tube is connected with the input node, and the drain electrode of the PMOS tube is respectively connected with the output node and the switch tube series group.
4. A voltage stabilizing circuit according to claim 2 or 3, wherein said negative feedback output module further comprises a capacitor;
the capacitor is connected between the control end of the second switching tube and the second end of the second switching tube.
5. The voltage regulator circuit of claim 4, wherein the at least two third switching tubes connected in series comprise a third a switching tube and a third B switching tube;
the first end of the third A switch tube is connected with the second end of the second switch tube, the control end of the third A switch tube is respectively connected with the second end of the third A switch tube, the control end of the third B switch tube and the first end of the third B switch tube, and the second end of the third B switch tube is respectively connected with the second end of the first switch tube and the third end of the current mirror module.
6. The voltage regulator circuit of claim 5, wherein the at least two third switching tubes connected in series further comprise a third C-switching tube;
the third C switch tube is connected between the second end of the second switch tube and the first end of the third A switch tube.
7. The voltage regulator circuit of claim 1, wherein the current mirror module comprises a first current mirror unit and a second current mirror unit;
the first end of the first current mirror unit is connected with the input node, the second end of the first current mirror unit is connected with the constant current module, the third end of the first current mirror unit is connected with the first end of the second current mirror unit, the fourth end of the first current mirror unit is connected with the first end of the negative feedback output module, the second end of the second current mirror unit is connected with the second end of the negative feedback output module, and the third end of the second current mirror unit is connected with the third end of the negative feedback output module;
the first current mirror unit outputs the mirror current to the negative feedback output module and the second current mirror unit based on the input voltage source and the reference current respectively;
the second current mirror unit outputs the first voltage to the negative feedback output module based on the mirror current.
8. The voltage regulator circuit of claim 7, wherein the first current mirror unit comprises a PMOS current mirror unit or a cascode current mirror unit.
9. The voltage regulator circuit of claim 7, wherein the second current mirror unit comprises an NMOS current mirror unit.
10. A power supply apparatus comprising a voltage stabilizing circuit as claimed in any one of claims 1 to 9.
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| CN116755507B (en) | 2023-12-15 |
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