CN116704968A

CN116704968A - Control method and control system of liquid crystal panel

Info

Publication number: CN116704968A
Application number: CN202310866114.3A
Authority: CN
Inventors: 赵合; 黄炯; 高元元
Original assignee: Hefei Weiguo Semiconductor Co ltd
Current assignee: Hefei Weiguo Semiconductor Co ltd
Priority date: 2023-07-14
Filing date: 2023-07-14
Publication date: 2023-09-05
Anticipated expiration: 2043-07-14
Also published as: CN116704968B

Abstract

The invention provides a control method and a control system of a liquid crystal panel, and relates to the technical field of control of liquid crystal panels. Comprising the following steps: determining an enabling time period of the target function according to a preset vertical synchronous signal and an enabling signal of the target function; adjusting a preset clock signal in an enabling time period to obtain a target clock signal; outputting a target clock signal and a frame start signal corresponding to the vertical synchronous signal through a first output end; and outputting an enabling signal through the second output end so that the level converter determines an enabling time period based on the frame start signal and the enabling signal, starts a target function in the enabling time period, converts a target clock signal under the action of the target function, and generates a clock control signal so as to perform multi-row scanning on the liquid crystal panel. The method comprises the steps of flexibly controlling the starting time period of a target function, changing the charging time of one row of pixels in the liquid crystal panel when the target function is started, and flexibly changing the charging time of one row of pixels in the liquid crystal panel.

Description

Control method and control system of liquid crystal panel

Technical Field

The invention relates to the technical field of control of liquid crystal panels, in particular to a control method and a control system of a liquid crystal panel.

Background

The lcd is an active matrix lcd driven by thin film transistors, and the lcd panel can largely determine the brightness, contrast, color, and viewing angle of the lcd. The higher the refresh rate of the liquid crystal panel, the better the stability of the displayed picture.

In the related art, the charging time for one row in the liquid crystal panel is also different for different refresh rates, for example, the charging time for one row at 120Hz (hertz) refresh rate corresponds to half the charging time for one row of pixels at 60Hz refresh rate, i.e., the charging time is halved. When the charging time of one row of pixels in the liquid crystal panel is shorter as the refresh rate is higher, display abnormality due to insufficient charging of the pixels may occur.

However, in the related art, the charging time of one row of pixels in the liquid crystal panel cannot be flexibly controlled.

Disclosure of Invention

The present invention is directed to a control method and a control system for a liquid crystal panel, which solve the technical problems of the related art.

In order to achieve the above purpose, the technical scheme adopted by the embodiment of the invention is as follows:

in a first aspect, an embodiment of the present invention provides a control method of a liquid crystal panel, applied to a controller, where a first output end in the controller is connected to an input end of a level shifter, a second output end in the controller is connected to an enable end of a target function in the level shifter, and an output end of the level shifter is connected to the liquid crystal panel, the method includes:

Determining an enabling time period of the target function according to a preset vertical synchronous signal and an enabling signal of the target function;

adjusting a preset clock signal in the starting time period to obtain a target clock signal;

outputting the target clock signal and a frame start signal corresponding to the vertical synchronous signal through the first output end;

and outputting the enabling signal through the second output end so that the level converter determines the enabling time period based on the frame starting signal and the enabling signal, starts the target function in the enabling time period, converts the target clock signal under the action of the target function, and generates a clock control signal so as to perform multi-row scanning on the liquid crystal panel.

Optionally, the determining the enabling time period of the target function according to the preset vertical synchronization signal and the enabling signal of the target function includes:

determining an enabling mode of the target function according to a first high level corresponding to a current frame in the vertical synchronous signal, the number of continuous first pulses in the enabling signal after the first high level and the number of continuous second pulses, wherein the second pulses are pulses after the first pulses;

And determining the starting time period according to the starting mode.

Optionally, the determining the enabling mode of the target function according to the first high level corresponding to the current frame in the vertical synchronization signal, and the number of continuous first pulses and the number of continuous second pulses in the enabling signal after the first high level includes:

if the number of the continuous first pulses is a first number and the number of the continuous second pulses is a second number, determining that the starting mode is a first mode;

if the number of the continuous first pulses is the first number and the number of the continuous second pulses is the third number, determining that the enabling mode is a second mode;

if the number of the continuous first pulses is a fourth number and the number of the continuous second pulses is the second number, determining that the enabling mode is a third mode;

and if the number of the continuous first pulses is the fourth number and the number of the continuous second pulses is the third number, determining that the starting mode is a fourth mode.

Optionally, the determining the enabling time period according to the enabling mode includes:

If the enabling mode is the first mode, determining the enabling time period according to the starting time of a first frame and the ending time of a second frame, wherein the first frame is a current frame corresponding to the case that the number of the continuous first pulses is detected to be a first number, and the second frame is a current frame corresponding to the case that the number of the continuous second pulses is detected to be a second number;

if the enabling mode is the second mode, determining the enabling time period according to the starting time of the first frame and the ending time of a third frame, wherein the third frame is the next frame of the current frame corresponding to the detected continuous second pulse number is a third number;

if the enabling mode is the third mode, determining the enabling time period according to the starting time of a fourth frame and the ending time of the second frame, wherein the fourth frame is the next frame of the current frame corresponding to the detected continuous first pulse number is the fourth number;

and if the starting mode is the fourth mode, determining the starting time period according to the starting time of the fourth frame and the ending time of the third frame.

Optionally, the preset clock signal includes: a first clock signal and a second clock signal, the start time intervals of the first clock signal and the second clock signal being preset for a number of time periods;

The adjusting the preset clock signal in the enabling time period to obtain the target clock signal includes:

moving the second clock signal to obtain a moved second clock signal, so that the initial time interval between the first clock signal and the moved second clock signal is smaller than the preset number of time periods;

the target clock signal includes: the first clock signal and the shifted second clock signal.

In a second aspect, an embodiment of the present invention provides a control method of a liquid crystal panel, applied to a level shifter, where a first output terminal in a controller is connected to an input terminal in the level shifter, a second output terminal in the controller is connected to an enable terminal of a target function in the level shifter, and an output terminal of the level shifter is connected to the liquid crystal panel, the method includes:

receiving an enabling signal of the target function sent by the controller through the enabling end;

receiving a target clock signal and a frame start signal sent by the controller through the input end;

determining an enabling time period of the target function according to the enabling signal and the frame starting signal, and starting the target function in the enabling time period;

And under the action of the target function, converting the target clock signal to generate a clock control signal so as to perform multi-line scanning on the liquid crystal panel.

Optionally, the converting the target clock signal under the action of the target function to generate a clock control signal includes:

in the starting time period, performing level conversion processing according to the target clock signal to obtain a plurality of clock control signals with sequence;

and shorting the plurality of output ends of the level shifter, so that the plurality of output ends are divided into at least two groups, and each group of output ends outputs the same clock control signal, wherein each group of output ends consists of a preset number of adjacent output ends.

Optionally, the starting time intervals of the clock control signals output by the two adjacent groups of output ends are one time period, and the one time period is: and the scanning time of the preset number of lines is continuous in the liquid crystal panel.

Optionally, the determining the enabling time period of the target function according to the enabling signal and the frame start signal includes:

determining an enabling mode of the target function according to a first high level corresponding to a current frame in the frame start signal, the number of continuous first pulses in the enabling signal after the first high level and the number of continuous second pulses, wherein the second pulses are pulses after the first pulses;

And determining the starting time period according to the starting mode.

In a third aspect, an embodiment of the present application provides a control system for a liquid crystal panel, including: the liquid crystal display device comprises a controller and a level shifter, wherein a first output end in the controller is connected with an input end in the level shifter, a second output end in the controller is connected with an enabling end of a target function in the level shifter, and an output end of the level shifter is connected with a liquid crystal panel;

wherein the controller is configured to execute the control method of the liquid crystal panel according to any one of the first aspect, and the level shifter is configured to execute the control method of the liquid crystal panel according to any one of the second aspect.

The beneficial effects of the application are as follows: the embodiment of the application provides a control method of a liquid crystal panel, which comprises the following steps: determining an enabling time period of the target function according to a preset vertical synchronous signal and an enabling signal of the target function; adjusting a preset clock signal in an enabling time period to obtain a target clock signal; outputting a target clock signal and a frame start signal corresponding to the vertical synchronous signal through a first output end; and outputting an enabling signal through the second output end so that the level converter determines an enabling time period based on the frame start signal and the enabling signal, starts a target function in the enabling time period, converts a target clock signal under the action of the target function, and generates a clock control signal so as to perform multi-row scanning on the liquid crystal panel. The level shifter determines the starting time period of the target function according to the enabling signal and the frame starting signal sent by the controller, so that the flexible control of the starting time period of the target function can be realized, the liquid crystal panel is controlled based on the clock control signal output by the level shifter under the action of the target function, and the charging time of one row of pixels in the liquid crystal panel can be changed, so that the flexible change of the charging time of one row of pixels in the liquid crystal panel is realized.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a control system of a liquid crystal panel according to an embodiment of the present application;

fig. 2 is a schematic flow chart of a control method of a liquid crystal panel according to an embodiment of the present application;

fig. 3 is a flow chart diagram II of a control method of a liquid crystal panel according to an embodiment of the present application;

FIG. 4a is a schematic diagram I of an enabling mode of a target function according to an embodiment of the present application;

FIG. 4b is a schematic diagram II of an enabling mode of a target function according to an embodiment of the present application;

fig. 5 is a flowchart illustrating a control method of a liquid crystal panel according to an embodiment of the present application;

fig. 6 is a flow chart diagram of a control method of a liquid crystal panel according to an embodiment of the present application;

Fig. 7 is a flowchart of a control method of a liquid crystal panel according to an embodiment of the present application;

FIG. 8 is a timing diagram of signals when a target function is not activated according to an embodiment of the present application;

FIG. 9 is a timing diagram of signals at the start of a target function according to an embodiment of the present application;

FIG. 10 is a schematic diagram of signal timing before and after starting a target function according to an embodiment of the present application;

FIG. 11 is a schematic diagram of signal timing before and after starting a first mode target function according to an embodiment of the present application;

FIG. 12 is a schematic diagram showing signal timing before and after starting a target function in a second mode according to an embodiment of the present application;

FIG. 13 is a schematic diagram showing signal timing before and after the third mode target function is started according to the embodiment of the present application;

FIG. 14 is a schematic diagram showing signal timing before and after the fourth mode target function is activated according to the embodiment of the present application;

fig. 15 is a schematic structural diagram of a control device for a liquid crystal panel according to an embodiment of the present application;

fig. 16 is a schematic diagram of a control device for a liquid crystal panel according to an embodiment of the application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application.

Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

In the description of the present application, it should be noted that, if the terms "upper", "lower", and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or an azimuth or the positional relationship conventionally put in use of the product of the application, it is merely for convenience of describing the present application and simplifying the description, and it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present application.

Furthermore, the terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It should be noted that the features of the embodiments of the present application may be combined with each other without conflict.

Fig. 1 is a schematic structural diagram of a control system of a liquid crystal panel according to an embodiment of the present application, as shown in fig. 1, where the control system of the liquid crystal panel includes: a controller 101 and a level shifter 102;

wherein a first output terminal of the controller 101 is connected to an input terminal of the level shifter 102, a second output terminal of the controller 101 is connected to an enable terminal of a target function of the level shifter 102, and an output terminal of the level shifter 102 is connected to the liquid crystal panel 103.

In this embodiment of the present application, the first output end and the second output end may be I/O (input/output) ports in the controller 101, the number of the second output ends may be one, the controller 101 outputs an enable signal to the enable end of the level shifter 102 through the second output end, the number of the first output ends may be at least one, and the controller 101 outputs a target clock signal and a frame start signal corresponding to the vertical synchronization signal to the level shifter 102 through the at least one first output end.

The second output terminal is connected to the enable terminal of the level shifter 102 through a connection line, and the first output terminal is also connected to the input terminal of the level shifter 102 through a connection line. The controller 101 may also be referred to as Tcon (Timing Controller, timing controller 101), and the Level Shifter 102 may also be referred to as Level Shifter.

It should be noted that, the second output terminal in the controller 101 is connected to the enabling terminal of the target function in the level shifter 102, so that the controller 101 can flexibly control the on/off of the target function, flexibly change the clock control signal output by the level shifter 102, and further, the level shifter 102 can flexibly control the charging time of a row of pixels in the liquid crystal panel based on the clock control signal, and the specific implementation process can refer to the following related content of the control method of the liquid crystal panel 103.

The embodiment of the application also provides a control method of the liquid crystal panel, which is applied to the controller 101 in the control system of the liquid crystal panel, and the control method of the liquid crystal panel provided by the embodiment of the application is explained below.

Fig. 2 is a schematic flow chart of a control method of a liquid crystal panel according to an embodiment of the present application, as shown in fig. 2, the method may include:

s101, determining an enabling time period of the target function according to a preset vertical synchronous signal and an enabling signal of the target function.

The vertical synchronization signal may also be referred to as a VSync (Vertical Synchronization ) signal, and the enable signal may include a plurality of high levels.

In some embodiments, the start time and the end time of the target function may be determined according to the number and the sequence between the high levels in the vertical synchronization signal and the plurality of high levels in the enable signal, and a period between the start time and the end time may be taken as the enabled period of the target function.

It should be noted that, the enabled period of the target function may be a period corresponding to when scanning is performed for at least one target frame.

S102, adjusting a preset clock signal in an enabling time period to obtain a target clock signal.

In the embodiment of the present application, the preset clock signal may include a plurality of clock signals, and the adjusting is performed on a part of the clock signals in the preset clock signal to obtain an adjusted part of the clock signals, where the target clock signal may include: the adjusted partial clock signal and the remaining clock signals of the plurality of clock signals excluding the partial clock signal.

It should be noted that, the target clock signal is output to the level shifter during the enabled period of the target function, and the preset clock signal may be output to the level shifter when the target function is not started.

S103, outputting a target clock signal and a frame start signal corresponding to the vertical synchronous signal through a first output end.

The waveforms corresponding to the frame start signal and the vertical synchronization signal are similar, and the frame start signal may be considered as the vertical synchronization signal input to the level shifter, and the frame start signal may be also referred to as the STV signal.

It should be noted that, in the enabling period of the target function, the controller outputs the target clock signal and the frame start signal corresponding to the vertical synchronization signal to the input end of the level shifter through the first output end, and then the level shifter may acquire the target clock signal and the frame start signal.

In addition, in the period that the target function is not started, the controller outputs a preset clock signal and a frame start signal corresponding to the vertical synchronization signal to the input end of the level shifter through the first output end.

S104, outputting an enabling signal through the second output end so that the level converter determines an enabling time period based on the frame starting signal and the enabling signal, starts a target function in the enabling time period, converts a target clock signal under the action of the target function, and generates a clock control signal so as to perform multi-row scanning on the liquid crystal panel.

The controller outputs an enabling signal to an enabling end of the level shifter through a second output end; the level shifter may determine the enable period according to the frame start signal and the enable signal, and it should be noted that the process of determining the enable period by the level shifter frame start signal and the enable signal is similar to the process of determining the enable period by the controller according to the vertical synchronization signal and the enable signal.

In some embodiments, the level shifter turns on the target function during the enabling time period, and when the target function is turned on, the first rule is used to convert the target clock signal to generate a first clock control signal; and the level converter converts the preset clock signal by adopting a second rule in a time period when the target function is not started, and generates a second clock control signal.

In practical application, the level shifter needs to sequentially perform multi-frame line scanning on the liquid crystal panel, and performs line scanning on the liquid crystal panel for a target frame according to a first clock control signal; and performing line scanning on the liquid crystal panel for the rest frames according to the second clock control signal, wherein the charging time of one line of pixels in the liquid crystal panel when the liquid crystal panel performs line scanning on the target frame is different from the charging time of one line of pixels in the liquid crystal panel when the liquid crystal panel performs line scanning on the rest frames. The target frame may be any continuous at least one frame of the multiple frames, and the remaining frames may be frames of the multiple frames other than the target frame.

For example, if the liquid crystal panel displays at a first refresh rate during a first period of time, the liquid crystal panel displays at a second refresh rate during a second period of time. The charging time of one row of pixels of the liquid crystal panel is X1, so that the liquid crystal panel can be ensured to normally display at a first refresh rate; the charging time of one row of pixels of the liquid crystal panel is X2, so that the liquid crystal panel can be ensured to display normally under the second refresh rate. When the target function is not started, the charging time of one row of pixels of the liquid crystal panel is X1, and when the target function is started, the charging time of one row of pixels of the liquid crystal panel is X2, and the starting time period of the target function can be a second time period.

It should be noted that, the on period of the target function is determined according to the preset vertical synchronization signal and the enable signal of the target function, and the enable signal of the target function may be preset according to the timing of the change of the refresh rate, so that the on period of the target function is related to the timing of the change of the refresh rate, thereby implementing that the target function is started when the refresh rate is changed, and the target function is closed when the refresh rate is restored to the original refresh rate.

In summary, an embodiment of the present application provides a method for controlling a liquid crystal panel, including: determining an enabling time period of the target function according to a preset vertical synchronous signal and an enabling signal of the target function; adjusting a preset clock signal in an enabling time period to obtain a target clock signal; outputting a target clock signal and a frame start signal corresponding to the vertical synchronous signal through a first output end; and outputting an enabling signal through the second output end so that the level converter determines an enabling time period based on the frame start signal and the enabling signal, starts a target function in the enabling time period, converts a target clock signal under the action of the target function, and generates a clock control signal so as to perform multi-row scanning on the liquid crystal panel. The level shifter determines the starting time period of the target function according to the enabling signal and the frame starting signal sent by the controller, so that the flexible control of the starting time period of the target function can be realized, the liquid crystal panel is controlled based on the clock control signal output by the level shifter under the action of the target function, and the charging time of one row of pixels in the liquid crystal panel can be changed, so that the flexible change of the charging time of one row of pixels in the liquid crystal panel is realized.

And moreover, the controller outputs an enabling signal to the enabling end of the level shifter through the second output end, the mode of connection between the second output end of the controller and the enabling end of the level shifter is single-wire connection, the enabling target function can be controlled efficiently, the influence of time delay is reduced, and the display effect of higher refresh rate is achieved.

Optionally, fig. 3 is a second flowchart of a control method of a liquid crystal panel according to an embodiment of the present application, as shown in fig. 3, a process of determining an enabling time period of a target function according to a preset vertical synchronization signal and an enabling signal of the target function in S101 may include:

s201, determining an enabling mode of a target function according to a first high level corresponding to a current frame in the vertical synchronous signal, the number of continuous first pulses in the enabling signal after the first high level and the number of continuous second pulses.

Wherein the second pulse is a pulse subsequent to the first pulse.

In some embodiments, determining a start time of the target function based on a number of consecutive first pulses in the enable signal after the first high level; and determining the termination time of the target function according to the number of continuous second pulses in the enabling signal after the first high level, and determining the enabling mode of the target function according to the starting time and the termination time of the target function.

S202, determining an enabling time period according to the enabling mode.

It should be noted that, different enabling modes correspond to different enabling time periods, and the enabling time periods are time periods of performing multi-line scanning with respect to the target frame.

In summary, the enabling mode of the target function is determined according to the vertical synchronization signal and the enabling signal of the target function, and the enabling time period is determined according to the enabling mode, so that the determining process of the enabling time period is more flexible.

Optionally, the step of determining the enabling mode of the target function in S201 according to the first high level corresponding to the current frame in the vertical synchronization signal, and the number of continuous first pulses and the number of continuous second pulses in the enabling signal after the first high level may include:

if the number of the continuous first pulses is the first number and the number of the continuous second pulses is the third number, determining that the starting mode is the second mode;

if the number of the continuous first pulses is the fourth number and the number of the continuous second pulses is the second number, determining that the starting mode is a third mode;

If the number of the continuous first pulses is the fourth number and the number of the continuous second pulses is the third number, determining that the enabling mode is the fourth mode.

In the embodiment of the application, different values can be respectively set for the first quantity, the second quantity, the third quantity and the fourth quantity according to actual requirements.

For example, the first number may be 1, the second number may be 3, the third number may be 4, and the fourth number may be 2, and of course, the first number, the second number, the third number, and the fourth number may be other different values, which are not particularly limited in the embodiment of the present application.

Alternatively, the first pulse may be at the second high level, and the second pulses may each be at the third high level.

FIG. 4a is a schematic diagram of a first mode for enabling a target function according to an embodiment of the present application, as shown in FIG. 4a, the number of consecutive second high levels is 1, and the number of consecutive third high levels is 3, and the enabled mode is a first mode; the number of the continuous second high levels is 1, the number of the continuous third high levels is 4, and the enabling mode is the second mode; the number of the continuous second high levels is 2, the number of the continuous third high levels is 3, and the enabling mode is a third mode; the number of consecutive second high levels is 2, and the number of consecutive third high levels is 4, the enabling mode being the fourth mode.

Alternatively, the first pulse may be at a first low level, and the second pulse may be at a second low level.

FIG. 4b is a schematic diagram II of an enabling mode of a target function according to an embodiment of the present application, as shown in FIG. 4b, the number of consecutive first low levels is 1, and the number of consecutive second low levels is 3, and the enabling mode is the first mode; the number of continuous first low levels is 1, the number of continuous second low levels is 4, and the enabling mode is a second mode; the number of continuous first low levels is 2, the number of continuous second low levels is 3, and the enabling mode is a third mode; the number of consecutive first low levels is 2, and the number of consecutive second low levels is 4, and the enabling mode is the fourth mode.

Wherein a high level in the vertical synchronization signal indicates a start signal of a frame.

In some embodiments, the controller may have a preset correspondence, where the preset correspondence is used to characterize a correspondence between a plurality of sets of preset numbers, preset modes, and an enabling time period, and search a set of preset numbers matching the number of the first pulses and the number of the second pulses from the plurality of sets of preset numbers, and use a preset mode corresponding to the preset number as an enabling mode of the target function.

Optionally, the determining the enabling time period in S202 according to the enabling mode may include:

if the starting mode is the first mode, determining a starting time period according to the starting time of the first frame and the ending time of the second frame, wherein the first frame is a current frame corresponding to the condition that the number of the continuous first pulses is detected to be the first number, and the second frame is a current frame corresponding to the condition that the number of the continuous second pulses is detected to be the second number;

if the starting mode is the second mode, determining a starting time period according to the starting time of the first frame and the ending time of a third frame, wherein the third frame is the next frame of the current frame corresponding to the detected continuous second pulse number is the third number;

if the starting mode is the third mode, determining a starting time period according to the starting time of a fourth frame and the ending time of a second frame, wherein the fourth frame is the next frame of the current frame corresponding to the condition that the number of the continuous first pulses is detected to be the fourth number;

if the enabling mode is the fourth mode, determining an enabling time period according to the starting time of the fourth frame and the ending time of the third frame.

In the embodiment of the application, after determining the starting time period, the controller can adjust the preset clock signal in the starting time period to obtain the target clock signal; the target clock signal is input to the level shifter in the enabling time period, so that the level shifter can perform level shifting based on the target clock signal after the target function is started in the enabling time period, and the clock control signal is output.

In addition, the enabling time period determined by the level shifter is the same as the enabling time period determined by the controller, and the level shifter may determine the enabling mode according to the enabling time period.

In some embodiments, if the enabled mode is the first mode, the level shifter initiates the target function in a first frame and terminates the target function in a second frame; if the enabling mode is the second mode, enabling the target function by the level shifter in the first frame and terminating the target function in the third frame; if the enabling mode is the third mode, enabling the target function by the level shifter in the fourth frame and terminating the target function in the second frame; if the enabling mode is the fourth mode, the level shifter enables the target function in the fourth frame and terminates the target function in the third frame.

Optionally, the preset clock signal includes: the first clock signal and the second clock signal, the initial time interval of the first clock signal and the second clock signal is preset for a plurality of time periods;

in the step S102, the process of adjusting the preset clock signal in the enabling time period to obtain the target clock signal may include:

moving the second clock signal to obtain a moved second clock signal, so that the initial time interval between the first clock signal and the moved second clock signal is smaller than a preset number of time periods;

Wherein the target clock signal comprises: a first clock signal and a shifted second clock signal. The first clock signal may be represented by CPV1 and the second clock signal may be represented by CPV 2.

In the embodiment of the application, the second clock signal is moved forward to obtain the moved second clock signal, and the initial time interval between the moved second clock signal and the first clock signal is shortened. A time period may be one high level and one low level in succession in the first clock signal.

For example, the start times of the first clock signal and the second clock signal are 4 time periods apart, and the start times of the first clock signal and the shifted second clock signal are 2 time periods apart.

The embodiment of the application also provides a control method of the liquid crystal panel, which is applied to the level shifter 102 in the control system of the liquid crystal panel, and the control method of the liquid crystal panel provided by the embodiment of the application is explained below.

Fig. 5 is a flow chart III of a control method of a liquid crystal panel according to an embodiment of the present application, as shown in fig. 5, the method may include:

s301, receiving an enabling signal of the target function sent by the controller through an enabling end.

The controller outputs an enabling signal to an enabling end of the level shifter through a second output end, and the level shifter receives the enabling signal of the target function sent by the controller through the enabling end.

S302, receiving a target clock signal and a frame start signal sent by a controller through an input end.

In some embodiments, the controller determines an enabling time period of the target function according to the preset vertical synchronization signal and the enabling signal of the target function, and in the enabling time period, the controller outputs the target clock signal and a frame start signal corresponding to the vertical synchronization signal to an input end of the level shifter through the first output end, and the level shifter receives the target clock signal and the frame start signal sent by the controller through the input end.

It should be noted that, in the enabling period of the target function, the controller continuously outputs the target clock signal and the frame start signal to the input end of the level shifter through the first output end, and in the period of the target function not being started, the controller outputs the preset clock signal and the frame start signal to the input end of the level shifter through the first output end.

S303, determining an enabling time period of the target function according to the enabling signal and the frame start signal, and starting the target function in the enabling time period.

Wherein waveforms corresponding to the frame start signal and the vertical synchronization signal are similar.

In some embodiments, the start time and the end time of the target function may be determined according to the number and the sequence between the plurality of high levels in the frame start signal and the plurality of high levels in the enable signal, and a time period between the start time and the end time is taken as the enabling time period of the target function.

In addition, the level shifter turns on the target function for the enabled period.

S304, converting the target clock signal under the action of the target function to generate a clock control signal so as to perform multi-line scanning on the liquid crystal panel.

The level shifter may also output a frame start signal.

In the embodiment of the application, under the action of a target function, a first rule is adopted to convert a target clock signal to generate a first clock control signal; and in the time period when the target function is not started, converting the preset clock signal by adopting a second rule to generate a second clock control signal. The first rule and the second rule are different rules.

In practical application, the level shifter needs to sequentially perform multi-frame line scanning on the liquid crystal panel, and performs line scanning on the liquid crystal panel for a target frame according to a first clock control signal; and performing line scanning on the liquid crystal panel for the rest frames according to the second clock control signal, wherein the refresh rate of the display target frame of the liquid crystal panel is different from the refresh rate of the display rest frames. The target frame may be any continuous at least one frame of the multiple frames, and the remaining frames may be frames of the multiple frames other than the target frame.

In summary, an embodiment of the present application provides a method for controlling a liquid crystal panel, including: receiving an enabling signal of a target function sent by the controller through an enabling terminal; receiving a target clock signal and a frame start signal sent by a controller through an input end; determining an enabling time period of the target function according to the enabling signal and the frame starting signal, and starting the target function in the enabling time period; under the action of the target function, the target clock signal is converted to generate a clock control signal so as to perform multi-line scanning on the liquid crystal panel. The level shifter determines the starting time period of the target function according to the enabling signal and the frame starting signal sent by the controller, so that the flexible control of the starting time period of the target function can be realized, the liquid crystal panel is controlled based on the clock control signal output by the level shifter under the action of the target function, and the charging time of one row of pixels in the liquid crystal panel can be changed, so that the flexible change of the charging time of one row of pixels in the liquid crystal panel is realized.

Optionally, fig. 6 is a flowchart of a control method of a liquid crystal panel according to an embodiment of the present application, as shown in fig. 6, in S303, determining an enabling time period of a target function according to an enabling signal and a frame start signal includes:

s401, determining an enabling mode of a target function according to a first high level corresponding to a current frame in a frame start signal, the number of continuous first pulses in an enabling signal after the first high level and the number of continuous second pulses.

Wherein the second pulse is a pulse subsequent to the first pulse.

In the embodiment of the present application, if the number of continuous first pulses is a first number and the number of continuous second pulses is a second number, determining that the enabling mode is a first mode;

S402, determining an enabling time period according to the enabling mode.

If the enabling mode is the first mode, determining an enabling time period according to a start time of a first frame and a stop time of a second frame, wherein the first frame is a current frame corresponding to the case that the number of the continuous first pulses is detected to be the first number, and the second frame is a current frame corresponding to the case that the number of the continuous second pulses is detected to be the second number;

Fig. 7 is a flowchart fifth of a control method of a liquid crystal panel according to an embodiment of the present application, as shown in fig. 7, a process of converting a target clock signal to generate a clock control signal under the effect of a target function in S304 may include:

S501, performing level conversion processing according to a target clock signal in an enabling time period to obtain a plurality of clock control signals with sequence.

In the multiple clock control signals with the sequence, the starting time of two adjacent clock control signals can be separated by a time period, and one time period corresponds to one high level and one low level in succession in the first clock signal.

In addition, the plurality of clock control signals are respectively output by a plurality of output ends of the level shifter, and each output end can output one clock control signal.

S502, shorting the plurality of output ends of the level converter, so that the plurality of output ends are divided into at least two groups, and each group of output ends outputs the same clock control signal.

Wherein each group of output ends is composed of a preset number of adjacent output ends.

In the embodiment of the application, each group of output ends outputs adjacent preset number of clock control signals, and each group of output ends outputs the same starting time and the same waveform of the clock control signals. The number of the preset units may be 2 or 4, or of course, may be other number, which is not limited in particular in the embodiment of the present application.

It should be noted that, the plurality of output terminals are divided into at least two groups, and the output terminals divided into the same group are shorted, so that the clock control signals output by the output terminals of each group are the same.

Optionally, the starting time intervals of the clock control signals output by the two adjacent groups of output ends are one time period, and one time period is: the scanning time of a predetermined number of lines is continuously performed in the liquid crystal panel.

Wherein a time period may correspond to a high level and a low level in succession in the first clock signal.

In addition, if the preset number is 2, each group of output ends outputs two identical clock control signals, one continuous high level and one continuous low level in the first clock signal correspond to the scanning time of 2 continuous lines in the crystal display screen; if the preset number is 4, each group of output ends outputs four identical clock control signals, and one high level and one low level in the first clock signal correspond to the scanning time of 4 continuous lines in the crystal display screen.

In the embodiment of the present application, the target function may also be referred to as a DLG (Dual Line Gate) function, and the enable signal of the target function may also be referred to as a dlg_en.

In a period of time when the target function is not started, the DLG_EN does not have the first pulse and the second pulse, and the controller outputs a preset clock signal and an enabling signal to the level shifter, wherein the preset clock signal comprises: fig. 8 is a timing diagram of a signal when a target function is not started, as shown in fig. 8, STV1 represents a frame start signal, CPV1 represents a first clock signal, CPV2 represents a second clock signal, the first clock signal and the second clock signal are separated by 4 time periods, and dlg_en is a continuous low level. The STV1-G represents a frame start signal output from the level shifter, and the first clock control signal output from the level shifter may include: CLK1-G, CLK2-G, CLK3-G, CLK4-G, CLK5-G, CLK6-G, CLK7-G, CLK8-G.

In some embodiments, during the period when the target function is not turned on, the refresh rate of the liquid crystal panel may be 60 hertz (Hz), and the resolution is: 3840X2160 (number of horizontal pixels X number of vertical pixels), as shown in fig. 8, one CLK period in each first clock control signal is 8H, the duty ratio is 50 percent, and the charging time of one row of pixels is 1H for a 60Hz panel, where 1 h=1/(refresh_rate)Htotal), where refresh_rate represents the Refresh rate, refresh_rate=60 hz, htotal is the required horizontal scan line in a frame plus the relative horizontal scan line time required for controller processing, for example 2160 for a frame, and htotal=2160+90=2250 for controller processing.

It should be noted that, taking a 60hz refresh rate as an example, 1h=7.4 us (microseconds), that is, the time required for scanning one line is 7.4us, as shown in fig. 8, one period of time (one high level and one low level in succession in the first clock signal CPV 1) corresponds to the scanning time 1H of one line in the liquid crystal panel. The refresh rate corresponding to fig. 8 is 60 hz.

FIG. 9 is a timing diagram of signals at the start of a target function, 1H at 60Hz and 1H at 120 Hz, according to an embodiment of the present application With different definition time, if 120 Hz is used as refresh rate, charging time of one row of pixels in the liquid crystal panel is 1H +.>1/(120 × in)>2250 =3.7 us, which is one half of the charge time of each row at 60 hz, if 120 hz is to be used as refresh rate, as shown in fig. 9, oneA time period (one high level and one low level in succession in the first clock signal CPV 1) corresponding to a scanning time 2H ∈ of 2 rows in succession in the liquid crystal panel>=7.4 us, each with sufficient charge time is guaranteed at a refresh rate of 120 hz.

In the embodiment of the present application, when the target function is turned on, the charging time of a row of pixels of the liquid crystal panel can be changed, if the refresh rate of the liquid crystal panel is to be increased from 60 hz to 120 hz, after the target function is turned on, shorting can be performed on every two adjacent ports, and the second clock control signal output by the level shifter can include: waveform, start time identical CLK2-G and CLK1-G, waveform, start time identical CLK4-G and CLK3-G, waveform, start time identical CLK6-G and CLK5-G, waveform and start time identical CLK8-G and CLK7-G. The liquid crystal display is controlled based on the second clock signal, so that the charging time of one row of pixels of the liquid crystal panel is changed, the display effect of the liquid crystal panel is better under 120 Hz, and the problem that the display of the liquid crystal panel is abnormal due to the fact that the charging time of one row of pixels is insufficient when the refresh rate of the liquid crystal panel is changed from 60 Hz to 120 Hz is avoided. The first pulse may be at a second high level, as shown in fig. 9, and the number of consecutive second high levels is 2, and the target function is turned on in the next frame of the current frame.

During a start-up period of the target function, the controller outputs a target clock signal and an enable signal to the level shifter, the target clock signal including: the first clock signal and the shifted second clock signal, as shown in fig. 9, STV1 represents a frame start signal, CPV1 represents the first clock signal, CPV3 represents the shifted second clock signal, STV1-G represents a frame start signal output from the level shifter, a space between CPV1 and CPV3 is 2 time periods, after the target function is started, the waveforms and the starting time of the CLK2-G and the CLK1-G are the same, the waveforms and the starting time of the CLK4-G and the CLK3-G are the same, the waveforms and the starting time of the CLK6-G and the CLK5-G are the same, and the waveforms and the starting time of the CLK8-G and the CLK7-G are the same. Wherein CLK1-G and CLK3-G are spaced one apartFor a period of time, i.e. 2HAlso, the CLK5-G and the CLK3-G are separated by a time period, the CLK7-G and the CLK5-G are separated by a time period, and one CLK period in each second clock control signal is 8H +>The duty cycle is 50 percent and the refresh rate corresponding to fig. 9 is 120 hz.

Fig. 10 is a schematic signal timing diagram before and after starting a target function according to an embodiment of the present application, as shown in fig. 10, before the target function is not started, 4 time periods are separated between the first clock signal CPV1 and the second clock signal CPV2, 1 time period (continuous one high level and low level in CPV 1) corresponds to a charging time of 1H (i.e. charging 1 row of the liquid crystal panel in 1 time period), and the level shifter outputs 8 first clock control signals: CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, CLK8, each adjacent two first clock control signals are separated by a time period. The refresh rate of the liquid crystal panel is 60 Hz, and the target function is not started. The first pulse may be a second high level, as shown in fig. 10, the number of consecutive second high levels being 2, and the target function is turned on in the next frame of the current frame.

As shown in fig. 10, after the target function is started, the first clock signal CPV1 and the second clock signal CPV3 are separated by 2 time periods, and the charging time corresponding to 1 time period (one continuous high level and low level in CPV 1) is 2H(i.e., charge 2 rows of the liquid crystal panel in 1 time period), the level shifter outputs 8 second clock control signals: CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, CLK8, include: CLK2 and CLK1 with the same waveform, CLK4 and CLK3 with the same start time, CLK6 and CLK5 with the same waveform, start time, and CLK8 and CLK7 with the same waveform and start time. Wherein the waveforms of CLK2 and CLK1 startThe start time is the same, the waveforms and start times of CLK4 and CLK3 are the same, the waveforms and start times of CLK6 and CLK5 are the same, and the waveforms and start times of CLK8 and CLK7 are the same. Wherein CLK1 and CLK3 are separated by a time period, CLK5 and CLK3 are also separated by a time period, and CLK7-G and CLK5-G are also separated by a time period. In the starting time period of the target function, the charging time of one row of pixels of the liquid crystal panel is changed, the display effect of the liquid crystal panel is ensured to be smoother under 120 Hz, and the problem that the charging time of one row of pixels is insufficient when the refresh rate of the liquid crystal panel is changed from 60 Hz to 120 Hz, so that the display of the liquid crystal panel is abnormal is avoided.

It should be noted that the architecture based on fig. 8 to 10 is an architecture in which the level shifter outputs 8 clock control signals, and the method provided by the embodiment of the present application is also applicable to an architecture in which the level shifter outputs 6 clock control signals, 10 clock control signals, and 12 clock control signals, which is not particularly limited in the embodiment of the present application.

In summary, in the above-mentioned process, when the refresh rate of the liquid crystal panel is originally 60 hz, if the refresh rate of the liquid crystal panel is increased to 120 hz, the target function is started, and in the enabling time period of the target function, the charging time of one row of pixels of the liquid crystal panel is changed, so that the liquid crystal panel can be ensured to be normally displayed at 120 hz, however, the above-mentioned processes of fig. 8 to 10 are only an example, and in the embodiment of the present application, the charging time of one row of pixels of the liquid crystal panel can be controlled to be changed differently according to different refresh rates, which is related to the number of time periods of the start time interval of the first clock signal and the second clock signal after movement, and the number of clock control signals with the same waveform and start time output by each group.

Fig. 11 is a schematic signal timing diagram before and after starting a target function in a first mode according to an embodiment of the present application, as shown in fig. 11, for the first mode, the number of consecutive second high levels is 1, the target function is started in a current frame (first frame) corresponding to the consecutive second high levels, the number of consecutive third high levels is 3, and the target function is terminated in a current frame (second frame) corresponding to the consecutive third high levels.

Fig. 12 is a schematic signal timing diagram before and after starting a target function in a second mode according to an embodiment of the present application, as shown in fig. 12, for the second mode, the number of consecutive second high levels is 1, the target function is started in a current frame (first frame) corresponding to the consecutive second high levels, the number of consecutive third high levels is 4, and the target function is terminated in a next frame (third frame) corresponding to the current frame corresponding to the consecutive third high levels.

Fig. 13 is a schematic signal timing diagram before and after starting a target function in a third mode according to an embodiment of the present application, as shown in fig. 13, for the third mode, the number of consecutive second high levels is 2, the target function is started in the next burst (fourth frame) of the current frame corresponding to the consecutive second high levels, the number of consecutive third high levels is 3, and the target function is terminated in the current frame (second frame) corresponding to the consecutive third high levels.

Fig. 14 is a schematic signal timing diagram before and after starting a target function in a fourth mode according to an embodiment of the present application, as shown in fig. 14, for the fourth mode, the number of consecutive second high levels is 2, the target function is started in the next burst (fourth frame) of the current frame corresponding to the consecutive second high levels, the number of consecutive third high levels is 4, and the target function is terminated in the next frame (third frame) of the current frame corresponding to the consecutive third high levels.

The following describes a control device, a controller, a storage medium, etc. of a liquid crystal panel for executing the control method of a liquid crystal panel provided by the present application, and specific implementation processes and technical effects thereof are referred to in the relevant content of the control method of a liquid crystal panel, and are not described in detail below.

Fig. 15 is a schematic structural diagram of a control device for a liquid crystal panel according to an embodiment of the present application, where the device is applied to a controller, a first output terminal in the controller is connected to an input terminal of a level shifter, a second output terminal in the controller is connected to an enable terminal of a target function in the level shifter, and an output terminal of the level shifter is connected to the liquid crystal panel, as shown in fig. 15, and the device includes:

a determining module 1101, configured to determine an enabling time period of the target function according to a preset vertical synchronization signal and an enabling signal of the target function;

an adjustment module 1102, configured to adjust a preset clock signal in the enabling time period to obtain a target clock signal;

an output module 1103, configured to output, through the first output terminal, the target clock signal and a frame start signal corresponding to the vertical synchronization signal; and outputting the enabling signal through the second output end so that the level converter determines the enabling time period based on the frame starting signal and the enabling signal, starts the target function in the enabling time period, converts the target clock signal under the action of the target function, and generates a clock control signal so as to perform multi-row scanning on the liquid crystal panel.

Optionally, the determining module 1101 is specifically configured to determine, according to a first high level corresponding to a current frame in the vertical synchronization signal, a number of continuous first pulses in the enable signal after the first high level, and a number of continuous second pulses, where the second pulses are pulses after the first pulses, an enabling mode of the target function; and determining the starting time period according to the starting mode.

Optionally, the determining module 1101 is specifically configured to determine that the enabling mode is the first mode if the number of the continuous first pulses is the first number and the number of the continuous second pulses is the second number; if the number of the continuous first pulses is the first number and the number of the continuous second pulses is the third number, determining that the enabling mode is a second mode; if the number of the continuous first pulses is a fourth number and the number of the continuous second pulses is the second number, determining that the enabling mode is a third mode; and if the number of the continuous first pulses is the fourth number and the number of the continuous second pulses is the third number, determining that the starting mode is a fourth mode.

Optionally, the determining module 1101 is specifically configured to determine, if the enabling mode is the first mode, the enabling time period according to a start time of a first frame and a stop time of a second frame, where the first frame is a current frame corresponding to when the number of continuous first pulses is detected to be the first number, and the second frame is a current frame corresponding to when the number of continuous second pulses is detected to be the second number;

the adjusting module 1102 is specifically configured to move the second clock signal to obtain a moved second clock signal, so that an initial time interval between the first clock signal and the moved second clock signal is smaller than the preset number of time periods; the target clock signal includes: the first clock signal and the shifted second clock signal.

Fig. 16 is a schematic diagram of a second structure of a control device for a liquid crystal panel according to an embodiment of the present application, where the device is applied to a level shifter, a first output terminal in a controller is connected to an input terminal in the level shifter, a second output terminal in the controller is connected to an enable terminal of a target function in the level shifter, and an output terminal of the level shifter is connected to the liquid crystal panel, as shown in fig. 16, the device includes:

a receiving module 1201, configured to receive, by using the enabling terminal, an enable signal of the target function sent by the controller; receiving a target clock signal and a frame start signal sent by the controller through the input end;

A determining module 1202, configured to determine an enabling time period of the target function according to the enabling signal and the frame start signal, and turn on the target function in the enabling time period;

the generating module 1203 is configured to convert the target clock signal under the effect of the target function, and generate a clock control signal to perform multi-line scanning on the liquid crystal panel.

Optionally, the generating module 1203 is further configured to perform level conversion processing according to the target clock signal in the enabling period to obtain a plurality of clock control signals with a sequence; and shorting the plurality of output ends of the level shifter, so that the plurality of output ends are divided into at least two groups, and each group of output ends outputs the same clock control signal, wherein each group of output ends consists of a preset number of adjacent output ends.

Optionally, the determining module 1202 is further configured to determine an enabling mode of the target function according to a first high level corresponding to a current frame in the frame start signal, a number of continuous first pulses in the enable signal after the first high level, and a number of continuous second pulses, where the second pulses are pulses after the first pulses; and determining the starting time period according to the starting mode.

The foregoing apparatus is used for executing the method provided in the foregoing embodiment, and its implementation principle and technical effects are similar, and are not described herein again.

The above modules may be one or more integrated circuits configured to implement the above methods, for example: one or more application specific integrated circuits (Application Specific Integrated Circuit, abbreviated as ASIC), or one or more microprocessors (digital singnal processor, abbreviated as DSP), or one or more field programmable gate arrays (Field Programmable Gate Array, abbreviated as FPGA), or the like. For another example, when a module above is implemented in the form of a processing element scheduler code, the processing element may be a general-purpose processor, such as a central processing unit (Central Processing Unit, CPU) or other processor that may invoke the program code. For another example, the modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A control method of a liquid crystal panel, which is applied to a controller, wherein a first output end in the controller is connected with an input end of a level shifter, a second output end in the controller is connected with an enabling end of a target function in the level shifter, and an output end of the level shifter is connected with the liquid crystal panel, the method comprising:

2. The method according to claim 1, wherein the determining the activation period of the target function according to the preset vertical synchronization signal and the activation signal of the target function includes:

and determining the starting time period according to the starting mode.

3. The method according to claim 2, wherein determining the enabling mode of the target function according to the first high level corresponding to the current frame in the vertical synchronization signal and the number of consecutive first pulses and the number of consecutive second pulses in the enable signal after the first high level comprises:

4. A method according to claim 3, wherein said determining said activation period according to said activation pattern comprises:

5. The method of claim 1, wherein the predetermined clock signal comprises: a first clock signal and a second clock signal, the start time intervals of the first clock signal and the second clock signal being preset for a number of time periods;

6. A control method of a liquid crystal panel, applied to a level shifter, wherein a first output terminal in a controller is connected to an input terminal in the level shifter, a second output terminal in the controller is connected to an enable terminal of a target function in the level shifter, and an output terminal of the level shifter is connected to the liquid crystal panel, the method comprising:

7. The method of claim 6, wherein said converting the target clock signal under the influence of the target function to generate a clock control signal comprises:

8. The method of claim 7, wherein the start times of the clock control signals output by the adjacent two sets of output terminals are spaced apart by a time period of: and the scanning time of the preset number of lines is continuous in the liquid crystal panel.

9. The method of claim 6, wherein the determining the activation period of the target function based on the enable signal and the start of frame signal comprises:

determining an enabling mode of the target function according to a first high level corresponding to a current frame in the frame start signal, the number of continuous first pulses in the enabling signal after the first high level and the number of continuous second pulses, wherein the second pulses are pulses after the first pulses; and determining the starting time period according to the starting mode.

10. A control system of a liquid crystal panel, comprising: the liquid crystal display device comprises a controller and a level shifter, wherein a first output end in the controller is connected with an input end in the level shifter, a second output end in the controller is connected with an enabling end of a target function in the level shifter, and an output end of the level shifter is connected with a liquid crystal panel;

Wherein the controller is configured to execute the method for controlling the liquid crystal panel according to any one of claims 1 to 5, and the level shifter is configured to execute the method for controlling the liquid crystal panel according to any one of claims 6 to 9.