CN115331607A - Display driving device, display device, and display driving method - Google Patents
Display driving device, display device, and display driving method Download PDFInfo
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Abstract
The application discloses display drive device, display device and display drive method, wherein drive device includes: the display device comprises a time sequence controller and a grid driving circuit, wherein the time sequence controller is configured to control the grid driving circuit to scan pixel unit rows of a display panel in a mode of N periods in one frame of picture period when the picture display state is detected that the refresh rate is smaller than or equal to a preset threshold value, and when the total row number N of the pixel unit rows can be divided by N, the i + (j-1) · N rows of the pixel unit rows are scanned in the i period, i =1,2 and …, N; j =1,2, …, N/N, when the total number N of rows of pixel cell rows cannot be divided by N, the i-th period scans the i + (j-1) · N-th row of pixel cell rows, where i =1,2, …, N; j is 1,2 and …, (N + N-i)/N, and the number of rows obtained after j satisfies the value is less than or equal to N. According to the embodiment of the application, when the refresh rate is less than or equal to the preset threshold value, the pixel unit rows are scanned in a frame of picture period in a time-sharing mode, so that the picture flicker can be avoided when the low refresh rate is displayed.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a display driving apparatus, a display apparatus, and a display driving method.
Background
In recent years, as the requirements of electronic products for power consumption are becoming more and more strict, a method of reducing a refresh rate is mostly adopted to reduce power consumption under a static or low-motion picture in the display product industry. When the refresh rate of the existing display is reduced to 30Hz or lower, human eyes can easily observe flicker in low gray scale, which affects the use of terminal customers. In order to avoid the complaint of the products by the end customers, the brand factory provides a standard for the Flicker under the low refresh rate, namely, the Flicker is measured by adopting optical equipment under a 64-gray scale picture and can not exceed 60db under normal temperature and high temperature. However, it is still difficult to meet the customer requirements by optimizing the material plane (negative liquid crystal, PI) and the pixel design plane.
Disclosure of Invention
In order to solve at least one of the above problems, a first aspect of the present application provides a display driving apparatus comprising: a timing controller and a gate driving circuit, wherein,
a timing controller configured to control the gate driving circuit to scan the pixel unit rows of the display panel in n-time intervals in one frame period when the detected picture display state is that the refresh rate is less than or equal to a preset threshold, wherein,
when the total number of rows N of the pixel unit rows can be divided by N, scanning the i + (j-1) · N rows of the pixel unit rows by i =1,2, …, N for the i-th period; j =1,2, …, N/N,
when the total row number N of the pixel unit rows cannot be divided by N, scanning the i + (j-1) · N rows of the pixel unit rows in the i-th period, wherein i =1,2, …, N; j is 1,2, …, (N + N-i)/N, j is less than or equal to N after meeting the requirement of value taking,
n and N are positive integers greater than or equal to 2.
In some alternative embodiments, when n is 2, the scan signals of the odd-numbered rows corresponding to the pixel unit rows are sequentially output in a first period in one frame of the picture period, and the scan signals of the even-numbered rows corresponding to the pixel units are sequentially output in a second period in one frame of the picture period.
In some alternative embodiments, a first blank period is provided between a first period and a second period in one frame picture period, and a second blank period is provided between adjacent frame picture periods.
In some optional embodiments, further comprising a source driving circuit, the timing controller transmits a data voltage corresponding to an odd-numbered row to the source driving circuit in a first period and transmits a data voltage corresponding to an even-numbered row to the source driving circuit in a second period, corresponding to a manner of scanning in 2 periods in one frame picture period.
In some alternative embodiments, the gate driving circuit comprises a first gate driving circuit comprising a cascaded a shift register cells and a second gate driving circuit comprising a cascaded B shift register cells,
the first gate driving circuit correspondingly outputs the driving control signals of the odd-numbered rows, the second gate driving circuit correspondingly outputs the driving control signals of the even-numbered rows,
wherein A, B is a positive integer of 1 or more.
In some alternative embodiments, each stage of the shift register unit in the gate driving circuit outputs the clock signal connected to the clock signal terminal based on the control of the input signal, wherein,
the clock signal end of the 2a-1 stage shift register unit of the first grid driving circuit is electrically connected to a first clock signal line, and the clock signal end of the 2a stage shift register unit is electrically connected to a second clock signal line;
the clock signal terminal of the 2b-1 stage shift register unit of the second gate driving circuit is electrically connected to the third clock signal line, the clock signal terminal of the 2b stage shift register unit is electrically connected to the fourth clock signal line,
the clock signal of the second clock signal line is delayed by 2H from the clock signal of the first clock signal line, the clock signal of the fourth clock signal line is delayed by 2H from the clock signal of the third clock signal line, where H represents the time required to scan one pixel cell line,
wherein a and b are positive integers of 1 or more.
In some alternative embodiments, in one frame of picture period, the gate driving circuit scans the pixel unit rows of the display panel in a manner of scanning in 3 periods or 5 periods.
In some optional embodiments, the timing controller includes a storage unit, and when the timing controller detects that the image display state is a static image with a refresh rate less than or equal to a preset threshold, the timing controller reads the static image data pre-stored in the storage unit and controls the gate driving circuit to scan the pixel unit rows of the display panel in n time periods.
A second aspect of the present application provides a display device comprising the display driving device described above.
A third aspect of the present application provides a display driving method comprising:
acquiring image data to be displayed;
when detecting a refresh period in which a display state of image data to be displayed is equal to or less than a preset threshold, controlling a gate driving circuit to scan a pixel cell row of a display panel in n periods in a frame period, wherein,
when the total number of rows N of the pixel unit rows can be divided by N, scanning the i + (j-1) · N rows of the pixel unit rows by i =1,2, …, N for the i-th period; j =1,2, …, N/N,
scanning an i + (j-1) · N-th row of the pixel unit row for an i-th period when the total number N of rows of the pixel unit row cannot be divided by N, wherein i =1,2, …, N; j is 1,2, …, (N + N-i)/N, j is equal to or less than N,
n and N are positive integers greater than or equal to 2.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a waveform diagram illustrating a related art display driving scheme;
FIG. 2 is a diagram illustrating a display luminance variation during a related art display driving;
FIG. 3 is a schematic block diagram of a display driving apparatus according to an embodiment of the present application;
FIG. 4 is a waveform diagram illustrating a driving architecture of a display driving apparatus according to an embodiment of the present application;
FIG. 5 is a waveform diagram illustrating another driving scheme of a display driving apparatus according to an embodiment of the present application;
FIG. 6 is a schematic diagram illustrating a display luminance variation of a display driving apparatus according to an embodiment of the present application; and
fig. 7 and 8 are schematic block diagrams of odd and even row driving circuits for gate display driving in a display driving apparatus according to an embodiment of the present application.
The beneficial effect of this application is as follows:
the present application addresses the existing problems at present, formulating a display driving device, a display device, and a display driving method, and scanning pixel unit rows in a frame of a picture period in divided periods when a picture display state is that a refresh rate is less than or equal to a preset threshold, and specifically scanning i + (j-1) · N rows of the pixel unit rows in an i-th period when a total row number N of the pixel unit rows can be divided by N, i =1,2, …, N; j =1,2, …, N/N, when the total number N of rows of pixel cell rows cannot be divided by N, the i-th period scans the i + (j-1) · N-th row of pixel cell rows, where i =1,2, …, N; j is 1,2 and …, (N + N-i)/N, and the number of rows obtained after j meets the value is less than or equal to N, so that the phenomenon that a user watches pictures to flicker can be avoided when the low refresh rate is displayed, the user requirements can be met, the refresh rate can be further reduced, the display effect is improved, and the wide application prospect is achieved.
Detailed Description
In order to more clearly illustrate the present application, the present application is further described below in conjunction with the preferred embodiments and the accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the present application.
It should be noted that the ordinal numbers "first", "second", "third" … …, etc. herein are not intended to limit the order of the respective units, nodes, elements or components, but are merely intended to distinguish the respective units, nodes, elements or components. The terms "comprises," "comprising," or "having," when used in this specification, are intended to be open-ended, i.e., to encompass a element, node, component, or section, but also to encompass other elements, nodes, components, or sections, in addition to or in addition to such elements, nodes, components, or sections.
Referring to fig. 1, a driving waveform diagram of a display panel in the related art when displaying a static picture is shown. When a static picture is displayed, a Self-Refresh function (PSR) may be activated, that is, no image data is input to the signal receiving terminal TCON RX of the timing controller TCON of the display Panel, and the timing controller TCON obtains display data by reading a Self-Refresh picture stored in its internal Buffer (Frame Buffer). Referring to fig. 1, in a frame of picture display period, the timing controller TCON sequentially and continuously outputs display data corresponding to the 1 st to 2400 th rows of the pixel unit row in the display interval Vdisplay of one frame, and correspondingly, in the frame of picture display period, the timing controller TCON also controls the gate driving circuit GOA to sequentially input clock signals corresponding to the 1 st to 2400 th rows of the pixel unit row, so that under the action of the clock signals, the gate driving circuit GOA opens the data input transistors of the 1 st to 2400 th rows of the pixel unit row by row and updates the data of the picture to each pixel by row. Of course, fig. 1 only illustrates the static picture waveform in the self-refresh mode, and the display driving waveform in the non-self-refresh mode at the low refresh rate in the related art is similar to fig. 1, except that the timing controller TCON has or has not input image data in one frame of picture period.
In the above driving manner, the brightness of the related art display panel at a low refresh rate varies as shown in fig. 2. Referring to fig. 2, the timing controller TCON supplies an initial signal to the initial signal terminal STV, which indicates driving of one frame of image display when the initial signal is at a high level. In a frame of picture display period, the trend of pixel brightness is changed in a manner of attenuation and uplift, because odd-numbered lines and even-numbered lines are continuously and sequentially driven in a frame of picture to display, and the change intervals of the brightness of adjacent odd-numbered lines and even-numbered lines along with time are very close, the total brightness amplitude change L1 after the brightness of the odd-numbered lines and the brightness of the even-numbered lines are superposed in the frame of picture display period is large, the brightness is changed violently, and the violent change can enable human eyes to perceive obvious picture flicker along with the reduction of the refresh rate, so that the display effect and the user experience are influenced.
In order to solve at least one of the above problems, an embodiment of the present application provides a display driving apparatus, as shown in fig. 3, including: a timing controller 101 and a gate driving circuit 102, wherein,
a timing controller 101 configured to control the gate driving circuit 102 to scan the pixel cell rows of the display panel in n periods in one frame of a picture period when the picture display state is detected as the refresh rate being equal to or less than a preset threshold, wherein,
when the total row number N of the pixel unit rows can be divided by N, scanning the i + (j-1) · N rows of the pixel unit rows in the i-th period, i =1,2, …, N; j =1,2, …, N/N,
scanning an i + (j-1) · N-th row of the pixel unit row for an i-th period when the total number N of rows of the pixel unit row cannot be divided by N, wherein i =1,2, …, N; j is 1,2, …, (N + N-i)/N, j is equal to or less than N,
n and N are positive integers greater than or equal to 2.
In this embodiment, when the screen display state is that the refresh rate is equal to or less than the preset threshold, scanning the pixel unit row in a frame of the screen cycle in divided periods, and specifically when the total row number N of the pixel unit row can be divided by N, scanning the i + (j-1) · N row of the pixel unit row in the i-th period, i =1,2, …, N; j =1,2, …, N/N, when the total number N of rows of pixel cell rows cannot be divided by N, the i-th period scans the i + (j-1) · N-th row of pixel cell rows, where i =1,2, …, N; j is 1,2 and …, (N + N-i)/N, and the number of rows obtained after j meets the value is less than or equal to N, so that the phenomenon that a user watches pictures to flicker can be avoided when the low refresh rate is displayed, the user requirements can be met, the refresh rate can be further reduced, the display effect is improved, and the wide application prospect is achieved.
The structure and function of the display driving device of the embodiment of the present application are described in detail below by a specific example.
Referring to fig. 3, the display driving apparatus includes a Timing Controller (TCON) 101 and a gate driving circuit 102. The timing controller 101 comprises a signal receiving terminal TCON RX and a gate driving control terminal STV, wherein the signal receiving terminal TCON RX is used for receiving picture data from a display card, and the picture data comprises data voltage for driving a data input transistor of each pixel unit pixel circuit and a driving timing sequence corresponding to the driving gate driving circuit; the gate driving control terminal STV is used to transmit an initial signal STV for controlling the gate driving circuit 102 to output a gate driving signal (i.e., a scan signal) to the gate driving circuit 102. In addition, as shown in fig. 3, the display driving apparatus further includes a Source driving circuit (Source IC) 103, and the timing controller 101 further includes a signal output terminal TCON TX for outputting a data voltage to the Source driving circuit 103, so that the Source driving circuit 103 receives the data voltage and outputs a corresponding data voltage to the Source of the data input transistor in the pixel circuit of each pixel of the display panel.
In particular, in the embodiment of the present application, the timing controller 101 is configured to, upon detecting that the screen display state is a refresh rate equal to or less than a preset threshold, scan the rows of pixel cells of the display panel in a manner of controlling the gate drive circuit for n periods in one frame of the screen period, wherein,
scanning an i + (j-1) · N-th row of the pixel unit row for an i =1,2, …, N, when a total number N of rows of the pixel unit row is divisible by N; j =1,2, …, N/N,
scanning an i + (j-1) · N row of the pixel unit row for an i-th period when a total number N of rows of the pixel unit row cannot be divided by N, wherein i =1,2, …, N; j is 1,2, …, (N + N-i)/N, j is equal to or less than N,
n and N are positive integers greater than or equal to 2.
In the embodiment of the present application, the preset threshold may be a frequency value of 60Hz, 30Hz or less, and the specific frequency value may be determined according to the specific function of the display panel, and is not limited herein.
Continuing to refer to fig. 3 and 4, in this example, n is taken as 2 for a specific explanation.
When N is 2, when the total number of rows N of the pixel unit rows can be divided by 2, that is, when the total number of rows N of the pixel unit rows is an even number, i =1,2, …, N, j =1,2, …, N/2; when the total number N of rows of pixel element rows cannot be divided by 2 in whole, that is, when the total number N of rows of pixel element rows is an odd number, i =1,2, …, N, j =1,2, …, (N + 1)/2,n, N is a positive integer of 2 or more.
Specifically, when n is 2, the scan signals of the odd-numbered rows corresponding to the pixel unit rows are sequentially output in a first period in one frame of the picture period, and the scan signals of the even-numbered rows corresponding to the pixel units are sequentially output in a second period in one frame of the picture period.
For convenience of description, it is assumed that N is an even number in this example, for example, 2400 is used for illustration, and the refresh rate is 30Hz in this example. Of course, those skilled in the art should understand that the above specific values are not intended to limit the present application, and the refresh rate and the total number of rows of pixel units may be specifically set in practical applications.
Referring to fig. 3 and 4, in one frame of picture period, the signal receiving terminal RX of the timing controller 101 receives all picture data corresponding to the pixel unit rows 1 to 2400, and in this application, since the data voltages of the odd and even rows are output sequentially, in order to ensure that the data voltage of the even row can be read correctly, all row data voltages should be received in the first period Vdisplay 1. That is, differently from the scheme of driving the pixel cells of the odd and even rows continuously in one frame of the picture period, the blank period Vblank after the signal receiving terminal RX receives the picture data is larger to ensure that the picture data written by the timing controller 101 is correct, and a specific range is described below.
With continued reference to fig. 3 and 4, under the control of the gate driving control terminal STV of the timing controller 101, the gate driving circuit 102 controls the output terminals Out1, out3, … and OutN-1 of the odd-numbered row of the gate driving circuit 102 to output the scanning signals of the odd-numbered row to drive the data input transistors of the odd-numbered row of the pixel cells to be turned on by controlling the clock signal terminals CK1, CK3, … and CK2399 of the odd-numbered row of the gate driving circuit to output the clock signals in sequence at the first period Vdisplay1, so that the data voltages which are already input to the sources of the data input transistors by the odd-numbered row output terminals ata1, vdata3, … and Vdata 99 of the source driving circuit 103 can be written into the pixel circuits; in the second period Vdisplay2, the output terminals Out2, out4, … and OutN of the gate driving circuit 102 corresponding to the even-numbered row of pixel cells output the scanning signals of the even-numbered row by controlling the clock signal terminals CK2, CK4, … and CK2400 of the even-numbered row gate driving circuit to sequentially output the clock signals so as to drive the data input transistors of the even-numbered row of pixel cells to be turned on, thereby enabling the data voltages which have been input to the sources of the data input transistors by the even-numbered row output terminals Vdata2, vdata4, … and Vdata2400 of the source driving circuit 103 to be written into the pixel circuits.
Particularly, in the embodiment of the present application, the timing controller 101 does not sequentially output the data voltages Vdata1, vdata2, vdata3, …, vdataN-1, and VdataN corresponding to all the rows of one frame of the picture at one time through the timing controller TCON, but sequentially outputs the data voltages corresponding to the odd-numbered rows and the even-numbered rows respectively in two times. That is, in the embodiment of the present application, although the picture data of each row is received at a time, the signal output terminal TCON TX of the timing controller 101 is set to read the data voltages corresponding to the odd-numbered rows, respectively, so that the data voltages are written to the odd-numbered and even-numbered rows of the pixel unit rows at intervals in one frame picture period.
Specifically, referring to fig. 4, the timing controller 101 transmits a data voltage corresponding to odd-numbered rows to the source driving circuit 103 for a first period Vdisplay1, and transmits a data voltage corresponding to even-numbered rows to the source driving circuit 103 for a second period Vdisplay 2.
In addition, as shown in fig. 4, a first blank period Vblank1 is provided between the first period Vdisplay1 and the second period Vdisplay2 in one frame picture period, and a second blank period Vblank2 is provided between adjacent frame picture periods. It will be understood by those skilled in the art that one frame picture period is composed of a first period Vdisplay1, a first blank period Vblank1, a second period Vdisplay2, and a second blank period Vblank2. By setting the first blank period Vblank1, it can be ensured that the gate driving circuit 102 is correctly controlled to output the scanning signal corresponding to the odd-numbered row and the scanning signal corresponding to the even-numbered row, respectively.
Further, correspondingly to this, for the signal output terminal TCON TX of the timing controller 101, the first blank period Vblank1 is also spaced between the output of the data voltage corresponding to the odd-numbered line and the data voltage corresponding to the even-numbered line to ensure that it can correspond to the writing time of the scan signal of the odd-numbered line and the scan signal of the even-numbered line.
In some alternative embodiments, in order to reduce power consumption, a self-refresh function is employed when the display panel displays a static picture.
Specifically, the timing controller 101 further includes a storage unit (not shown), which may be a Buffer memory (Frame Buffer) in which still picture data to be displayed is stored in advance. Referring to fig. 5, when the timing controller 101 detects that the image display state is a static image with a refresh rate less than or equal to a predetermined threshold, the timing controller 101 reads the static image data pre-stored in the storage unit and controls the gate driving circuit to scan the pixel unit rows of the display panel in 2 time periods.
It should be noted that the above manner of dividing into 2 periods is only exemplary, and the present application does not limit the number of periods, that is, similar to the above embodiment, the pixel unit rows of the display panel may be scanned in the manner of dividing into n periods, and the scanning manner is consistent with the setting of the above embodiment.
In particular, referring to fig. 5, when it is detected that the picture display state is a static picture with a refresh rate equal to or less than a preset threshold, the signal input terminal TCON RX of the timing controller 101 is not inputted with picture data, the signal output terminal TCON TX reads pre-stored still picture data from the storage unit, transmits a data voltage corresponding to an odd-numbered row to the source driving circuit 103 during a first period Vdisplay1, and transmits a data voltage corresponding to an even-numbered row to the source driving circuit 103 during a second period Vdisplay2, as shown in fig. 5.
In addition, as shown in fig. 3 and 5, the signal output terminal TCON TX reads pre-stored still picture data from the storage unit, and the gate driving circuit 102 controls the clock signal terminals CK1, CK3, …, and CK2399 of the odd-numbered row gate driving circuit to sequentially output clock signals at the first period Vdisplay1 under the control of the gate driving control terminal STV of the timing controller 101, so as to control the output terminals Out1, out3, …, and OutN-1 of the gate driving circuit 102 and the odd-numbered row pixel cell row to output scanning signals of the odd-numbered row to drive the data input transistor of the odd-numbered row pixel cell to be turned on, thereby writing data voltages, which have been input from the odd-numbered row output terminals Vdata1, vdata3, …, and Vdata2399 of the source driving circuit 103 to the source of the data input transistor; in the second period Vdisplay2, the clock signal terminals CK2, CK4, … and CK2400 of the even-numbered row gate drive circuit are controlled to sequentially output the clock signals, so that the output terminals Out2, out4, … and OutN of the gate drive circuit 102 corresponding to the even-numbered row of pixel units output the scanning signals of the even-numbered row to drive the data input transistors of the even-numbered row of pixel units to be turned on, and thus the data voltage which is input to the sources of the data input transistors from the even-numbered row output terminals Vdata2, vdata4, … and Vdata2400 of the source drive circuit 103 can be written into the pixel circuits.
Through the arrangement of the embodiment of the application, according to the waveform diagram of fig. 6, the gate driving control terminal STV outputs the initial signal STV twice in one frame of the picture period, wherein the black high-level signal is the initial signal of the even-numbered line, and the gray high-level signal is the initial signal of the odd-numbered line, because the gate driving circuit is controlled to output the scanning signal of the even-numbered line and the scanning signal of the odd-numbered line in the first time period and the second time period in one frame of the picture period, so that the scanning signal of the even-numbered line and the scanning signal of the odd-numbered line are staggered by 90 degrees in phase, the peak of the brightness change of the odd-numbered line and the peak of the brightness change of the even-numbered line in one frame of the picture display period correspond to a trough, the total brightness amplitude variation L2 after superposition is reduced, the brightness change is reduced, thereby the obvious flicker of the picture can not be perceived by human eyes in the display state with a low refresh rate, and the display effect and the user experience are improved. In addition, through the arrangement, the brightness variation of the display panel during displaying the image can be reduced, and compared with the display effect of the related art, the refresh rate of the display panel can be further reduced, so that the lower limit of the existing refresh rate can be further reduced, and the power consumption of the product can be further reduced.
It should be noted that, although the driving control process at the time of low refresh rate is described above by taking 2 time periods as an example, the application is not limited to this, and optionally, when it is detected that the image display state is that the refresh rate is less than or equal to the preset threshold, in one frame of image period, the gate driving circuit scans the pixel unit rows of the display panel in a manner of scanning in 3 time periods or 5 time periods, and specific processes and principles are not repeated.
It should be further specifically noted that the gate driving circuit is a circuit formed by cascaded shift register units, and therefore, in order to match the time-division scanning method of the gate driving circuit 102 in the present application and ensure that the scanning signals of each row can be output according to the time-division scanning method, in the embodiment of the present application, the gate driving circuit 102 is divided into independent units and is controlled separately.
The gate drive circuit comprises a first gate drive circuit and a second gate drive circuit, the first gate drive circuit comprises a cascaded A shift register units, the second gate drive circuit comprises a cascaded B shift register units,
the first gate driving circuit correspondingly outputs the driving control signals of the odd-numbered rows, the second gate driving circuit correspondingly outputs the driving control signals of the even-numbered rows,
wherein A, B is a positive integer of 1 or more.
Specifically, a specific circuit description is still given below by taking a manner of scanning at 2 periods as an example, in which an example of driving 8 pixel unit rows is schematically shown. Referring to fig. 7 and 8, the gate driving circuit 102 includes a first gate driving circuit 102-1 and a second gate driving circuit 102-2, the first gate driving circuit 102-1 includes 4 cascaded shift register units GOA-1, GOA-3, GOA-5, and GOA-7, and the second gate driving circuit includes 4 cascaded shift register units GOA-2, GOA-4, GOA-6, and GOA-8; the first gate driving circuit 102-1 outputs driving control signals (i.e., scan signals) out1, out3, out5, and out7 for odd-numbered rows, and the second gate driving circuit 102-2 outputs driving control signals (i.e., scan signals) out2, out4, out6, and out8 for even-numbered rows.
As can be seen, the first gate driving circuit 102-1 outputting the scanning signals to the odd-numbered row of pixel unit rows and the second gate driving circuit 102-2 outputting the scanning signals to the even-numbered row of pixel unit rows are respectively and independently cascaded.
In addition, the first gate driving circuit 102-1 outputting the scanning signals to the odd-numbered pixel unit rows and the second gate driving circuit 102-2 outputting the scanning signals to the even-numbered pixel unit rows are independently controlled, that is, initial signals of different timings are respectively supplied, and correspond to the output clock signals.
Each stage of shift register unit in the gate driving circuit outputs a clock signal accessed by a clock signal terminal based on the control of the input signal of the shift register unit, wherein,
the clock signal end of the 2a-1 stage shift register unit of the first grid driving circuit is electrically connected to a first clock signal line, and the clock signal end of the 2a stage shift register unit is electrically connected to a second clock signal line; the clock signal terminal of the 2b-1 stage shift register unit of the second gate driving circuit is electrically connected to a third clock signal line, the clock signal terminal of the 2b stage shift register unit is electrically connected to a fourth clock signal line, the clock signal of the third clock signal line is delayed by 2H from the clock signal of the first clock signal line, the clock signal of the fourth clock signal line is delayed by 2H from the clock signal of the second clock signal line, where H represents a time required to scan one pixel cell line,
wherein a and b are positive integers of 1 or more.
Specifically, referring to fig. 7 and 8, the clock signal terminal of the 1 st stage shift register unit (i.e., GOA-1) of the first gate driving circuit 102-1 is electrically connected to the first clock signal line CLK _1, the clock signal terminal of the 2 nd stage shift register unit (i.e., GOA-3) is electrically connected to the second clock signal line CLK-2, the clock signal terminal of the 3 rd stage shift register unit (i.e., GOA-5) is electrically connected to the first clock signal line CLK _1, and the clock signal terminal of the 4 th stage shift register unit (i.e., GOA-7) is electrically connected to the second clock signal line CLK-2;
the clock signal terminal of the 1 st stage shift register unit (i.e., GOA-2) of the second gate driving circuit 102-2 is electrically connected to the third clock signal line CLK _3, the clock signal terminal of the 2 nd stage shift register unit (i.e., GOA-4) is electrically connected to the fourth clock signal line CLK _4, the clock signal terminal of the 3 rd stage shift register unit (i.e., GOA-6) is electrically connected to the third clock signal line CLK _3, and the clock signal terminal of the 4 th stage shift register unit (i.e., GOA-8) is electrically connected to the fourth clock signal line CLK _4.
The first clock signal line CLK _1, the second clock signal line CLK _2, the third clock signal line CLK _3, and the fourth clock signal line CLK _4 are independently controllable signal lines that are respectively connected to different clock signals. In addition, compared with the case where the timing controller sequentially transmits the frame data of each line in one frame period, in the embodiment of the present invention, the output interval of the scan signal of the odd-numbered lines and the scan signal of the even-numbered lines is larger, so that the clock signal of the third clock signal line CLK _2 is delayed by 2H from the clock signal of the first clock signal line CLK _1, and the clock signal of the fourth clock signal line CLK _4 is delayed by 2H from the clock signal of the second clock signal line CLK _3, where H represents the time required for scanning one pixel unit line.
Based on the same inventive concept, an embodiment of the present application further provides a display driving method, which can be applied to the display driving apparatus described in the above embodiments, including:
acquiring image data to be displayed;
when detecting that the display state of the image data to be displayed is a refresh stage which is less than or equal to a preset threshold value, in a frame of picture period, controlling the grid drive circuit to scan the pixel unit row of the display panel in n periods, wherein,
when the total number of rows N of the pixel unit rows can be divided by N, scanning the i + (j-1) · N rows of the pixel unit rows by i =1,2, …, N for the i-th period; j =1,2, …, N/N,
scanning an i + (j-1) · N-th row of the pixel unit row for an i-th period when the total number N of rows of the pixel unit row cannot be divided by N, wherein i =1,2, …, N; j is 1,2, …, (N + N-i)/N, j is equal to or less than N,
n and N are positive integers greater than or equal to 2.
With the above arrangement, when the screen display state is that the refresh rate is less than or equal to the preset threshold, scanning the pixel unit rows in a frame of the screen cycle in divided periods, and specifically, when the total number N of rows of the pixel unit rows can be divided by N, scanning the i + (j-1) · N rows of the pixel unit rows in the i-th period, i =1,2, …, N; j =1,2, …, N/N, when the total number N of rows of pixel cell rows cannot be divided by N, the i-th period scans the i + (j-1) · N-th row of pixel cell rows, where i =1,2, …, N; j is 1,2 and …, (N + N-i)/N, and the number of rows obtained after j meets the value is less than or equal to N, so that the phenomenon that a user watches pictures to flicker can be avoided when the low refresh rate is displayed, the user requirements can be met, the refresh rate can be further reduced, the display effect is improved, and the wide application prospect is achieved.
Based on the same inventive concept, embodiments of the present application also provide a display device including the display driving device described in the above embodiments.
In this embodiment, the display device may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, an on-board display, a digital photo frame, or a navigator, and by using the display device having the above display driving device, an image flicker phenomenon recognizable by a user can be avoided in a low refresh display state during a display process, so that a display effect and user experience are improved, and the display device has a wide application prospect.
The present application addresses the existing problems at present, formulating a display driving device, a display device, and a display driving method, and scanning pixel unit rows in a frame of a picture period in divided periods when a picture display state is that a refresh rate is less than or equal to a preset threshold, and specifically scanning i + (j-1) · N rows of the pixel unit rows in an i-th period when a total row number N of the pixel unit rows can be divided by N, i =1,2, …, N; j =1,2, …, N/N, when the total number N of rows of pixel cell rows cannot be divided by N, the i-th period scans the i + (j-1) · N-th row of pixel cell rows, where i =1,2, …, N; j is 1,2 and …, (N + N-i)/N, and the number of rows obtained after j meets the value is less than or equal to N, so that the phenomenon that a user watches pictures to flicker can be avoided when the low refresh rate is displayed, the user requirements can be met, the refresh rate can be further reduced, the display effect is improved, and the wide application prospect is achieved.
It should be understood that the above-mentioned examples are given for the purpose of illustrating the present application clearly and not for the purpose of limiting the same, and that various other modifications and variations of the present invention may be made by those skilled in the art in light of the above teachings, and it is not intended to be exhaustive or to limit the invention to the precise form disclosed.
Claims (10)
1. A display driving apparatus, comprising: a timing controller and a gate driving circuit, wherein,
the time sequence controller is configured to control the grid drive circuit to scan the pixel unit rows of the display panel in a mode of dividing into n periods in one frame of picture period when the picture display state is detected that the refresh rate is less than or equal to a preset threshold value,
scanning an i + (j-1) · N-th row of the pixel unit row for an i =1,2, …, N, when a total number N of rows of the pixel unit row is divisible by N; j =1,2, …, N/N,
scanning an i + (j-1) · N row of the pixel unit row for an i-th period when a total number N of rows of the pixel unit row cannot be divided by N, wherein i =1,2, …, N; j is 1,2, …, (N + N-i)/N, j is equal to or less than N,
n and N are positive integers greater than or equal to 2.
2. The drive control device according to claim 1, wherein when n is 2, the scan signals corresponding to odd-numbered lines of the pixel unit rows are sequentially output in a first period in one frame period, and the scan signals corresponding to even-numbered lines of the pixel unit rows are sequentially output in a second period in one frame period.
3. The drive control device according to claim 2, wherein a first blanking period is provided between a first period and a second period in one frame picture period, and a second blanking period is provided between adjacent frame picture periods.
4. The display driving device according to claim 2, further comprising a source driving circuit, wherein the timing controller transmits a data voltage corresponding to the odd-numbered row to the source driving circuit in the first period and transmits a data voltage corresponding to the even-numbered row to the source driving circuit in the second period, corresponding to a manner of scanning in 2 periods in one frame period.
5. The display driving device according to claim 2, wherein the gate driving circuit comprises a first gate driving circuit and a second gate driving circuit, the first gate driving circuit comprises a cascaded number A of shift register cells, the second gate driving circuit comprises a cascaded number B of shift register cells,
the first gate driving circuit correspondingly outputs the driving control signals of the odd-numbered rows, the second gate driving circuit correspondingly outputs the driving control signals of the even-numbered rows,
wherein A, B is a positive integer of 1 or more.
6. The display driving device according to claim 5, wherein each stage of the shift register unit in the gate driving circuit outputs a clock signal connected to a clock signal terminal based on the control of its input signal, wherein,
the clock signal end of the 2a-1 stage shift register unit of the first gate driving circuit is electrically connected to a first clock signal line, and the clock signal end of the 2a stage shift register unit is electrically connected to a second clock signal line;
the clock signal terminal of the 2b-1 stage shift register unit of the second gate driving circuit is electrically connected to a third clock signal line, the clock signal terminal of the 2b stage shift register unit is electrically connected to a fourth clock signal line,
the clock signal of the second clock signal line is delayed by 2H from the clock signal of the first clock signal line, the clock signal of the fourth clock signal line is delayed by 2H from the clock signal of the third clock signal line, where H represents a time required to scan one pixel cell line,
wherein a and b are positive integers of 1 or more.
7. The display driving device according to claim 1, wherein the gate driving circuit scans the pixel unit rows of the display panel in a manner of scanning in 3 periods or 5 periods in one frame period.
8. The display driving device according to claim 1, wherein the timing controller comprises a storage unit, and when the timing controller detects that the image display state is a static image with a refresh rate less than or equal to the preset threshold, the timing controller reads the static image data pre-stored in the storage unit and controls the gate driving circuit to scan the pixel unit rows of the display panel in the n-period manner.
9. A display device characterized by comprising the display drive device according to any one of claims 1 to 8.
10. A display driving method, comprising:
acquiring image data to be displayed;
when detecting that the display state of the image data to be displayed is a refresh stage which is less than or equal to a preset threshold value, in one frame of picture period, controlling the grid drive circuit to scan the pixel unit rows of the display panel by n periods, wherein,
when the total number of rows N of the pixel unit rows can be divided by N, scanning the i + (j-1) · N rows of the pixel unit rows by i =1,2, …, N for the i-th period; j =1,2, …, N/N,
scanning an i + (j-1) · N-th row of the pixel unit row for an i-th period when the total number N of rows of the pixel unit row cannot be divided by N, wherein i =1,2, …, N; j is 1,2, …, (N + N-i)/N, j is equal to or less than N,
n and N are positive integers greater than or equal to 2.
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| CN114863871A (en) * | 2022-05-17 | 2022-08-05 | 昆山国显光电有限公司 | Display panel, driving method thereof and display device |
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| CN114863871A (en) * | 2022-05-17 | 2022-08-05 | 昆山国显光电有限公司 | Display panel, driving method thereof and display device |
| CN114863871B (en) * | 2022-05-17 | 2024-02-27 | 昆山国显光电有限公司 | Display panel, driving method thereof and display device |
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