CN113643645A - Display panel, display panel driving method and display - Google Patents
Display panel, display panel driving method and display Download PDFInfo
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- CN113643645A CN113643645A CN202111207436.4A CN202111207436A CN113643645A CN 113643645 A CN113643645 A CN 113643645A CN 202111207436 A CN202111207436 A CN 202111207436A CN 113643645 A CN113643645 A CN 113643645A
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The invention discloses a display panel, a display panel driving method and a display, and relates to the technical field of display. The display panel comprises a data driving circuit, a time sequence control circuit, an array substrate and a plurality of scanning driving circuits. And the time sequence control circuit is used for generating a plurality of groups of clock signals and transmitting the groups of clock signals to the scanning driving circuits in a one-to-one correspondence manner, wherein the starting time corresponding to each group of clock signals is different. And the scanning driving circuit is used for driving the pixels of the corresponding row in the array substrate according to the corresponding clock signal. The invention can configure the starting time of the corresponding scanning drive circuit according to the charging time required by the pixel; configuring a shorter opening time for the pixels close to the driving side with shorter charging time; for the pixels which are far away from the driving side and have longer charging time, the longer opening time is configured, so that all pixels in the array substrate are sufficiently charged, and the phenomenon that part of pixels are insufficiently charged to cause darker display is avoided.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel, a display panel driving method and a display.
Background
For a high refresh rate/high resolution display screen, the turn-on time corresponding to each row of scanning lines is often short. When the data line is charging each pixel, because the pixel voltage who keeps away from the data line drive end climbs slowly, when the opening time of scanning line was short, leaded to the pixel to charge inadequately easily, and display brightness is darker relatively, influences user experience.
Disclosure of Invention
The invention mainly aims to provide a display panel, a display panel driving method and a display, and aims to solve the technical problem that pixels far away from a data line driving end are easy to be insufficiently charged in the prior art.
In order to achieve the above object, the present invention provides a display panel, which includes a data driving circuit, a timing control circuit, and an array substrate, wherein the data driving circuit is disposed at a driving side of the array substrate, the display panel further includes a plurality of scan driving circuits, and each scan driving circuit is connected to the timing control circuit;
the time sequence control circuit is used for generating a plurality of groups of clock signals and transmitting the groups of clock signals to the scanning driving circuits in a one-to-one correspondence manner, wherein the starting time of each group of clock signals is different;
and the scanning driving circuit is used for driving the pixels of the corresponding row in the array substrate according to the corresponding clock signal, wherein the starting time corresponding to the clock signal received by the scanning driving circuit far away from the driving side is longer than the starting time corresponding to the clock signal received by the scanning driving circuit close to the driving side.
Optionally, the timing control circuit is further configured to generate a plurality of frame start signals, and transmit each frame start signal to each scan driving circuit in a one-to-one correspondence manner;
and the scanning driving circuit is also used for driving the pixels of the corresponding row in the array substrate according to the corresponding clock signal when receiving the corresponding frame starting signal.
Optionally, the start trigger time corresponding to the clock signal far away from the driving side precedes the start trigger time corresponding to the clock signal close to the driving side.
In addition, in order to achieve the above object, the present invention further provides a display panel driving method, where the display panel includes a data driving circuit and an array substrate, the data driving circuit is disposed on a driving side of the array substrate, the display panel is further provided with a plurality of scan driving circuits, the display panel driving method is applied to the display panel, and the display panel driving method includes the following steps:
generating a plurality of groups of clock signals according to preset time parameters, and transmitting the groups of clock signals to each scanning driving circuit in a one-to-one correspondence manner, wherein the starting time corresponding to each group of clock signals is different;
and driving the pixels of the corresponding row in the array substrate according to the clock signals corresponding to the scanning driving circuits, wherein the starting time corresponding to each group of clock signals is different, and the starting time corresponding to the clock signal received by the scanning driving circuit far away from the driving side is longer than the starting time corresponding to the clock signal received by the scanning driving circuit close to the driving side.
Optionally, generating a plurality of groups of clock signals according to the preset time parameter, and transmitting each group of clock signals to each scan driving circuit in a one-to-one correspondence manner, includes:
generating a plurality of groups of clock signals according to preset time parameters;
generating corresponding frame start signals according to the driving sequence of each scanning driving circuit;
and transmitting each group of clock signals and the corresponding frame start signals to each scanning driving circuit in a one-to-one correspondence manner.
Optionally, the preset time parameter includes a plurality of opening times;
generating a plurality of groups of clock signals according to preset time parameters, comprising:
determining the number of clock signals required by each scanning driving circuit and the corresponding starting time of each scanning driving circuit;
and generating a clock signal group corresponding to each scanning driving circuit according to the starting time and the number of the clock signals corresponding to each scanning driving circuit to obtain a plurality of groups of clock signals.
Optionally, the preset time parameter includes a first opening time and a second opening time;
generating a plurality of groups of clock signals according to the preset time parameters, and transmitting the groups of clock signals to each scanning driving circuit in a one-to-one correspondence manner, wherein the method comprises the following steps:
generating a first clock signal according to the first starting time, and transmitting the first clock signal to a first scanning driving circuit far away from a driving side;
and generating a second clock signal according to a second starting time, and transmitting the second clock signal to a second scanning driving circuit close to the driving side, wherein the first starting time is longer than the second starting time.
Optionally, before generating the first clock signal according to the first turn-on time, the method further includes:
acquiring a first clock correction value;
and adding the preset opening time and the first clock correction value to obtain the first opening time.
Optionally, before generating the second clock signal according to the second turn-on time, the method further includes:
acquiring a second clock correction value;
and subtracting the second clock correction value from the preset opening time to obtain a second opening time.
In addition, in order to achieve the above object, the present invention further provides a display, which includes the display panel as described above.
In the invention, the display panel comprises a data driving circuit, a time sequence control circuit, an array substrate and a plurality of scanning driving circuits, wherein each scanning driving circuit is respectively connected with the time sequence control circuit. And the time sequence control circuit is used for generating a plurality of groups of clock signals and transmitting the groups of clock signals to the scanning driving circuits in a one-to-one correspondence manner, wherein the starting time corresponding to each group of clock signals is different. And the scanning driving circuit is used for driving the pixels of the corresponding row in the array substrate according to the corresponding clock signal, wherein the starting time corresponding to the clock signal received by the scanning driving circuit far away from the driving side is longer than the starting time corresponding to the clock signal received by the scanning driving circuit close to the driving side. The embodiment can configure the starting time of the corresponding scanning drive circuit according to the charging time required by the pixel; for the pixels close to the driving side with shorter charging time, shorter turn-on time can be configured for the corresponding scanning driving circuit; for the pixels far away from the driving side with longer charging time, longer opening time can be configured for the corresponding scanning driving circuit, so that all pixels in the array substrate are sufficiently charged, and the phenomenon that part of pixels are insufficiently charged to cause darker display is avoided.
Drawings
FIG. 1 is a schematic block diagram of a display panel according to a first embodiment of the present invention;
FIG. 2 is a diagram illustrating clock signals according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating a display panel driving method according to a second embodiment of the present invention;
FIG. 4 is a flowchart illustrating a display panel driving method according to a third embodiment of the present invention;
FIG. 5 is a first schematic diagram illustrating charging of a pixel near the driving side according to a third embodiment of the present invention;
FIG. 6 is a first schematic diagram illustrating charging of a pixel away from the driving side according to a third embodiment of the present invention;
FIG. 7 is a second schematic diagram illustrating charging of a pixel near the driving side according to a third embodiment of the present invention;
FIG. 8 is a second schematic diagram illustrating charging of a pixel away from the driving side according to a third embodiment of the present invention;
fig. 9 is a schematic structural diagram of a display according to a fourth embodiment of the present invention.
The reference numbers illustrate:
| reference numerals | Name (R) | Reference numerals | Name (R) |
| 100 | |
400 | |
| 200 | |
500 | |
| 300 | |
600 | Backlight module |
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that all the directional indicators (such as up, down, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.
In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should be considered to be absent and not within the protection scope of the present invention.
Example one
Referring to fig. 1, fig. 1 is a schematic block diagram of a display panel according to an embodiment of the invention. The invention provides an embodiment of a display panel.
In this embodiment, the display panel includes a data driving circuit 100, a timing control circuit 200, and an array substrate 300, the data driving circuit 100 is disposed on a driving side of the array substrate 300, and the display panel further includes a plurality of scan driving circuits 400, and each scan driving circuit 400 is connected to the timing control circuit 200.
The timing control circuit 200 is configured to generate a plurality of groups of clock signals, and transmit the groups of clock signals to the scan driving circuits 400 in a one-to-one correspondence manner, where the start times of the groups of clock signals are different;
the scan driving circuit 400 is configured to drive the pixels in the corresponding row of the array substrate 300 according to a corresponding clock signal, wherein an on time corresponding to the clock signal received by the scan driving circuit 400 far from the driving side is longer than an on time corresponding to the clock signal received by the scan driving circuit 400 near the driving side.
It is understood that the data driving circuit 100 is used to convert video signals into data voltages and apply the data voltages to the pixels through the data lines of the columns, so that the pixels perform display. The data driving circuit 100 is usually disposed at one end of a data line in the array substrate 300; for example, the data driving circuit 100 may be disposed above or below the data lines disposed in the column direction. If the data driving circuit 100 is disposed below the array substrate 300, the data voltage is transmitted from below to above as a driving side. At this time, if the size of the array substrate 300 is large, the voltage of each row of pixels located above the array substrate 300 tends to rise slowly.
In the present embodiment, in order to avoid insufficient charging of pixels in each row away from the driving side of the array substrate 300, the scan lines in the array substrate 300 are driven in groups. For example, if the data of the scanning lines is 1080 lines, two sets of scanning driving circuits 400 may be provided, and each scanning driving circuit 400 drives 540 lines. The scan driving circuit 400 far from the driving side is the scan driving circuit 400 driving the scan lines above the array substrate 300; the scan driving circuit 400 near the driving side refers to the scan driving circuit 400 that drives the scan lines located under the array substrate 300. Of course, if the data of the scanning lines is 1080 lines, three, four, etc. groups of scanning driving circuits 400 may be provided to drive the scanning lines in groups.
It is understood that since each scan driving circuit 400 can be independently configured, the corresponding turn-on time can be configured according to a desired charging time. For pixels near the driving side with shorter charging time, a shorter turn-on time may be configured for the corresponding scan driving circuit 400; for the pixels far from the driving side with longer charging time, the corresponding scan driving circuit 400 may be configured with longer turn-on time, so that all the pixels in the array substrate 300 are charged sufficiently, and the power consumption of the display panel is not increased.
It should be noted that each scan driving circuit 400 may include a plurality of Gate drive on Array (GOA) circuits, and the scan driving circuit 400 receives the clock signal sent by the timing control circuit and drives the scan lines to be turned on according to the clock signal. In a specific implementation, the array substrate 300 may adopt a single-sided GOA driving or a double-sided GOA driving.
It will be appreciated that the clock signal is used to drive the output voltage waveform of each GOA circuit. In specific implementation, the clock signal may be a pulse signal, the GOA circuit may output a scan signal when the clock signal is at a high potential, and the GOA circuit does not output the scan signal when the clock signal is at a low potential; wherein, the duration of the high potential in one period is the turn-on time corresponding to the clock signal.
Referring to fig. 2, fig. 2 is a schematic diagram of clock signals according to a first embodiment of the invention. As shown in fig. 2, from top to bottom, the first row signal and the sixth row signal are frame start signals; the second to fifth row signals are a first group of clock signals for driving the scan driving circuit 400 away from the driving side; the seventh to tenth row signals are a second group of clock signals for driving the scan driving circuit 400 near the driving side; and the starting time corresponding to the first group of clock signals is longer than the starting time corresponding to the second group of clock signals. Of course, the number of clock signals corresponding to a group of clock signals may be different according to the specific structure of the GOA circuit.
In addition, in order to facilitate driving of each group of scan driving circuits 400, in the present embodiment, the timing control circuit 200 is further configured to generate a plurality of frame start signals and transmit the frame start signals to each scan driving circuit 400 in a one-to-one correspondence. The scan driving circuit 400 is further configured to drive the pixels in the corresponding row of the array substrate 300 according to the corresponding clock signal when receiving the corresponding frame start signal.
It is understood that the frame start signal is used to drive the scan driving circuit 400 to turn on. The first-stage GOA circuit in each scanning driving circuit 400 outputs a scanning signal when receiving a frame start signal; and simultaneously driving the next-stage GOA circuit to be started. After all the GOA circuits in one group of scan driving circuits 400 are turned on, the first-stage GOA circuits in the next group of scan driving circuits 400 are driven to be turned on by a frame start signal. With continued reference to fig. 2, the frame start signal of the first row is used to drive the scan driving circuit 400 away from the driving side, and the frame start signal of the sixth row is used to drive the scan driving circuit 400 close to the driving side.
In this embodiment, in order to facilitate the arrangement of the clock signals of each group, the start trigger time corresponding to the clock signal far from the driving side precedes the start trigger time corresponding to the clock signal near the driving side. The starting triggering moment refers to the starting moment of the corresponding TFT device. Generally, each scanning line in the array substrate is driven in a one-by-one scanning mode, that is, the TFT device corresponding to one row of scanning line is turned on each time, and after the turn-on time reaches a preset time, the TFT device corresponding to the row of scanning line is turned off, and the TFT device corresponding to the next row of scanning line is turned on. In this embodiment, the driving order of the pixels in each row is from a row requiring longer charging to a row requiring shorter charging, that is, from the top to the bottom of the array substrate. The pixels which are charged longer are preferentially driven, so that the pixels are charged sufficiently, and the corresponding opening time of each pixel is conveniently configured within one frame time.
In this embodiment, the display panel includes a data driving circuit 100, a timing control circuit 200, an array substrate 300, and a plurality of scan driving circuits 400, and each scan driving circuit 400 is connected to the timing control circuit 200. The timing control circuit 200 is configured to generate a plurality of sets of clock signals, and transmit the sets of clock signals to the scan driving circuits 400 in a one-to-one correspondence manner, where the turn-on time of each set of clock signals is different. The scan driving circuit 400 is configured to drive the pixels in the corresponding row of the array substrate 300 according to a corresponding clock signal, wherein an on time corresponding to the clock signal received by the scan driving circuit 400 far from the driving side is longer than an on time corresponding to the clock signal received by the scan driving circuit 400 near the driving side. The present embodiment can configure the turn-on time of the corresponding scan driving circuit 400 according to the charging time required for the pixel; for pixels near the driving side with shorter charging time, a shorter turn-on time may be configured for the corresponding scan driving circuit 400; for the pixels far from the driving side with longer charging time, the corresponding scan driving circuit 400 may be configured with longer turn-on time, so that all the pixels in the array substrate 300 are charged sufficiently, and the phenomenon that part of the pixels are insufficiently charged to cause darker display is avoided.
Example two
Referring to fig. 3, fig. 3 is a flowchart illustrating a display panel driving method according to a second embodiment of the present invention, and an embodiment of the display panel driving method according to the present invention is provided based on the above-mentioned hardware structure.
In this embodiment, a specific structure of the display panel may refer to fig. 1, and a specific description may refer to the foregoing example, and the display panel driving method includes the steps of:
step S10: a plurality of sets of clock signals are generated according to the preset time parameter, and the sets of clock signals are correspondingly transmitted to the scan driving circuits 400 one by one, wherein the turn-on time of each set of clock signals is different.
In the present embodiment, in order to avoid insufficient charging of pixels in each row away from the driving side of the array substrate 300, the scan lines in the array substrate 300 are driven in groups. For example, if the data of the scanning lines is 1080 lines, two sets of scanning driving circuits 400 may be provided, and each scanning driving circuit 400 drives 540 lines. The scan driving circuit 400 far from the driving side is the scan driving circuit 400 driving the scan lines above the array substrate 300; the scan driving circuit 400 near the driving side refers to the scan driving circuit 400 that drives the scan lines located under the array substrate 300. Of course, if the data of the scanning lines is 1080 lines, three, four, etc. groups of scanning driving circuits 400 may be provided to drive the scanning lines in groups.
It should be noted that the preset time parameter may be an on time corresponding to the group clock signal. In specific implementation, the preset time parameter includes a plurality of opening times, and the generation of the plurality of groups of clock signals according to the preset time parameter may be: determining the number of clock signals required by each scan driving circuit 400 and the corresponding turn-on time of each scan driving circuit 400; the clock signal group corresponding to each scan driving circuit 400 is generated according to the turn-on time and the number of the clock signals corresponding to each scan driving circuit 400, and a plurality of groups of clock signals are obtained.
It is understood that each scan driving circuit 400 may include a plurality of GOA (Gate drive on Array) circuits. Each GOA circuit requires a corresponding clock signal to drive. As shown in fig. 2, the number of clock signals corresponding to each GOA circuit is four, and as shown in fig. 2, from top to bottom, the first row signal and the sixth row signal are frame start signals; the second to fifth row signals are a first group of clock signals for driving the scan driving circuit 400 away from the driving side; the seventh to tenth row signals are a second group of clock signals for driving the scan driving circuit 400 near the driving side; and the starting time corresponding to the first group of clock signals is longer than the starting time corresponding to the second group of clock signals. Of course, the number of clock signals corresponding to a group of clock signals may be different according to the specific structure of the GOA circuit.
In specific implementation, the clock signal may be a pulse signal, the GOA circuit may output a scan signal when the clock signal is at a high potential, and the GOA circuit does not output the scan signal when the clock signal is at a low potential; wherein, the duration of the high potential in one period is the turn-on time corresponding to the clock signal.
Step S20: the pixels in the corresponding row of the array substrate 300 are driven according to the clock signal corresponding to each scan driving circuit 400, wherein the turn-on time corresponding to each group of clock signals is different, and the turn-on time corresponding to the clock signal received by the scan driving circuit 400 far away from the driving side is longer than the turn-on time corresponding to the clock signal received by the scan driving circuit 400 near the driving side.
It is understood that the data driving circuit 100 is used to convert video signals into data voltages and apply the data voltages to the pixels through the data lines of the columns, so that the pixels perform display. The data driving circuit 100 is usually disposed at one end of a data line in the array substrate 300; for example, the data driving circuit 100 may be disposed above or below the data lines disposed in the column direction. If the data driving circuit 100 is disposed below the array substrate 300, the data voltage is transmitted from below to above as a driving side. At this time, if the size of the array substrate 300 is large, the voltage of each row of pixels located above the array substrate 300 tends to rise slowly.
Each scan driving circuit 400 outputs a scan signal to a corresponding scan line under the driving of a clock signal to turn on a TFT (Thin Film Transistor) device of a corresponding pixel, so that the pixel is charged by a data voltage. Since each scan driving circuit 400 can be configured independently, the corresponding turn-on time can be configured according to the required charging time. For pixels near the driving side with shorter charging time, a shorter turn-on time may be configured for the corresponding scan driving circuit 400; for the pixels far from the driving side with longer charging time, the corresponding scan driving circuit 400 may be configured with longer turn-on time, so that all the pixels in the array substrate 300 are charged sufficiently, and the power consumption of the display panel is not increased.
In this embodiment, a plurality of groups of clock signals are generated according to the preset time parameter, and the groups of clock signals are transmitted to the scan driving circuits 400 in a one-to-one correspondence manner, wherein the turn-on time of each group of clock signals is different; the pixels in the corresponding row of the array substrate 300 are driven according to the clock signal corresponding to each scan driving circuit 400, wherein the turn-on time corresponding to each group of clock signals is different, and the turn-on time corresponding to the clock signal received by the scan driving circuit 400 far away from the driving side is longer than the turn-on time corresponding to the clock signal received by the scan driving circuit 400 near the driving side. The present embodiment can configure the turn-on time of the corresponding scan driving circuit 400 according to the charging time required for the pixel; for pixels near the driving side with shorter charging time, a shorter turn-on time may be configured for the corresponding scan driving circuit 400; for the pixels far from the driving side with longer charging time, the corresponding scan driving circuit 400 may be configured with longer turn-on time, so that all the pixels in the array substrate 300 are charged sufficiently, and the phenomenon that part of the pixels are insufficiently charged to cause darker display is avoided.
EXAMPLE III
Referring to fig. 4, fig. 4 is a flowchart illustrating a display panel driving method according to a third embodiment of the present invention, and based on the above embodiment, a display panel driving method according to yet another embodiment of the present invention is provided.
In this embodiment, step S10 may include:
step S101: and generating a plurality of groups of clock signals according to the preset time parameters.
It should be noted that the preset time parameter may be an on time corresponding to the group clock signal, and the preset time parameter includes a plurality of on times. In this embodiment, a display panel including two scan driver circuits 400 will be described as an example. The preset time parameter comprises a first opening time and a second opening time, wherein the first opening time is greater than the second opening time. Specific values of the first opening time and the second opening time may be set according to user requirements, and this embodiment is not limited thereto.
In a specific implementation, step S101 may include: generating a first clock signal according to the first opening time; and generating a second clock signal according to the second opening time.
It is understood that the first clock signal corresponds to a first on time, and the second clock signal corresponds to a second on time. The first clock signal is used for transmitting to a first scanning driving circuit far away from the driving side, and the second clock signal is used for transmitting to a second scanning driving circuit close to the driving side.
Generally, the turn-on time of all scan lines in the array substrate needs to be completed within one frame time, and therefore, to ensure that the total turn-on time meets the requirement, the process of determining the turn-on time in the embodiment may be: acquiring a first clock correction value; and adding the preset opening time and the first clock correction value to obtain the first opening time. Acquiring a second clock correction value; and subtracting the second clock correction value from the preset opening time to obtain a second opening time.
It should be noted that the preset on time is the on time corresponding to the scan lines when all the scan lines are driven with the same on time. In order to calculate faster, the preset on-time may be determined according to the refresh rate and/or resolution of the picture, and the calculation method of the preset on-time is a mature technology, which is not described herein again.
It will be appreciated that increasing the on-time of the scan lines away from the drive side results in an increase in the total scan time, which is limited due to the refresh rate or resolution requirements of the picture. To avoid the total scan line length being too long, it is necessary to reduce the on time of the scan line close to the driving side. In a specific implementation, the first clock correction value may be equal to the second clock correction value, and the adjusted total scanning requirement may still meet the requirements of the refresh rate and/or resolution of the picture by increasing and decreasing the opening time of the two portions by the same amplitude. Specific values of the first clock correction value and the second clock correction value may be set according to user requirements, and this embodiment is not limited thereto.
Step S102: the corresponding frame start signal is generated according to the driving order of each scan driving circuit 400.
It is understood that the frame start signal is used to drive the scan driving circuits 400 to be turned on, and each scan driving circuit 400 is driven by using one frame start signal in order to drive each scan driving circuit 400. Wherein the driving sequence may be driving from the far driving side to the near driving side or driving from the near driving side to the far driving side.
In a specific implementation, the first-stage GOA circuit in each scan driving circuit 400 outputs a scan signal when receiving a frame start signal; and simultaneously driving the next-stage GOA circuit to be started. After all the GOA circuits in one group of scan driving circuits 400 are turned on, the first-stage GOA circuits in the next group of scan driving circuits 400 are driven to be turned on by a frame start signal. With continued reference to fig. 2, the frame start signal of the first row is used to drive the scan driving circuit 400 away from the driving side, and the frame start signal of the sixth row is used to drive the scan driving circuit 400 close to the driving side.
Step S103: each set of clock signals and the corresponding frame start signal are transmitted to each scan driving circuit 400 in a one-to-one correspondence.
It is understood that the scan driving circuit 400 outputs scan signals to the scan lines to drive the TFT devices corresponding to the pixels to be turned on when receiving corresponding clock signals and frame start signals. Simultaneously, the pixel is charged by matching with the applied data voltage.
To more clearly illustrate the influence of this embodiment on the charging process, referring to fig. 5-8, fig. 5 is a first schematic diagram of charging a pixel close to the driving side in the third embodiment of the present invention, fig. 6 is a first schematic diagram of charging a pixel far from the driving side in the third embodiment of the present invention, fig. 7 is a second schematic diagram of charging a pixel close to the driving side in the third embodiment of the present invention, and fig. 8 is a second schematic diagram of charging a pixel far from the driving side in the third embodiment of the present invention. Fig. 5 and 6 show the pixel charging process when the pixel units in each row are driven at the same turn-on time, and fig. 7 and 8 show the pixel charging process when the pixel units in each row are driven at different turn-on times. The Gate is a scanning signal, the Data is a Data signal, the TFT device is turned on when the scanning signal is at a high potential, the pixel unit starts to be charged under the action of the Data signal, the potential gradually increases, and the dotted line position in the figure indicates the time when the charging process of the pixel unit reaches the highest voltage. As can be seen from fig. 5 and 6, when the scanning lines are driven at the same turn-on time, the charging voltage of the pixel far from the driving side reaches the maximum value when the corresponding TFT device is turned off, that is, the pixel unit is not charged before the TFT device is turned off, so the maximum value of the pixel unit may not reach the preset value, and the situation of insufficient charging is likely to occur; as can be seen from fig. 7 and 8, the turn-on time corresponding to the pixel far from the driving side is longer than the turn-on time corresponding to the pixel near the driving side, all the pixels complete charging before the corresponding TFT devices are turned off, and the charging voltage reaches the preset value.
In the embodiment, a plurality of groups of clock signals are generated according to preset time parameters; generating corresponding frame start signals according to the driving sequence of each scanning driving circuit 400; each set of clock signals and the corresponding frame start signal are transmitted to each scan driving circuit 400 in a one-to-one correspondence. In this embodiment, each scan driving circuit 400 is driven by a frame start signal independently, which facilitates switching between scan driving circuits 400 and stabilizes the driving of scan lines.
Example four
In addition, in order to achieve the purpose, the invention also provides a display. Referring to fig. 9, fig. 9 is a schematic structural diagram of a display according to a fourth embodiment of the present invention. The display includes the display panel 500 and the backlight module 600 as described above, the backlight module 600 is disposed on the back of the display panel 500, and the backlight module 600 is used for providing a backlight source for the display panel 500. The specific structures of the display panel and the display panel driving device can refer to the foregoing descriptions, and since the display can adopt the technical solutions of all the embodiments, the display at least has the beneficial effects brought by the technical solutions of the embodiments, and the descriptions are omitted here.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present invention or portions thereof that contribute to the prior art may be embodied in the form of a software product, where the computer software product is stored in a storage medium (e.g., a Read Only Memory (ROM)/Random Access Memory (RAM), a magnetic disk, an optical disk), and includes several instructions for enabling a terminal device (which may be a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A display panel comprises a data driving circuit, a time sequence control circuit and an array substrate, wherein the data driving circuit is arranged at the driving side of the array substrate;
the time sequence control circuit is used for generating a plurality of groups of clock signals and transmitting the groups of clock signals to the scanning driving circuits in a one-to-one correspondence manner, wherein the starting time of each group of clock signals is different;
the scanning driving circuit is used for driving the pixels of the corresponding row in the array substrate according to the corresponding clock signal, wherein the starting time corresponding to the clock signal received by the scanning driving circuit far away from the driving side is longer than the starting time corresponding to the clock signal received by the scanning driving circuit close to the driving side.
2. The display panel of claim 1, wherein the timing control circuit is further configured to generate a plurality of frame start signals and transmit the frame start signals to the scan driving circuits in a one-to-one correspondence;
and the scanning driving circuit is further used for driving the pixels of the corresponding row in the array substrate according to the corresponding clock signal when the corresponding frame starting signal is received.
3. The display panel of claim 1, wherein the clock signal further from the driving side corresponds to a start trigger time that precedes the clock signal closer to the driving side.
4. A display panel driving method, a display panel including a data driving circuit and an array substrate, the data driving circuit being disposed on a driving side of the array substrate, the display panel driving method being applied to the display panel according to any one of claims 1 to 3, the display panel being further provided with a plurality of scan driving circuits, the display panel driving method comprising the steps of:
generating a plurality of groups of clock signals according to preset time parameters, and transmitting the groups of clock signals to each scanning driving circuit in a one-to-one correspondence manner, wherein the starting time corresponding to each group of clock signals is different;
and driving the pixels of the corresponding row in the array substrate according to the clock signals corresponding to the scanning driving circuits, wherein the starting time corresponding to each group of clock signals is different, and the starting time corresponding to the clock signal received by the scanning driving circuit far away from the driving side is greater than the starting time corresponding to the clock signal received by the scanning driving circuit close to the driving side.
5. The method for driving a display panel according to claim 4, wherein the generating a plurality of sets of clock signals according to the preset time parameter and transmitting the sets of clock signals to the scan driving circuits in a one-to-one correspondence includes:
generating a plurality of groups of clock signals according to preset time parameters;
generating corresponding frame start signals according to the driving sequence of each scanning driving circuit;
and transmitting each group of clock signals and the corresponding frame start signals to each scanning driving circuit in a one-to-one correspondence manner.
6. The display panel driving method of claim 5, wherein the preset time parameter comprises a plurality of turn-on times;
the generating of the plurality of groups of clock signals according to the preset time parameters includes:
determining the number of clock signals required by each scanning driving circuit and the corresponding starting time of each scanning driving circuit;
and generating a clock signal group corresponding to each scanning driving circuit according to the starting time and the number of the clock signals corresponding to each scanning driving circuit to obtain a plurality of groups of clock signals.
7. The display panel driving method of claim 4, wherein the preset time parameter includes a first on time and a second on time;
the generating a plurality of groups of clock signals according to the preset time parameter and transmitting the groups of clock signals to the scanning driving circuits in a one-to-one correspondence manner includes:
generating a first clock signal according to the first starting time, and transmitting the first clock signal to a first scanning driving circuit far away from the driving side;
and generating a second clock signal according to the second turn-on time, and transmitting the second clock signal to a second scanning driving circuit close to the driving side, wherein the first turn-on time is longer than the second turn-on time.
8. The display panel driving method according to claim 7, wherein before generating the first clock signal according to the first on time, further comprising:
acquiring a first clock correction value;
and adding the preset opening time and the first clock correction value to obtain first opening time.
9. The display panel driving method according to claim 8, wherein before generating the second clock signal according to the second on time, further comprising:
acquiring a second clock correction value;
and subtracting the second clock correction value from the preset opening time to obtain a second opening time.
10. A display, comprising the display panel as claimed in any one of claims 1 to 3 and a backlight module, wherein the backlight module is disposed on a back surface of the display panel, and the backlight module is configured to provide a backlight source to the display panel.
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| CN202111207436.4A CN113643645A (en) | 2021-10-18 | 2021-10-18 | Display panel, display panel driving method and display |
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| CN202111207436.4A CN113643645A (en) | 2021-10-18 | 2021-10-18 | Display panel, display panel driving method and display |
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