CN116633349A - Fractional phase-locked loop with low clock jitter - Google Patents

Fractional phase-locked loop with low clock jitter Download PDF

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Publication number
CN116633349A
CN116633349A CN202310612194.XA CN202310612194A CN116633349A CN 116633349 A CN116633349 A CN 116633349A CN 202310612194 A CN202310612194 A CN 202310612194A CN 116633349 A CN116633349 A CN 116633349A
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Prior art keywords
phase
output
detection circuit
fractional
clock
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CN202310612194.XA
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Inventor
陆兆俊
常龙鑫
杨煜
徐玉婷
涂波
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Wuxi Zhongwei Yixin Co Ltd
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Wuxi Zhongwei Yixin Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

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Abstract

The application discloses a fractional phase-locked loop with low clock jitter, which relates to the technical field of fractional phase-locked loops, wherein a pipeline converter is arranged in the fractional phase-locked loop to copy fractional clock signals in a phase mirror image mode and output multipath feedback signals to multipath phase-frequency detectors respectively through a pipeline output mechanism, each path of phase-frequency detector and a charge pump independently identify the instantaneous phase difference of an input reference clock and feedback signals, and the phase-frequency detectors and the charge pump are in a pipeline operation mode, so that the phase-frequency detection is carried out by staggering one clock period, the instantaneous phase differences generated by a plurality of instantaneous frequency division ratios are subjected to circuit conversion, and the voltage-controlled voltage fluctuation generated by the instantaneous phase differences in the same time can be effectively reduced, so that the fluctuation amplitude of voltage-controlled voltage can be reduced under the condition that the reference clock and loop parameters are not changed, the jitter of the fractional phase-locked loop is reduced, and the application scene that the frequency resolution of an output clock is high and the jitter of the output clock is low can be satisfied.

Description

Fractional phase-locked loop with low clock jitter
Technical Field
The application relates to the field of fractional phase-locked loops, in particular to a fractional phase-locked loop with low clock jitter.
Background
The charge pump phase-locked loop is a mature and wide method for realizing the frequency synthesizer at present, and the circuit comprises a phase frequency detector, a charge pump, a loop filter and a voltage-controlled oscillator which are sequentially connected in series, wherein one input of the phase frequency detector acquires a reference frequency, and the output frequency of the voltage-controlled oscillator is returned to the other input of the phase frequency detector through a frequency divider. According to the difference of frequency dividers, the charge pump phase-locked loop can be divided into an integer phase-locked loop and a fractional phase-locked loop, the output frequency of the integer phase-locked loop can only be an integer multiple of the reference frequency, the inherent defect exists, and the requirements of a modern communication system on higher and higher indexes such as frequency conversion speed, precision and noise are difficult to meet. The fractional phase-locked loop well solves the contradiction between the channel interval and the reference frequency because the output frequency can be a small multiple of the reference frequency, and has the advantages of high frequency switching speed, high precision and small noise, and is getting more attention.
The fractional frequency divider used by the fractional phase-locked loop is a programmable frequency divider, and the frequency dividing mode of the fractional frequency divider can be automatically switched according to the requirement of the frequency dividing ratio by utilizing external control logic, so that the purpose of fractional frequency division is achieved on average. However, this switching of the frequency division mode introduces a serious problem to the frequency synthesizer, that is, the occurrence of fractional spurious in the output frequency spectrum is mainly caused by instantaneous phase errors, and after the phase errors varying with time pass through the phase frequency discriminator, the charge pump and the loop filter, a period disturbance is generated at the voltage control terminal of the voltage controlled oscillator, so that the occurrence of fractional spurious in the final output frequency spectrum becomes a main problem restricting the application of the fractional phase locked loop.
Disclosure of Invention
The present inventors have proposed a fractional phase-locked loop with low clock jitter, which is directed to the above-mentioned problems and technical needs, and the technical scheme of the present application is as follows:
the fractional phase-locked loop with low clock jitter comprises K phase frequency detectors, K charge pumps, a loop filter, a voltage-controlled oscillator, a fractional frequency divider and a pipeline converter, wherein K is more than or equal to 3, and the fractional frequency divider is based on a delta-sigma modulator design;
the fractional frequency divider performs fractional frequency division on an oscillation clock Fvco output by the voltage-controlled oscillator to generate a frequency division clock signal Dout;
the pipeline converter copies the frequency division clock signal Dout of the fractional frequency divider in a phase mirror image mode and outputs K paths of feedback signals by a pipeline output mechanism, wherein the output K paths of feedback signals comprise the frequency division clock signal Dout and signals obtained by time delay of the frequency division clock signal Dout, and the K paths of feedback signals are sequentially delayed by one clock cycle;
the output ends of the phase frequency detectors are connected with a corresponding charge pump, and the output ends of the charge pumps are connected with the input ends of the loop filter;
the loop filter filters the output charges of all K charge pumps and generates a tuning voltage VCTRL to be provided to the voltage-controlled oscillator, which outputs an oscillation clock Fvco according to the tuning voltage VCTRL.
The pipeline converter comprises a plurality of output phase mirror image modules which are sequentially cascaded, a frequency division clock signal Dout is input to the output phase mirror image modules of the first stage and is output as one feedback signal Fb, the circuit structures of the output phase mirror image modules of each stage are the same, for each stage of output phase mirror image module, the output phase mirror image module completely mirrors an input signal Sig and outputs a corresponding one feedback signal Fb, the output pulse feedback signal Fb mirrors the rising edge of the input signal Sig, and the feedback signal Fb is delayed by one clock period compared with the rising edge of the input signal Sig.
The further technical scheme is that each output phase mirror module comprises a phase detection unit and a phase delay unit, the phase detection unit charges an internal capacitor according to a preset charging speed in one clock period of an input signal Sig, and outputs a peak voltage Vt reached by the internal capacitor to the phase delay unit when the current clock period of the signal Sig is ended, and the phase delay unit starts to charge the internal capacitor according to the preset charging speed when the next clock period of the input signal Sig arrives until a feedback signal Fb in a pulse form is output when the peak voltage Vt is reached.
The further technical scheme is that the phase detection unit comprises a D trigger DFF1, a first phase detection circuit, a second phase detection circuit and a peak detection circuit, wherein the circuit structures of the first phase detection circuit and the second phase detection circuit are the same, and each phase detection circuit comprises a current source and a capacitor;
the clock end of the D trigger DFF1 acquires a signal Sig input to the current-stage output phase mirror module, and the input end of the D trigger DFF1 is connected with the reverse output end; the input end of the first phase detection circuit is connected with the forward output end of the D trigger DFF1, the input end of the second phase detection circuit is connected with the reverse output end of the D trigger DFF1, and the output end of the first phase detection circuit and the output end of the second phase detection circuit are both connected with the peak detection circuit;
when the input signal Sig is in a high level or a low level, the D trigger DFF1 triggers the first phase detection circuit or the second phase detection circuit to charge an internal capacitor according to a preset charging speed by utilizing an internal current source; when one clock cycle of the signal Sig ends, the peak detection circuit detects the output of the first phase detection circuit or the second phase detection circuit to obtain the peak voltage Vt and sends it to the phase delay unit.
In each phase detection circuit, the positive electrode of a current source Id1 is connected with a power supply voltage VDD, the negative electrode of the current source Id1 is connected with the source electrode of a PMOS tube MP1, the drain electrode of the PMOS tube M1 is connected with the drain electrode of an NMOS tube MN2, the source electrode of the MN2 is grounded, the grid electrode of the MP1 is connected with the grid electrode of the MN2 and is used as the input end of the phase detection circuit, the drain electrode of the MP1 is grounded through a capacitor Cd1, and the drain electrode of the MP1 is also connected with the output end of the phase detection circuit;
when the input signal Sig is at a high level or a low level, the D flip-flop DFF1 triggers and turns on the MP1 in the first phase detection circuit or the second phase detection circuit, so that the current source Id1 in the phase detection circuit charges the capacitor Cd1 to raise the voltage at the output end of the phase detection circuit, and after one clock period is finished, the peak voltage vt=tsig (Id 1/Cd 1) output by the peak detection circuit, where Tsig is the period duration of one clock period of the input signal Sig.
The phase delay unit comprises a comparator CMP1, a pulse generator and a charging circuit, wherein the charging circuit comprises a current source Id2 and a capacitor Cd2, the negative input end of the comparator CMP1 is connected with the phase detection unit to obtain peak voltage Vt, the negative input end of the comparator CMP1 is also grounded through a capacitor Ct, and the output end of the charging circuit is connected with the positive input end of the comparator CMP 1;
the input end of the pulse generator is connected with the input end of the output phase mirror module to acquire an input signal Sig, the pulse generator outputs a trigger pulse when the next clock period of the input signal Sig arrives, the charging circuit charges the capacitor Cd2 according to a preset charging speed by using an internal current source Id2 under the action of the trigger pulse, so that the output voltage Vd3 of the charging circuit rises until the output voltage Vd3 of the charging circuit rises to reach a peak voltage, and the output end of the comparator CMP1 outputs a feedback signal Fb in a positive pulse form.
In the charging circuit, the reset end of the D trigger DFF2 is connected with the output end of the pulse generator, the forward output end of the D trigger DFF2 is connected with the grid electrode of the NMOS tube MN3, the source electrode of the MN3 is grounded, and the drain electrode of the MN3 is connected with the positive input end of the comparator CMP 1; the positive electrode of the current source Id2 is connected with the power supply voltage VDD, the negative electrode of the current source Id2 is connected with the positive input end of the comparator CMP1, and the positive input end of the comparator CMP1 is grounded through a capacitor Cd 2;
d trigger DFF2 resets under the effect of trigger pulse and outputs low level through forward output end in order to control MN3 to close, and electric current source Id2 charges electric capacity Cd2 for the voltage of comparator CMP 1's positive input end rises.
The further technical scheme is that the output end of the comparator CMP1 is also connected with the clock end of the D trigger DFF2, the input end of the D trigger DFF2 is connected with the power supply voltage VDD, when the comparator CMP1 outputs the feedback signal Fb in the form of positive pulse, the D trigger DFF2 outputs high level through the positive output end to control the MN3 to be conducted, and the voltage of the positive input end of the comparator CMP1 is reset to 0.
The delta-sigma modulator in the fractional frequency divider adopts a high-order structure of cascade connection of multi-level modulators, each level of modulator of the delta-sigma modulator is introduced with quantization noise, the output of each level of the cascade connection of the delta-sigma modulator is counteracted with the quantization noise of the previous level, the output of the delta-sigma modulator only comprises the input and the quantization noise of the last level of modulator, and the quantization noise is filtered by a loop filter.
The method comprises the further technical scheme that the fractional frequency divider comprises a delta-sigma modulator, a counting controller, a programmable counter, a swallowing counter and a dual-mode frequency divider, wherein the delta-sigma modulator generates pseudo-random codes according to a decimal configuration signal and a frequency division clock signal Dout and provides the pseudo-random codes to the counting controller, and the counting controller configures the maximum counting period of the programmable counter and the maximum counting period of the swallowing counter according to the pseudo-random codes, the integer configuration signal and the frequency division clock signal Dout;
when the dual-mode frequency divider works in the n+1 mode, the dual-mode frequency divider pre-divides the oscillating clock Fvco and then sends the oscillating clock Fvco to the programmable counter and the swallowing counter, the swallowing counter finishes counting first and sends Sout pulse to the dual-mode frequency divider to trigger the dual-mode frequency divider to switch to the N mode and stop working until the programmable counter finishes counting and outputs a frequency division clock signal Dout, the instantaneous frequency division ratio of the dual-mode frequency divider is N x p+s, p is the maximum count value of the programmable counter, and s is the maximum count value of the swallowing counter.
The beneficial technical effects of the application are as follows:
the application discloses a fractional phase-locked loop with low clock jitter, wherein a pipeline converter is arranged in the fractional phase-locked loop to copy a fractional clock signal in a phase mirror image mode and output multipath feedback signals to multipath phase-frequency detectors respectively in a pipeline output mechanism, each path of phase-frequency detectors and a charge pump independently identify the instantaneous phase difference of an input reference clock and feedback signals, and the phase-frequency detectors and the charge pump are in a pipeline operation mode, so that the instantaneous phase differences generated by a plurality of instantaneous frequency division ratios are subjected to circuit conversion, the voltage-controlled voltage fluctuation generated by the instantaneous phase differences in the same time can be effectively reduced, and a fluctuation value which is not larger than the fluctuation range of the original voltage-controlled voltage is superimposed on a loop filter, so that the fluctuation amplitude of the voltage-controlled voltage is reduced under the condition that the reference clock and loop parameters are not changed, the jitter of the fractional phase-locked loop is reduced, and the application scene that the output clock frequency resolution is high and the output clock jitter is low can be met.
The modulation count of the delta-sigma modulator may be such that the fractional-divided instantaneous phase difference is as small as possible and as evenly distributed as possible over a certain period of time, further reducing the clock jitter of the fractional phase locked loop. The application of the high-order delta-sigma modulator can shift the quantization noise to the high-order position to be filtered by the loop filter, so that the clock jitter of the fractional phase-locked loop is further reduced.
The fractional phase-locked loop of the application extends the design thought of the classical fractional phase-locked loop, has simple structure and does not carry out complex change. Under the condition of keeping the total current unchanged, the phase frequency detector and the charge pump are split into a plurality of groups, each group works independently, the instantaneous phase difference output by the reference clock and the fractional frequency divider is converted into the charge difference, and the charge difference is summarized on the loop filter. Compared with the method for compensating the instantaneous phase difference by using the TDC and the method for compensating the charge pump current by using the DAC, the method has lower design requirements on the submodule and the loop. Firstly, the TDC/DAC is designed with high precision, and under the influence of PVT, analog mismatch of the two modules is easy to occur; secondly, the modules are applied to the phase-locked loop, a series of factors such as loop bandwidth and the like are needed to be considered, and finally, the fluctuation of the voltage-controlled voltage is counteracted, so that the technical difficulty is not small. The analog circuit with relatively high design requirements is an output phase mirror module, but the analog circuit is only a trigger, an operational amplifier and other conventional simple circuits which are applied in the analog circuit, and the analog circuit is influenced by PVT, the copied phases of the two output phase mirror modules can generate a little deviation, but the deviation of a single output phase mirror module can be weakened into one third due to the working mode of multistage flow, and the deviation in the same trend can be automatically regulated and offset by a loop, so that the normal function of the phase-locked loop is not influenced. Therefore, the application also solves the problems of high design difficulty of DAC/TDC compensation technical scheme, large area of finite impulse response technical scheme and high power consumption, and can realize the reduction of voltage-controlled voltage fluctuation and the reduction of output clock jitter of the fractional phase-locked loop with lower design difficulty under the condition of keeping the stability and fault tolerance of the original mature loop structure. Compared with the finite impulse response technology, the application only needs one fractional frequency divider, thereby greatly saving the chip area and the power consumption.
Drawings
Fig. 1 is a circuit configuration diagram of a fractional phase locked loop according to an embodiment of the present application.
Fig. 2 is a circuit configuration diagram of a fractional divider according to an embodiment of the present application.
Fig. 3 is a circuit configuration diagram of a pipeline converter according to an embodiment of the present application.
Fig. 4 is a circuit diagram of a single output phase mirror module according to one embodiment of the application.
Detailed Description
The following describes the embodiments of the present application further with reference to the drawings.
Referring to fig. 1, the fractional phase-locked loop includes K phase frequency detectors, K charge pumps, a loop filter, a voltage-controlled oscillator, a fractional frequency divider and a pipeline converter, where K is greater than or equal to 3, and k=3 can be taken as a common value. The K phase frequency detectors are shown as 1 in the figures, wherein the K phase frequency detectors are 1-K phase frequency detectors, the K charge pumps are 1-K charge pumps, and the K phase frequency detectors and the K charge pumps are in one-to-one correspondence.
The fractional divider divides the oscillating clock Fvco output from the voltage controlled oscillator by a fraction to generate a divided clock signal Dout, which is provided to the pipeline converter. The pipeline converter copies the frequency division clock signal Dout of the fractional frequency divider in a phase mirror image mode and outputs K paths of feedback signals Fb by a pipeline output mechanism, wherein the output K paths of feedback signals Fb comprise the frequency division clock signal Dout and signals obtained by time delay of the frequency division clock signal Dout, and one time delay is carried out on the K paths of feedback signals in sequenceAnd (3) a clock period. The application respectively writes K paths of feedback signals Fb which are sequentially output according to a pipeline output mechanism as Fb 1 ～Fb K For example, fb 1 For the frequency-divided clock signal Dout, any feedback signal Fb k Compared with the former feedback signal Fb k-1 Delay by one clock period, K is a parameter and K is more than or equal to 2 and less than or equal to K.
The K feedback signals Fb output by the pipeline converter are respectively output to one input end of the K phase frequency detectors, and any K feedback signal Fb k And outputting the reference clock Fref to the kth phase frequency detector, and acquiring the reference clock Fref from the other input ends of all the K phase frequency detectors. The output end of each phase frequency detector is connected with a corresponding charge pump, and each phase frequency detector carries out phase frequency detection on the reference clock Fref and one input feedback signal and outputs a phase difference, and the phase difference is expressed as different output charges on the corresponding charge pump.
The output ends of all K charge pumps are connected with the input end of the loop filter. The loop filter filters the output charges of all K charge pumps and generates a tuning voltage VCTRL to be provided to the voltage-controlled oscillator, which outputs an oscillation clock Fvco according to the tuning voltage VCTRL. The current values of the K charge pumps are changed into 1/K of the output current value of the charge pump with a classical structure, the effect of current averaging is realized on the basis that the circuit structure is a current summation function, and additional loop analysis is not needed, so that the design complexity is reduced.
Although the phase difference of the multipath feedback signals Fb output by the pipeline converter is not reduced when the phase is detected, the frequency-detecting phase detectors independently detect the instantaneous phase difference of the input reference clock Fref and the feedback signals Fb, and the frequency-detecting phase detectors are staggered by one clock cycle in a pipeline operation mode, so that the instantaneous phase difference generated by the instantaneous frequency division ratios is subjected to circuit conversion, and a fluctuation value which is not greater than the original voltage fluctuation range is superimposed on the loop filter, so that the tuning voltage VCTRL with fewer voltage fluctuation can be output, and the output jitter of the voltage-controlled oscillator is reduced.
In addition, the fractional frequency divider in the fractional phase-locked loop of the application is designed based on a delta-sigma modulator, and further, the delta-sigma modulator in the fractional frequency divider adopts a high-order structure of cascade connection of multi-stage modulators. For example, in one embodiment, a delta-sigma modulator employing a MASH 1-1-1 architecture includes three first order modulators cascaded. The delta-sigma modulator adopting the high-order structure introduces quantization noise into each stage of modulator, and allows the output of each stage of the cascaded delta-sigma modulator to cancel the quantization noise of the previous stage in order to realize noise shaping and consider the stability of the circuit, so that the output of the whole delta-sigma modulator only comprises the input and the quantization noise of the last stage of modulator, and the quantization noise is filtered by the loop filter.
In one embodiment, as shown in fig. 2, the fractional divider includes a delta-sigma modulator, a count controller, a programmable counter, a swallow counter, and a dual-mode divider, and the fractional divider also obtains an external integer configuration signal Int and a fractional configuration signal Frac, which in one embodiment includes 16 bits and the fractional configuration signal Frac includes 7 bits. Within the fractional divider, a delta-sigma modulator generates a 3-bit pseudo-random code delta-sigma in the range of-3 to 4 at each clock cycle of the fractional divider output based on the fractional configuration signal Frac and the divided clock signal Dout, which is provided to a count controller. The count controller configures a maximum count period of the programmable counter and a maximum count period of the swallowing counter according to the pseudo-random code, the integer configuration signal Int, and the frequency division clock signal Dout. The programmable counter and the swallowing counter are of universal structures, specific circuits are not described in the application, and the maximum period of the two counters configured by the integer signal Int can dynamically change along with 3bit pseudo-random codes of-3 to 4, so that the decimal function is realized by averaging in a longer time.
When the dual-mode frequency divider works in the n+1 mode, the dual-mode frequency divider Pre-divides the oscillating clock Fvco to obtain Pre and sends the Pre to the programmable counter and the swallowing counter, the swallowing counter finishes counting firstly because the number of counting bits of the swallowing counter is small, the swallowing counter finishes counting firstly and sends Sout pulse to the dual-mode frequency divider to trigger the dual-mode frequency divider to switch to the N mode and stop working until the programmable counter finishes counting and outputs a frequency division clock signal Dout, the instantaneous frequency division ratio of the dual-mode frequency divider is N x p+s, p is the maximum count value of the programmable counter, and s is the maximum count value of the swallowing counter.
The pipeline converter comprises a plurality of output phase mirror image modules which are sequentially cascaded, as shown in fig. 3, a frequency division clock signal Dout is input to the output phase mirror image module of the first stage as an input signal Sig of the output phase mirror image module of the first stage, and the frequency division clock signal Dout is directly output as a feedback signal. The circuit structure of each stage of output phase mirror image module is the same, for each stage of output phase mirror image module, the output phase mirror image module completely mirrors the input signal Sig and outputs a corresponding feedback signal Fb, and the feedback signal Fb output by the output phase mirror image module of each stage is also used as the signal Sig input into the output phase mirror image module of the next stage. The output pulse-form feedback signal Fb mirrors the rising edge of the input signal Sig, and the feedback signal Fb is delayed by one clock cycle compared to the rising edge of the input signal Sig. Because the classical tri-state phase frequency detector only compares the phase difference of the rising edges of the signals, the feedback signal Fb output by the application mainly mirrors the rising edges of the input signal Sig, and the duration of the high level can drive the phase frequency detector without additional attention.
Referring to fig. 4, each output phase mirror module includes a phase detection unit and a phase delay unit, the phase detection unit charges an internal capacitor according to a predetermined charging speed in one clock cycle of an input signal Sig, and outputs a peak voltage Vt reached by the internal capacitor to the phase delay unit at the end of a current clock cycle of the signal Sig, and the phase delay unit starts charging the internal capacitor according to the predetermined charging speed when a next clock cycle of the input signal Sig arrives, until a feedback signal Fb in a pulse form is output when the received peak voltage Vt is reached.
In one embodiment, the phase detection unit includes a D flip-flop DFF1, a first phase detection circuit Φ1, a second phase detection circuit Φ2, and a peak detection circuit, the circuit structures of the first phase detection circuit Φ1 and the second phase detection circuit Φ2 are identical, and each phase detection circuit includes a current source Id1 and a capacitor Cd1. The clock end Clk end of the D trigger DFF1 obtains the signal input to the current-stage output phase mirror module
-sign Sig, D flip-flop DFF1 has its input connected to the inverted output Q. The input end of the first phase detection circuit phi 1 is connected with the positive output end Q of the D trigger DFF1, and the input end of the second phase detection circuit phi 2
-the inverse output Q of the D flip-flop DFF1 is connected, the output of the first phase detection circuit phi 1 and the output of the second phase detection circuit phi 2 being both connected to the peak detection circuit. The peak detection circuit may be implemented using existing circuit structures.
When the input signal Sig is at a high level or a low level, the D flip-flop DFF1 triggers the first phase detection circuit Φ1 or the second phase detection circuit Φ2 to charge the internal capacitor Cd1 at a predetermined charging speed by using the internal current source Id 1. When one clock cycle of the signal Sig ends, the peak detection circuit detects the output of the first phase detection circuit Φ1 or the second phase detection circuit Φ2 to obtain the peak voltage Vt and sends it to the phase delay unit.
In each phase detection circuit, the positive electrode of the current source Id1 is connected with the power supply voltage VDD, the negative electrode of the current source Id1 is connected with the source electrode of the PMOS tube MP1, the drain electrode of the PMOS tube M1 is connected with the drain electrode of the NMOS tube MN2, the source electrode of the NMOS tube MN2 is grounded, the grid electrode of the MP1 is connected with the grid electrode of the MN2 and is used as the input end of the phase detection circuit, the drain electrode of the MP1 is grounded through the capacitor Cd1, and the drain electrode of the MP1 is also connected with the output end of the phase detection circuit.
The D flip-flop DFF1 records the duration of the signal Sig and triggers the start of MP1 in the first phase detection circuit phi 1 or the second phase detection circuit phi 2, irrespective of whether the input signal Sig is high or low, so that the current source Id1 in the phase detection circuit charges the capacitor Cd1 and the voltage at the output of the phase detection circuit increases. The predetermined charging speed is Id1/Cd1, and after one clock period is finished, the peak voltage Vt=T outputted by the peak detection circuit sig * (Id 1/Cd 1), where T sig Is one time of the input signal SigThe period duration of the clock period.
In one embodiment, the phase delay unit includes a comparator CMP1, a pulse generator GEN, and a charging circuit, the charging circuit includes a current source Id2 and a capacitor Cd2, a negative input terminal of the comparator CMP1 is connected to the phase detection unit to obtain the peak voltage Vt, a negative input terminal of the comparator CMP1 is further grounded through the capacitor Ct, and an output terminal of the charging circuit is connected to a positive input terminal of the comparator CMP 1. The input end of the pulse generator is connected with the input end of the output phase mirror module to acquire an input signal Sig, the pulse generator outputs a trigger pulse with extremely small high-level duty ratio in a unit period when the next clock period of the input signal Sig arrives, and the higher the high-level duty ratio of the trigger pulse in the unit period is, the higher the difficulty of phase mirror is, so that the high-level duty ratio of the trigger pulse is reduced as much as possible. The charging circuit charges the capacitor Cd2 with an internal current source Id2 at a predetermined charging speed under the action of the trigger pulse, so that the output voltage Vd3 of the charging circuit rises until the output voltage Vd3 of the charging circuit rises to reach the peak voltage, and the output end of the comparator CMP1 outputs the feedback signal Fb in the form of a positive pulse. The predetermined charging speed here is the same as that of the phase detection circuit, and is denoted as Id2/Cd2, so that the same capacitance value of Cd2 and Cd1 should be ensured in the case of using the same current source, thereby ensuring the same predetermined charging speed.
In the charging circuit, a reset terminal RST of a D flip-flop DFF2 is connected to an output terminal of a pulse generator GEN, a forward output terminal Q of the D flip-flop DFF2 is connected to a gate of an NMOS tube MN3, a source of the MN3 is grounded, and a drain of the MN3 is connected to a positive input terminal of a comparator CMP 1. The positive pole of the current source Id2 is connected with the power supply voltage VDD, the negative pole of the current source Id2 is connected with the positive input end of the comparator CMP1, and the positive input end of the comparator CMP1 is grounded through the capacitor Cd 2. D trigger DFF2 resets under the effect of trigger pulse and outputs low level through forward output end in order to control MN3 to close, and electric current source Id2 charges electric capacity Cd2 for the voltage of comparator CMP 1's positive input end rises. The phase delay unit starts when the next clock cycle of the signal Sig arrives, delaying Vt (Cd 2/Id 2) =t sig And then the feedback signal Fb in the form of positive pulse is output, so that the perfect copying of the delay time can be realized.
In addition, the output terminal of the comparator CMP1 is further connected to the clock terminal Clk terminal of the D flip-flop DFF2, the input terminal D of the D flip-flop DFF2 is connected to the power supply voltage VDD, and when the comparator CMP1 outputs the feedback signal Fb in the form of a positive pulse, the D flip-flop DFF2 outputs a high level through the positive output terminal to control MN3 to turn on, and resets the voltage of the positive input terminal of the comparator CMP1 to 0.
The above is only a preferred embodiment of the present application, and the present application is not limited to the above examples. It is to be understood that other modifications and variations which may be directly derived or contemplated by those skilled in the art without departing from the spirit and concepts of the present application are deemed to be included within the scope of the present application.

Claims (10)

1. The fractional phase-locked loop with low clock jitter is characterized by comprising K phase frequency detectors, K charge pumps, a loop filter, a voltage-controlled oscillator, a fractional frequency divider and a pipeline converter, wherein K is more than or equal to 3, and the fractional frequency divider is based on a delta-sigma modulator design;
the fractional frequency divider performs fractional frequency division on an oscillation clock Fvco output by the voltage-controlled oscillator to generate a frequency division clock signal Dout;
the pipeline converter copies the frequency division clock signal Dout of the fractional frequency divider in a phase mirror image mode and outputs K paths of feedback signals by a pipeline output mechanism, wherein the output K paths of feedback signals comprise the frequency division clock signal Dout and signals obtained by delay of the frequency division clock signal Dout, and the K paths of feedback signals are delayed for one clock period in sequence;
the output ends of the K charge pumps are connected with the input ends of the loop filter;
the loop filter filters the output charges of all K charge pumps and generates a tuning voltage VCTRL to be provided to the voltage-controlled oscillator, which outputs an oscillation clock Fvco according to the tuning voltage VCTRL.
2. The fractional phase-locked loop of claim 1, wherein the pipeline converter comprises a plurality of output phase mirror modules which are cascaded in turn, the frequency division clock signal Dout is input to the output phase mirror module of the first stage and is output as a feedback signal Fb, the circuit structures of the output phase mirror modules of each stage are identical, the output phase mirror module completely mirrors the input signal Sig and outputs a corresponding feedback signal Fb for each stage, the output phase mirror module mirrors the rising edge of the input signal Sig of the output feedback signal Fb in the form of pulses, and the feedback signal Fb is delayed by one clock period compared with the rising edge of the input signal Sig.
3. The fractional phase-locked loop of claim 2, wherein each stage of the output phase mirror module comprises a phase detection unit that charges the internal capacitance at a predetermined charging rate during one clock cycle of the input signal Sig and outputs a peak voltage Vt reached by the internal capacitance to the phase delay unit at the end of the current clock cycle of the signal Sig, and a phase delay unit that starts charging the internal capacitance at the predetermined charging rate upon the arrival of the next clock cycle of the input signal Sig until the feedback signal Fb in the form of a pulse is output upon reaching the peak voltage Vt.
4. A fractional phase locked loop according to claim 3, wherein the phase detection unit comprises a D flip-flop DFF1, a first phase detection circuit, a second phase detection circuit and a peak detection circuit, the first phase detection circuit and the second phase detection circuit being identical in circuit configuration and each phase detection circuit comprising a current source and a capacitor;
the clock end of the D trigger DFF1 acquires a signal Sig input to the current-stage output phase mirror module, and the input end of the D trigger DFF1 is connected with the reverse output end; the input end of the first phase detection circuit is connected with the forward output end of the D trigger DFF1, the input end of the second phase detection circuit is connected with the reverse output end of the D trigger DFF1, and the output end of the first phase detection circuit and the output end of the second phase detection circuit are both connected with the peak detection circuit;
when the input signal Sig is at a high level or a low level, the D flip-flop DFF1 triggers the first phase detection circuit or the second phase detection circuit to charge an internal capacitor at the predetermined charging speed by using an internal current source; when one clock cycle of the signal Sig ends, the peak detection circuit detects the output of the first phase detection circuit or the second phase detection circuit to obtain the peak voltage Vt and sends the peak voltage Vt to the phase delay unit.
5. The fractional phase-locked loop of claim 4, wherein in each phase detection circuit, the positive electrode of a current source Id1 is connected to a power supply voltage VDD, the negative electrode of the current source Id1 is connected to the source electrode of a PMOS transistor MP1, the drain electrode of the PMOS transistor M1 is connected to the drain electrode of an NMOS transistor MN2, the source electrode of MN2 is grounded, the gate electrode of MP1 and the gate electrode of MN2 are connected and serve as input ends of the phase detection circuits, the drain electrode of MP1 is grounded through a capacitor Cd1, and the drain electrode of MP1 is also connected to the output end of the phase detection circuit;
when the input signal Sig is at high level or low level, the D flip-flop DFF1 triggers and turns on the MP1 in the first phase detection circuit or the second phase detection circuit, so that the current source Id1 in the phase detection circuit charges the capacitor Cd1 to raise the voltage at the output end of the phase detection circuit, and after one clock period is ended, the peak voltage vt=t output by the peak detection circuit sig * (Id 1/Cd 1), where T sig Is the period duration of one clock cycle of the input signal Sig.
6. The fractional phase-locked loop according to claim 3, wherein the phase delay unit comprises a comparator CMP1, a pulse generator and a charging circuit, the charging circuit comprises a current source Id2 and a capacitor Cd2, the negative input end of the comparator CMP1 is connected with the phase detection unit to obtain the peak voltage Vt, the negative input end of the comparator CMP1 is further grounded through a capacitor Ct, and the output end of the charging circuit is connected with the positive input end of the comparator CMP 1;
the input end of the pulse generator is connected with the input end of the output phase mirror module to acquire an input signal Sig, the pulse generator outputs a trigger pulse when the next clock period of the input signal Sig arrives, the charging circuit charges the capacitor Cd2 according to the preset charging speed by using the internal current source Id2 under the action of the trigger pulse, so that the output voltage Vd3 of the charging circuit rises until the output voltage Vd3 of the charging circuit rises to reach the peak voltage, and the output end of the comparator CMP1 outputs a feedback signal Fb in a positive pulse form.
7. The fractional phase-locked loop of claim 6, wherein in the charging circuit, a reset terminal of D flip-flop DFF2 is connected to an output terminal of the pulse generator, a forward output terminal of D flip-flop DFF2 is connected to a gate of NMOS transistor MN3, a source of MN3 is grounded, and a drain of MN3 is connected to a positive input terminal of the comparator CMP 1; the positive electrode of the current source Id2 is connected with the power supply voltage VDD, the negative electrode of the current source Id2 is connected with the positive input end of the comparator CMP1, and the positive input end of the comparator CMP1 is grounded through a capacitor Cd 2;
d trigger DFF2 resets under the effect of trigger pulse and outputs low level through forward output end in order to control MN3 to close, and electric current source Id2 charges electric capacity Cd2 for the voltage of the positive input end of comparator CMP1 rises.
8. The fractional phase-locked loop of claim 7, wherein the output terminal of the comparator CMP1 is further connected to the clock terminal of the D flip-flop DFF2, the input terminal of the D flip-flop DFF2 is connected to the power supply voltage VDD, and when the comparator CMP1 outputs the feedback signal Fb in the form of a positive pulse, the D flip-flop DFF2 outputs a high level through the positive output terminal to control MN3 to turn on, resetting the voltage at the positive input terminal of the comparator CMP1 to 0.
9. The fractional phase-locked loop of claim 1 wherein the delta-sigma modulator in the fractional divider employs a higher order structure of a cascade of multi-stage modulators, each stage modulator of the delta-sigma modulator incorporating quantization noise, the output of each stage of the cascade of delta-sigma modulators canceling the quantization noise of the previous stage, the output of the delta-sigma modulator containing only the quantization noise of the input and last stage modulator, and the quantization noise being filtered by the loop filter.
10. The fractional phase-locked loop of claim 9 wherein the fractional frequency divider comprises a delta-sigma modulator, a count controller, a programmable counter, a swallow counter, and a dual-mode frequency divider, the delta-sigma modulator generating a pseudo-random code from a fractional configuration signal and a divided clock signal Dout to be provided to the count controller, the count controller configuring a maximum count period of the programmable counter and a maximum count period of the swallow counter from the pseudo-random code, an integer configuration signal, and the divided clock signal Dout;
when the dual-mode frequency divider works in an N+1 mode, the dual-mode frequency divider pre-divides an oscillation clock Fvco and then sends the oscillation clock Fvco to the programmable counter and the swallowing counter, the swallowing counter finishes counting first and sends Sout pulse to the dual-mode frequency divider to trigger the dual-mode frequency divider to switch to the N mode and stop working until the programmable counter finishes counting and outputs a frequency division clock signal Dout, the instantaneous frequency division ratio of the dual-mode frequency divider is N x p+s, p is the maximum count value of the programmable counter, and s is the maximum count value of the swallowing counter.
CN202310612194.XA 2023-05-26 2023-05-26 Fractional phase-locked loop with low clock jitter Pending CN116633349A (en)

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