CN109936361B

CN109936361B - Decimal frequency division frequency synthesizer containing PFD/DAC quantization noise elimination technology

Info

Publication number: CN109936361B
Application number: CN201910265119.4A
Authority: CN
Inventors: 王腾佳; 李国儒; 李浩明; 沈玉鹏; 陈旭斌
Original assignee: Hangzhou Chengxin Technology Co ltd
Current assignee: Hangzhou Chengxin Technology Co ltd
Priority date: 2019-04-03
Filing date: 2019-04-03
Publication date: 2020-08-04
Anticipated expiration: 2039-04-03
Also published as: CN109936361A

Abstract

The invention discloses a decimal frequency division synthesizer containing a PFD/DAC quantization noise elimination technology, which inputs a decimal frequency division ratio to an ∑ -delta modulator, the ∑ -delta modulator controls a real-time integer frequency division ratio to be given to a frequency divider, a VCO initially oscillates on a frequency near a target frequency, the frequency division clock is given to the PFD after frequency division by the frequency divider, the PFD performs frequency and phase discrimination on a REF clock and the frequency division clock, a charge and discharge control pulse is output to the DAC, the DAC outputs charge or discharge current according to the control pulse, the current changes the control voltage of the VCO after passing through a loop filter, and thus the frequency and the phase of the output clock are changed, wherein a PFD/DAC module compensates the charge and discharge current according to the received residual error of the modulator to offset extra phase errors introduced by modulation, and finally the VCO can output a clock accurately equal to the target frequency after a loop is stable.

Description

Decimal frequency division frequency synthesizer containing PFD/DAC quantization noise elimination technology

Technical Field

The invention belongs to the field of fractional frequency division synthesizers, and particularly relates to a fractional frequency division synthesizer with a PFD/DAC quantization noise elimination technology.

Background

The decimal frequency division frequency synthesizer can generate a high-resolution high-speed clock and has important value for many communication systems. Conventional fractional-n frequency synthesizers include PFDs (phase frequency detectors), CPs (charge pumps), modulators, loop filters and frequency dividers. Because the frequency divider only realizes integer frequency division, the modulator needs to control the instantaneous frequency division ratio so as to realize dynamic fractional frequency division (for example, a 5-frequency division clock is output and then a 6-frequency division clock is output, so that the average frequency division ratio of 2-time frequency division is 5.5), however, the dynamic jitter of the modulator can be responded by the phase-locked loop, quantization noise with high spurious component is generated, and the phase noise performance of the synthesizer is deteriorated.

Initially, one increases the order of the ∑ - Δ modulator to scatter and shape the quantization noise to higher frequencies, and then suppresses the effect of the quantization noise on the output performance by the loop filter, but in this way, when the loop bandwidth is large, the phase noise at high frequencies is still severely degraded.

Disclosure of Invention

The invention is used for providing a decimal frequency division frequency synthesizer containing a PFD/DAC quantization noise elimination technology, which utilizes a DAC to compensate quantization noise to offset quantization errors in each phase discrimination period, thereby effectively reducing the quantization noise reflected at an output end.

In order to solve the technical problems, the invention adopts the following technical scheme:

a decimal frequency division frequency synthesizer containing a PFD/DAC quantization noise elimination technology comprises a phase frequency detector/digital-to-analog converter PFD/DAC, a loop filter, a voltage controlled oscillator VCO, a dual-mode frequency divider and an ∑ -delta modulator, wherein REF is an input reference frequency clock, the VCO clock is a phase-locked loop output clock, the frequency divider is an integer frequency divider with a variable frequency dividing ratio, the decimal frequency dividing ratio is input to a ∑ -delta modulator, the ∑ -delta modulator controls a real-time integer frequency dividing ratio to be given to the frequency divider, the VCO initially oscillates at a frequency near a target frequency, the frequency divided clock is given to the PFD after being divided by the frequency divider, the PFD performs frequency and phase discrimination on the REF clock and the frequency divided clock, a charge and discharge control pulse is given to the DAC, the DAC outputs a charge and discharge current according to the control pulse, the current changes a control voltage of the VCO after passing through the loop filter, so that the frequency and the phase of the output clock are changed, wherein the PFD/DAC module compensates a residual charge and discharge current according to offset an additional phase error introduced by modulation, and finally outputs a stable phase error which is equal to the target frequency of.

Preferably, the ∑ -delta modulator is a first-order Mash ∑ -delta modulator.

Preferably, when the modulator fractional input is 0.3, the integer output and the residual in 10 consecutive divided clock cycles are, by accumulation: 0-0-0-1-0-0-1-0-0-1; 0.3-0.6-0.9-0.2-0.5-0.8-0.1-0.4-0.7-0, the frequency divider carries out frequency division of 8 when the integer is 0, the frequency divider carries out frequency division of 9 when the integer is 1, the average frequency division ratio on the time domain is 8.3, and the phase error identified by each period phase discriminator is as follows: phi_errorWhen the DAC responds, subtract Φ_errorCorresponding part, a fixed more than T is added when PFD phase discrimination_vcoThe phase error of the period leads the output phase of the frequency divider to be more than one VCO period ahead of the reference clock, then, when discharging, the current value in the width of one VCO period is compensated according to the residual error, and the compensation current is as follows: i is_{Supplement device}1-residual I_cpThe compensation current corresponds to an accumulated charge quantity of Q_{Supplement device}＝I_{Supplement device}·T_vco1-residual I_cp·T_vcoThe amount of charge accumulated corresponding to the phase error caused by the residual error is Q_errResidual error T_vco·I_cpThe net charge accumulation amount of the compensation current and the phase error is 1, the quantization error is eliminated, and the phase-locked loop accurately works at 8.3 times of the reference frequency.

Preferably, the DAC adopts two current steering DACs, wherein one DAC consists of a current source IP1 and a switch controlled by UP1/UP2/UPN1/UPN2, the other DAC consists of a current source IP2 and a switch controlled by DN1/DN2/DNN1/DNN2, respective switch signals are generated by phi1, phi2, Dac _ data, DAC _ datan, UP and vdd, and vss through an AND gate, wherein phi1 and phi2 are discharge switch pulses output by the phase detector, wherein the rising edge of phi2 lags behind phi1 for one VCO period, the DAC outputs a discharge compensation current in the VCO period, UP is a fixed-width charge switch pulse generated by PFD, and is more than one VCO period, and I is I_downAnd I_upThe waveforms are discharge and charge current, respectively.

The invention has the following beneficial effects: the phase noise introduced by the DSM modulator can be reduced to 1/2 by applying the fractional frequency division phase-locked loop with the structureⁿ(1/64 in the embodiment of the present invention), the performance of the fractional division phase-locked loop is greatly improved, and the fractional division phase-locked loop can work under a larger loop bandwidth.

Drawings

FIG. 1 is a schematic diagram of a fractional-N frequency synthesizer with PFD/DAC quantization noise cancellation according to an embodiment of the present invention;

FIG. 2 is a waveform diagram of the response of a fractional-N synthesizer with PFD/DAC quantization noise cancellation according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a DAC of the fractional-N frequency synthesizer with PFD/DAC quantization noise elimination technology according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a per-bit difference circuit of a DAC in a fractional-n frequency synthesizer including a PFD/DAC quantization noise cancellation technique according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, a schematic diagram of a fractional division frequency synthesizer including a PFD/DAC quantization noise cancellation technique according to an embodiment of the present invention is shown, which includes a phase frequency detector/digital-to-analog converter (PFD/DAC), a loop filter, a voltage controlled oscillator VCO, a dual-mode frequency divider, and an ∑ - Δ modulator, where REF is an input reference frequency clock, a VCO clock is a phase locked loop output clock, a frequency divider is an integer divider with a variable division ratio, the fractional division ratio is input to a ∑ - Δ modulator, the ∑ - Δ modulator controls a real-time integer division ratio to the frequency divider, the VCO initially oscillates at a frequency near a target frequency, the VCO initially oscillates at the frequency divided by the frequency divider and outputs a divided clock to the PFD, the PFD performs frequency and phase discrimination on the REF clock and the divided clock, outputs a charge and discharge control pulse to the DAC, the DAC outputs a charge or discharge current according to the control pulse, the current passes through the loop filter and then changes a control voltage of the VCO, thereby changing a frequency and a phase of the output clock, where the PFD/DAC module compensates a residual current according to compensate the received modulator, and compensates a final phase error of the phase of the VCO, thereby stabilizing the target frequency.

Taking 8.3 frequency division as an example to specifically explain the working principle of P LL (Phase locked loop, Phase L locked L oop) under this structure, the modulator selects a first order mask ∑ - Δ modulator (essentially an accumulator), at this time, the decimal input is 0.3, and through accumulation, the integer output and residual error in 10 consecutive frequency division clock cycles are as shown in the following table:

correspondingly, the frequency divider performs frequency division of 8 when the integer is 0, and performs frequency division of 9 when the integer is 1, so that the average frequency division ratio in the time domain is 9.3, and the phase error identified by the phase discriminator in each period is as follows: phi_errorThe phase error caused by the residual error is actually not expected to be responded by the loop (if the loop responds to the phase error, the frequency of the VCO output is changed according to the change of the real-time frequency dividing ratio, so although the average frequency dividing ratio is still 8.3, quantization noise is introduced, and if the phase error is not responded, the VCO output is stabilized at 8.3 times the reference frequency and does not change), so when the DAC responds, phi needs to be subtracted_errorThe corresponding part is realized by adding a fixed T to the PFD phase discrimination_vcoThe phase error of the period leads the output phase of the frequency divider to be more than one VCO period ahead of the reference clock, then, when discharging, the current value in the width of one VCO period is compensated according to the residual error, and the compensation current is as follows: i is_{Supplement device}1-residual I_cpThe compensation current corresponds to an accumulated charge quantity of Q_{Supplement device}＝I_{Supplement device}·T_vco1-residual I_cp·T_vcoThe amount of charge accumulated corresponding to the phase error caused by the residual error is Q_errResidual error T_vco·I_cpThe net charge accumulation amount to compensate for current and phase errors is then T_vco·I_cpThe quantization error is eliminated and the phase-locked loop ideally operates exactly at 8.3 times the reference frequency.

The waveform response is shown in fig. 2, wherein REF is a reference clock, VCO is a phase-locked loop output clock, the frequency is 8.3 times of REF, and DIV is a frequency division output of the frequency divider, which is a frequency division ratio within continuous 10

periodsIs

8, 8, 8, 9, 8, 8, 9, 8, 8, 9; phi1 and phi2 are discharge switching pulses output by the phase detector, where the rising edge of phi2 lags phi1 by one VCO cycle in which the DAC outputs a discharge compensation current, and UP is a fixed-width charge switching pulse (greater than one VCO cycle) generated by the PFD, I_downAnd I_upIs respectively discharge and charge current waveform, [ integral ] I_down+I_upThe charge accumulation amount corresponds to the DAC output point.

The DAC structure provided by the embodiment of the invention can realize the function of compensating the current in the determined moment. One possible structure is shown in FIG. 3, Dac _ data<63:0>For the input after residual decoding, the decoding relationship is Dac _ data<63:0>And (3) multiplying the residual error by 64 and then rounding: p and N respectively represent positive and negative portions of a differential circuit (in the case of a single-ended circuit, a circuit corresponding to P may be used), and 64 bits are used (actually 2 bits)ⁿBit all) of the same current bits are output in parallel, and the structure of each bit is shown in fig. 4.

Wherein Dac _ data/Dac _ datan is the control code received by each bit, OutP/OutN is the output point, and Dmy is the node receiving the current rudder current when no current is needed to be output.

The proposed architecture is based mainly on 2 current steering DACs, one of which consists of current source IP1(IN1) and switches controlled by UP1/UP2/UPN1/UPN2, and the other of which consists of current source IP2(IN2) and switches controlled by DN1/DN2/DNN1/DNN2, the respective switch signals being generated by phi1, phi2, Dac _ data, DAC _ datan, UP and vdd, vss (high and low levels) via the and gates IN the figure, as will be understood by those skilled IN the art, as long as the logic relationship required by the function is met, other logic gates can be used.

For the structure in the P frame, all the current bits receiving data as 0 are turned on DN1 during phi1 high level, the current bits receiving data as 1 are turned on DN2 only during phi2 high level, and UP1 is turned on during UP high level; on the contrary, for the structure in N frame, all the current bits receiving data 0 conduct UP1 between phi1 high level, the current bits receiving data 1 conduct UP2 only during phi2, and DN1 conducts during UP high level. When viewed from the current at the output point, the discharging compensation current is output after phi1 arrives, the maximum discharging current is output when phi2 is turned on, and the charging current is output when UP is turned on. In accordance with the required functions.

The application of the fractional-N phase-locked loop with the structure can reduce the phase noise introduced by the DSM modulator to 1/2 in theoryⁿ(1/64 in the example of the patent), the performance of the fractional division phase locked loop is greatly improved and it can work with larger loop bandwidth.

It is to be understood that the exemplary embodiments described herein are illustrative and not restrictive. Although one or more embodiments of the present invention have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.

Claims

1. A decimal frequency division synthesizer containing a PFD/DAC quantization noise elimination technology is characterized by comprising a phase frequency detector/digital-to-analog converter PFD/DAC, a loop filter, a voltage controlled oscillator VCO, a dual-mode frequency divider and an ∑ -delta modulator, wherein REF is an input reference frequency clock, the VCO clock is a phase-locked loop output clock, the frequency divider is an integer frequency divider with variable frequency dividing ratio, the decimal frequency dividing ratio is input to a ∑ -delta modulator, the ∑ -delta modulator controls a real-time integer frequency dividing ratio to be given to the frequency divider, the VCO initially oscillates on a frequency near a target frequency, the frequency divider divides the frequency and then outputs a frequency dividing clock to the PFD, the PFD performs frequency and phase discrimination on the REF clock and the frequency dividing clock, outputs a charging and discharging control pulse to the DAC, the DAC outputs charging or discharging current according to the control pulse, the current passes through the loop filter and then changes the control voltage of the VCO, so that the frequency and the phase of the output clock are changed, wherein the PFD/DAC module compensates the charging and discharging current according to offset extra phase error of the modulator introduced to offset the extra phase, and finally output a stable target frequency of the VCO;

wherein, the ∑ -delta modulator is a first-order Mash ∑ -delta modulator;

∑ -delta modulator decimal input is 0.3, through accumulation, the integer output and residual in continuous 10 frequency division clock cycles are 0-0-0-1-0-0-1-0-0-1, 0.3-0.6-0.9-0.2-0.5-0.8-0.1-0.4-0.7-0, frequency divider carries out frequency division of 8 when integer is 0, frequency divider carries out frequency division of 9 when integer is 1, average frequency division ratio in time domain is 8.3, phase error identified by each period phase discriminator is phi_errorWhen the DAC responds, subtract Φ_errorCorresponding part, a fixed more than T is added when PFD phase discrimination_vcoThe phase error of the period leads the output phase of the frequency divider to be more than one VCO period ahead of the reference clock, then, when discharging, the current value in the width of one VCO period is compensated according to the residual error, and the compensation current is as follows: i is_{Supplement device}1-residual I_cpThe compensation current corresponds to an accumulated charge quantity of Q_{Supplement device}＝I_{Supplement device}·T_vco1-residual I_cp·T_vcoThe amount of charge accumulated corresponding to the phase error caused by the residual error is Q_errResidual error T_vco·I_cpThe net charge accumulation amount of the compensation current and the phase error is 1, the quantization error is eliminated, and the phase-locked loop accurately works at 8.3 times of the reference frequency.

2. The fractional frequency synthesizer incorporating PFD/DAC quantization noise removal techniques of claim 1, wherein said DAC employs two current steering DACs, one of which is composed of a current source IP1 and switches controlled by UP1/UP2/UPN1/UPN2, the other of which is composed of a current source IP2 and switches controlled by DN1/DN2/DNN1/DNN2, the respective switching signals being generated by phi1, phi2, Dac _ data, DAC _ datan, UP and vdd, vss via and gates, wherein phi1 and phi2 are discharge switching pulses output by the phase detector, wherein the rising edge of phi2 lags behind phi1 by one VCO cycle, the DAC outputting a discharge compensation current during this VCO cycle, and the fixed width charge switching pulses generated by the PFD are greater than one VCO cycle, I_downAnd I_upAre respectively dischargedDac _ data and Dac _ datan represent control words, and vdd and vss represent high and low levels.