CN116504646B - 多芯片排列封装结构及方法 - Google Patents
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Abstract
本发明涉及一种多芯片排列封装结构及方法,该方法包括如下步骤:提供一铜板;于所提供的铜板上植上多个铜柱;提供一基板,并将铜柱连接在基板上;对基板和铜板之间的铜柱进行塑封形成包覆铜柱的塑封层;利用研磨工艺将铜板去除以露出铜柱;提供多个芯片,将所提供的芯片贴装在铜柱上;于芯片之上点散热胶形成散热胶层;于芯片的侧部涂覆绝缘胶形成位于对应的塑封层之上的并与芯片相贴的绝缘胶层;于基板的背面植上锡球,从而完成封装。本发明的封装方法将多个芯片排列在铜柱上,能够有效缩小产品的体积,具有生产前置时间短、制造成本低、低功耗、高数据传输速率和占用空间小等的优势。
Description
技术领域
本发明涉及半导体封装技术领域,特指一种多芯片排列封装结构及方法。
背景技术
倒装芯片封装结构,只适用于凸点间距(Bump pitch)大于60um的情况,对于凸点间距小于60um的情况,现有的封装方式只能采用TCB(Thermal Compression Bonding,热压粘合)封装方式,但TCB封装方式存在良率差、成本高的问题。因此,亟需提供一种新的封装方式以适应于对于凸点间距小于60um的情况。
发明内容
本发明的目的在于克服现有技术的缺陷,提供一种多芯片排列封装结构及方法,解决现有的倒装芯片封装结构不能适用于小于60um的凸点间距的问题以及TCB封装存在的良率差和成本高的问题。
实现上述目的的技术方案是:
本发明提供了一种多芯片排列封装方法,包括如下步骤:
提供一铜板;
于所提供的铜板上植上多个铜柱;
提供一基板,并将所述铜柱连接在所述基板上;
对所述基板和所述铜板之间的铜柱进行塑封形成包覆所述铜柱的塑封层;
利用研磨工艺将所述铜板去除以露出所述铜柱;
提供多个芯片,将所提供的芯片贴装在所述铜柱上;
于所述芯片之上点散热胶形成散热胶层;
于所述芯片的侧部涂覆绝缘胶形成位于对应的塑封层之上的并与所述芯片相贴的绝缘胶层;
于所述基板的背面植上锡球,从而完成封装。
本发明的封装方法将多个芯片排列在铜柱上,能够有效缩小产品的体积,可实现将DRAM、闪存和SRAM等不同规格和不同尺寸的芯片封装在单一模块中,采用混合技术将2至8个芯片堆栈在低成本的基本上,具有生产前置时间短、制造成本低、低功耗、高数据传输速率和占用空间小等的优势。
本发明多芯片排列封装方法的进一步改进在于,提供散热片,将所述散热片覆设在所述绝缘胶层和所述散热胶层之上,并与所述绝缘胶层和所述散热胶层粘贴固定。
本发明多芯片排列封装方法的进一步改进在于,所提供的散热片包括覆设在所述绝缘胶层和所述散热胶层之上的顶板以及与所述顶板连接的四个侧板;
设置所述散热片时,将所述散热片罩扣在所述绝缘胶层和所述散热胶层之上,让所述散热片的四个侧板贴设在所述绝缘胶层以及所述塑封层对应的侧部上。
本发明多芯片排列封装方法的进一步改进在于,在所述铜板上植铜柱时,让相邻的两个铜柱之间的间距小于60um。
本发明多芯片排列封装方法的进一步改进在于,在贴装好芯片之后,对所述芯片进行引线键合。
本发明还提供了一种多芯片排列封装结构,包括:
基板;
连接在所述基板上的多个铜柱,所述铜柱的顶部连接有可研磨去除的铜板;
塑封形成在所述基板和所述铜板之间并包裹所述铜柱的塑封层;
贴装在经研磨去除铜板而露出的铜柱上的多个芯片;
设于所述芯片之上的散热胶层;
设于所述芯片侧部并位于对应的塑封层之上的绝缘胶层;
设于所述基板背面的锡球。
本发明多芯片排列封装结构的进一步改进在于,还包括覆设在所述绝缘胶层之上的散热片。
本发明多芯片排列封装结构的进一步改进在于,所述散热片包括覆设在所述绝缘胶层和所述散热胶层之上的顶板以及与所述顶板垂直连接的四个侧板,所述的四个侧板贴设在所述绝缘胶层以及所述塑封层对应的侧部上。
本发明多芯片排列封装结构的进一步改进在于,相邻的两个铜柱之间的间距小于60um。
本发明多芯片排列封装结构的进一步改进在于,还包括连接在所述芯片上的焊接线。
附图说明
图1为本发明多芯片排列封装结构及方法中的铜板的结构示意图。
图2为本发明多芯片排列封装方法中在铜板上植上铜柱的结构示意图。
图3为本发明多芯片排列封装方法中将铜柱与基板连接的结构示意图。
图4为本发明多芯片排列封装方法中对铜柱进行塑封的结构示意图。
图5为本发明多芯片排列封装方法中研磨去除铜板后的结构示意图。
图6为本发明多芯片排列封装方法中贴装芯片的结构示意图。
图7为本发明多芯片排列封装方法中设置散热片的结构示意图。
图8为本发明多芯片排列封装方法中在基板上植上锡球的结构示意图。
附图标记说明:
21-铜板;22-铜柱;23-基板;锡球-231;24-塑封层;25-芯片;26-散热胶层;27-散热片;28-绝缘胶层。
具体实施方式
下面结合附图和具体实施例对本发明作进一步说明。
参阅图8,本发明提供了一种多芯片排列封装结构及方法,用于解决现有的TCB封装方式存在良率差以及成本高的问题。本发明先利用在铜板上植上间距小于60um的铜柱,利用芯片排列的方式以有效缩小电子产品的体积,将多个芯片封装在一起,具有生产前置时间短、制造成本低、低功耗、高数据传输速率和占用空间小等的优势。下面结合附图对本发明多芯片排列封装结构及方法进行说明。
参阅图8,显示了本发明的多芯片排列封装结构的剖视图。下面结合图8,对本发明多芯片排列封装结构进行说明。
如图8所示,本发明的多芯片排列封装结构包括基板23、铜柱22、铜板21、塑封层24、芯片25、散热胶层26、绝缘胶层28以及锡球231;铜柱22有多个,连接在基板23和铜板21之间,较佳地,结合图1和图2所示,先将铜柱22植在铜板21上,结合图3所示,再将铜柱22的另一端与基板23连接,该铜板21可在后期研磨去除。结合图4所示,塑封层24形成在基板23和铜板21之间并包裹铜柱22,该塑封层24较佳采用绝缘胶形成。芯片25有多个,芯片25贴装在研磨去除铜板21后露出的铜柱22上,结合图5和图6所示,先将铜板21研磨去处露出铜柱,然后在将多个芯片25排列的贴装在铜柱22上。结合图7所示,散热胶层26设于芯片25之上,绝缘胶层28设于芯片25的侧部并位于对应的塑封层24之上;锡球231设于基板23的背面。
进一步地,如图7和图8所示,还包括覆设在绝缘胶层28之上的散热片27。
再进一步地,散热片27包括覆设在绝缘胶层28和散热胶层26之上的顶板以及与顶板垂直连接的四个侧板,该四个侧板贴设在绝缘胶层28以及塑封层24对应的侧部上。
又进一步地,相邻的两个铜柱22之间的间距小于60um。
又进一步地,还包括连接在芯片25上的焊接线。
本发明的芯片排列封装结构侧重在一个封装中排列了多个芯片,主要指多个存储器芯片的堆栈,在这个封装中含有存储器子***,可将DRAM、闪存和SRAM等不同规格和不同尺寸的芯片封装在单一模块中,并采用混合技术,将2至8个芯片堆栈在低成本的基板上,具备生产前置时间短、制造成本低、低功耗、高数据传输速率和占用空间小等优势。
本发明还提供了一种多芯片排列封装方法,下面对该封装方法进行说明。
如图1至图8所示,本发明的封装方法包括如下步骤:
提供一铜板21;
于所提供的铜板21上植上多个铜柱22;
提供一基板23,并将铜柱22连接在基板23上;
对基板23和铜板21之间的铜柱22进行塑封形成包覆铜柱22的塑封层24;
利用研磨工艺将铜板21去除以露出铜柱22;
提供多个芯片25,将所提供的芯片25贴装在铜柱22上;
于芯片25之上点散热胶形成散热胶层26;
于芯片25的侧部涂覆绝缘胶形成位于对应的塑封层24之上的并与芯片25相贴的绝缘胶层28;
于基板23的背面植上锡球231,从而完成封装。
在贴装芯片25时,将芯片25置于对应的铜柱22及塑封层24之上,并将芯片25上的引脚与铜柱22对应的电连接。
进一步地,还包括:提供散热片27,将散热片27覆设在绝缘胶层28和散热胶层26之上,并与绝缘胶层28和散热胶层26粘贴固定。
再进一步地,所提供的散热片27包括覆设在绝缘胶层28和散热胶层26之上的顶板以及与顶板连接的四个侧板;
设置散热片27时,将散热片27罩扣在绝缘胶层28和散热胶层26之上,让散热片27的四个侧板贴设在绝缘胶层以及塑封层对应的侧部上。
又进一步地,在铜板21上植铜柱22时,让相邻的两个铜柱22之间的间距小于60um。
又进一步地,在贴装好芯片25之后,对芯片25进行引线键合。
以上结合附图实施例对本发明进行了详细说明,本领域中普通技术人员可根据上述说明对本发明做出种种变化例。因而,实施例中的某些细节不应构成对本发明的限定,本发明将以所附权利要求书界定的范围作为本发明的保护范围。
Claims (2)
1.一种多芯片排列封装方法,其特征在于,包括如下步骤:
提供一铜板;
于所提供的铜板上植上多个铜柱;在所述铜板上植铜柱时,让相邻的两个铜柱之间的间距小于60um;铜柱的设置位置与芯片的设置位置相对应,且铜柱阵列在对应的芯片的设置位置处;
提供一基板,并将所述铜柱连接在所述基板上;
对所述基板和所述铜板之间的铜柱进行塑封形成包覆所述铜柱的塑封层;所述塑封层采用绝缘胶形成;
利用研磨工艺将所述铜板去除以露出所述铜柱;
提供多个芯片,将所提供的芯片贴装在所述铜柱上;所提供的多个芯片包括DRAM、闪存以及SRAM芯片;
于所述芯片之上点散热胶形成散热胶层;
于所述芯片的侧部涂覆绝缘胶形成位于对应的塑封层之上的并与所述芯片相贴的绝缘胶层;
于所述基板的背面植上锡球,从而完成封装,实现了将DRAM、闪存以及SRAM芯片封装在单一模块中;
还包括:
提供散热片,将所述散热片覆设在所述绝缘胶层和所述散热胶层之上,并与所述绝缘胶层和所述散热胶层粘贴固定;
所提供的散热片包括覆设在所述绝缘胶层和所述散热胶层之上的顶板以及与所述顶板连接的四个侧板;
设置所述散热片时,将所述散热片罩扣在所述绝缘胶层和所述散热胶层之上,让所述散热片的四个侧板贴设在所述绝缘胶层以及所述塑封层对应的侧部上;在贴装好芯片之后,对所述芯片进行引线键合。
2.一种多芯片排列封装结构,其特征在于,包括:
基板;
连接在所述基板上的多个铜柱,所述铜柱的顶部连接有可研磨去除的铜板;相邻的两个铜柱之间的间距小于60um,铜柱的设置位置与芯片的设置位置相对应,且铜柱阵列在对应的芯片的设置位置处;
塑封形成在所述基板和所述铜板之间并包裹所述铜柱的塑封层;所述塑封层采用绝缘胶形成;
贴装在经研磨去除铜板而露出的铜柱上的多个芯片,多个芯片包括DARM、闪存以及SRAM芯片;
设于所述芯片之上的散热胶层;
设于所述芯片侧部并位于对应的塑封层之上的绝缘胶层;
设于所述基板背面的锡球,从而实现了将DRAM、闪存以及SRAM芯片封装在单一模块中;
还包括覆设在所述绝缘胶层之上的散热片;
所述散热片包括覆设在所述绝缘胶层和所述散热胶层之上的顶板以及与所述顶板垂直连接的四个侧板,所述的四个侧板贴设在所述绝缘胶层以及所述塑封层对应的侧部上;还包括连接在所述芯片上的焊接线。
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