CN116470890A - Hysteresis comparison circuit and electronic equipment - Google Patents
Hysteresis comparison circuit and electronic equipment Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
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Abstract
The utility model relates to a hysteresis comparison circuit and electronic equipment, through the first electric current and the second electric current that generates the constant proportion of variation etc. by bias power supply production module, and respectively export these two electric currents as tail current to rail input module and hysteresis window production module's differential pair circuit, make hysteresis window voltage not change along with the change of input common mode, power supply voltage, temperature, and adopt hysteresis window control module control to adjust hysteresis current size that hysteresis window produced the module output in order to reach the purpose of adjusting hysteresis window voltage size, in addition, still make this hysteresis comparison circuit work in the input voltage scope from power supply voltage to ground through adding NMOS source follower circuit in rail to rail input module. The hysteresis comparison circuit in the application has high precision, the hysteresis window voltage is insensitive to the input common mode, the power supply voltage and the temperature, and the working speed is high.
Description
Technical Field
The present disclosure relates to the field of electronic circuits, and in particular, to a hysteresis comparator circuit and an electronic device.
Background
The comparator is one of the very common modules in the digital-analog hybrid integrated circuit, and can detect the relative magnitude of two analog signals and output corresponding digital signals in general, so that the comparator can be regarded as an analog-digital converter with one-bit precision. In practical application occasions, because the input signal has noise interference, the output response curve of the comparator easily oscillates and jumps along with the noise, and the comparison result is wrong. Therefore, the comparator with hysteresis characteristics is designed, and a hysteresis window can be formed near the reference signal of the comparator, so that the comparator can not generate misoperation as long as the oscillation amplitude of the noise signal does not exceed the size of the hysteresis window, and the anti-interference capability of the comparator is greatly improved.
In the prior art, common hysteresis comparator implementations include those that are formed using an external positive feedback structure and those that are formed using an internal positive feedback structure. The hysteresis comparator formed by adopting an external positive feedback structure forms a positive feedback loop through an operational amplifier external resistor, so that hysteresis characteristics are generated. However, the hysteresis window of the comparator is proportional to the power supply voltage, an accurate hysteresis window cannot be formed, and the resistor for feedback can form a load to be driven, so that the application range of the scheme is limited greatly because the deviation value of the resistor device is relatively large and difficult to control due to the limitation of a process. And a hysteresis comparator formed by an internal positive feedback structure is adopted, and a hysteresis window is realized by the internal positive feedback. The circuit has a simple structure, but the width of the hysteresis window is mainly determined by the parameters of the transistor, once the circuit is determined, the circuit cannot be flexibly adjusted, the circuit is easily influenced by power supply voltage and temperature, and higher precision is difficult to achieve, and the input end of the circuit is in a single-tube form and cannot be suitable for a wider input common-mode voltage range.
Disclosure of Invention
In view of the above, it is desirable to provide a hysteresis comparator circuit and an electronic device that can generate a precise hysteresis window voltage and can maintain the window voltage level unchanged with the input common mode level, the power supply voltage, and the temperature.
A hysteresis comparison circuit, comprising: the system comprises a rail-to-rail input module, a bias power supply generating module, a hysteresis window control module, a hysteresis window generating module, a buffer, a gain amplifying stage module and a load module,
the input end of the rail-to-rail input module is used for receiving positive and negative input signals, the output end of the rail-to-rail input module is connected to the load module and the hysteresis window generation module, the input end of the hysteresis window control module is used for receiving a control code and feedback signals output by the hysteresis comparison circuit, the output end of the hysteresis window control module is connected to the hysteresis window generation module, the output end of the hysteresis window generation module is used for being connected to the load module, the output end of the load module is used for being connected to the gain amplification stage module, the gain amplification stage module is connected to the buffer, the output end of the buffer outputs the feedback signals of the hysteresis comparison circuit and single-ended output signals, the input end of the bias power generation module is used for receiving reference currents, and the output ends of the bias power generation module are respectively connected to the rail-to-rail input module, the hysteresis window control module and the hysteresis window generation module;
The rail-to-rail input module comprises a PMOS differential pair circuit and an NMOS source follower circuit, and is used for generating corresponding differential current signals according to the positive and negative input signals, namely differential voltage signals, and outputting the differential current signals to the load module, wherein the differential voltage signals are reduced by the NMOS source follower circuit and then are input into the differential pair circuit;
the hysteresis window control module comprises a voltage dividing resistor string circuit and a logic gate circuit and is used for generating a control signal according to the logic relation between the control code and the feedback signal;
the hysteresis window generation module comprises two groups of hysteresis differential pair circuits, and is used for generating two hysteresis currents according to the control signals and acting on the differential current signals to adjust the hysteresis currents so that the load module generates hysteresis window voltages corresponding to the control signals;
the bias power supply generating module comprises a first current summing circuit and a second current summing circuit, wherein the first current summing circuit generates a first current and a first voltage, the first current and the first voltage are output to the rail-to-rail input module and are respectively used as tail currents of the differential pair circuit and bias voltages of the NMOS source follower circuit, and the second current summing circuit dynamically generates a second current consistent with the first current variable quantity according to the first voltage and inputs the second current to the hysteresis window generating module to be used as tail currents of the hysteresis differential pair circuit.
In one embodiment, the device further comprises a gain amplification stage module, wherein the gain amplification stage module is connected between the output end of the load module and the input end of the buffer module.
In one embodiment, in the rail-to-rail input module, the differential pair circuit includes a first PMOS differential pair circuit and a second PMOS differential pair circuit, the differential voltage signal is input to the first PMOS input differential pair circuit and the NMOS source follower circuit at the same time, and the differential voltage signal is reduced by the NMOS source follower circuit and then input to the second PMOS input differential pair circuit;
and the first current generated by the first current summation circuit is used as the tail current of the first PMOS differential pair circuit.
In one embodiment, the first PMOS differential pair circuit includes a first PMOS transistor and a second PMOS transistor, gates of the first PMOS transistor and the second PMOS transistor are respectively used as a positive input terminal and a negative input terminal to correspondingly receive a positive input signal and a negative input signal, and sources of the first PMOS transistor and the second PMOS transistor are connected with the first current;
the NMOS source follower circuit comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a seventh PMOS tube and an eighth PMOS tube, wherein the grid electrodes of the first NMOS tube and the second NMOS tube are respectively used as negative input ends and positive input ends to correspondingly receive the positive input signals and the negative input signals, the grid electrodes of the first NMOS tube and the second NMOS tube are respectively input into the second PMOS differential pair circuit after level shifting, the source electrodes of the first NMOS tube and the second NMOS tube are respectively and correspondingly connected to the drain electrodes of the third NMOS tube and the fourth NMOS tube, the grid electrodes of the third NMOS tube and the fourth NMOS tube are connected with the first voltage, the source electrodes of the third NMOS tube and the fourth NMOS tube are grounded, the drain electrodes of the first NMOS tube and the second NMOS tube are respectively connected with the drain electrodes of the seventh PMOS tube and the eighth PMOS tube,
The second PMOS differential pair circuit comprises a third PMOS tube and a fourth PMOS tube, the grid electrodes of the third PMOS tube and the fourth PMOS tube are respectively connected with the source electrodes of the first NMOS tube and the second NMOS tube to receive positive input signals and negative input signals after level shifting, and the drain electrodes of the third PMOS tube and the fourth PMOS tube are respectively connected with the drain electrodes of the first PMOS tube and the second PMOS tube to input differential current signals to the load module;
the rail-to-rail input module further comprises a fifth PMOS tube and a sixth PMOS tube, the grid electrodes of the fifth PMOS tube and the sixth PMOS tube are respectively connected with the grid electrodes of the seventh PMOS tube and the eighth PMOS tube, the source electrodes of the seventh PMOS tube and the eighth PMOS tube are connected with a power supply voltage, the grid electrodes and the drain electrodes are connected to form a current mirror, currents are mirrored to the fifth PMOS tube and the sixth PMOS tube, and the drain electrodes of the fifth PMOS tube and the sixth PMOS tube are connected to the source electrodes of the third NMOS tube and the fourth NMOS tube to provide tail currents for the second PMOS differential pair circuit.
In one embodiment, in the hysteresis window control module:
the voltage dividing resistor string circuit is connected with reference voltage, and three voltage dividing voltage signals are obtained after the reference voltage is divided;
the logic gate circuit comprises a NAND gate, an inverter and 4 transmission gates;
the NAND gate is provided with two input ends respectively used for receiving the control code and the feedback signal and outputting a first logic signal, and the input end of the inverter is used for receiving the first logic signal and outputting a second logic signal;
And using each divided voltage signal as an input signal of a transmission gate, controlling the on and off of each transmission gate by using the first logic signal and the second logic signal to output corresponding first control signals, wherein the number of the first control signals is two, one divided voltage signal is used as a second control signal, and the first control signal and the second control signal are used as the control signals to be output to the hysteresis window generation module.
In one embodiment, the control code is one or more bits, and when the control code is more than one bit, the number of the logic gates is increased to twice the number of the control code bits, and the number of the first control signals obtained at this time is also increased to twice the number of the control code bits.
In one embodiment, the hysteresis window generating module includes a first hysteresis differential pair circuit and a second hysteresis differential pair circuit, and is configured to generate a first hysteresis current and a second hysteresis current;
each hysteresis differential circuit comprises two groups of PMOS (P-channel metal oxide semiconductor) tubes, each group of PMOS tubes comprises one PMOS tube for receiving the second control signal and a plurality of PMOS tubes in parallel connection for receiving the first control signal, the number of the PMOS tubes for receiving the first control signal is consistent with the number of control code bits, wherein two groups of PMOS tube grids belonging to the same hysteresis differential circuit are used for receiving corresponding control signals, the drains of the two groups of PMOS tubes are respectively connected and then used for outputting hysteresis current, and the sources of the two groups of PMOS tubes are connected and then used for receiving tail current;
The second hysteresis differential pair circuit further comprises two PMOS tubes forming a current mirror circuit for mirroring the second current into the second hysteresis differential pair circuit as tail current;
the first hysteresis differential pair circuit further comprises two PMOS tubes, wherein the drain electrodes of the two PMOS tubes are connected, the grid electrodes of the PMOS tubes are respectively connected to the seventh PMOS tube grid electrode and the eighth PMOS tube grid electrode of the rail-to-rail input module, and the PMOS tubes are used for providing tail currents with the same size as the tail currents in the second PMOS differential pair circuit for the first hysteresis differential pair circuit.
In one embodiment, in the bias power supply generating module:
the first summing circuit comprises 5 PMOS tubes, wherein the sources of the 5 PMOS tubes are connected with the power supply voltage, the gates of the 5 PMOS tubes are respectively a ninth PMOS tube, a tenth PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube and a fourteenth PMOS tube, the sources of the eleventh PMOS tube are connected with the drain electrode of the tenth PMOS tube, the gates of the eleventh PMOS tube are connected with the drain electrode of the twelfth PMOS tube and then grounded through a resistor, and the drain electrode of the tenth PMOS tube outputs the first current and the eleventh PMOS tube outputs the first voltage;
the second summing circuit comprises a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a fifteenth PMOS tube and a sixteenth PMOS tube, wherein the grid electrodes of the fifth NMOS tube, the seventh NMOS tube and the ninth NMOS tube are respectively connected with the drain electrodes of the sixth NMOS tube, the eighth NMOS tube and the tenth NMOS tube, the grid electrodes of the sixth NMOS tube, the eighth NMOS tube and the tenth NMOS tube are mutually connected, the source electrodes of the eighth NMOS tube are grounded, the drain electrode of the fifth NMOS tube is connected with the reference current, the drain electrode of the seventh NMOS tube is connected with the drain electrode of the ninth PMOS tube, the drain electrode of the ninth NMOS tube outputs the second current and is connected with the drain electrode of the fifteenth PMOS tube, the fifteenth PMOS tube and the sixteenth PMOS tube form a current mirror, the drain electrode of the sixteenth PMOS tube and the drain electrode of the twelfth NMOS tube are respectively connected with the drain electrode of the NMOS tube, the drain electrode of the twelfth PMOS tube and the eleventh tube form a current mirror.
In one embodiment, in the rail-to-rail input module and the hysteresis window generation module, parameters of the PMOS tubes in the first PMOS differential pair circuit and the second PMOS differential pair circuit are identical or in proportion; and the parameters of the PMOS tubes in the second PMOS differential pair circuit and the first hysteresis differential circuit are consistent or the proportion is the same.
An electronic device comprising the hysteresis comparison circuit.
According to the hysteresis comparison circuit and the electronic equipment, the bias power supply generating module generates the first current and the second current with the same ratio of variable quantity and the like, and the two currents are respectively output to the differential pair circuit of the rail-to-rail input module and the hysteresis window generating module as tail currents, so that the hysteresis window voltage does not change along with the change of the input common mode, the power supply voltage and the temperature, the hysteresis window control module is adopted to control and adjust the magnitude of the hysteresis current output by the hysteresis window generating module so as to achieve the purpose of adjusting the magnitude of the hysteresis window voltage, and in addition, the NMOS source follower circuit is added into the rail-to-rail input module, so that the hysteresis comparison circuit can work in the input voltage range from the power supply voltage to the ground. The hysteresis comparison circuit in the application has high precision, the hysteresis window voltage is insensitive to the input common mode, the power supply voltage and the temperature, and the working speed is high.
Drawings
FIG. 1 is a functional block diagram of a hysteresis comparison circuit in one embodiment;
FIG. 2 is a schematic diagram of a hysteresis comparator circuit in one embodiment;
FIG. 3 is a schematic diagram of the hysteresis window control module circuit of FIG. 2;
FIG. 4 is a schematic diagram of a hysteresis comparator circuit according to another embodiment;
FIG. 5 is a schematic diagram of the bias power generation module of FIG. 4;
FIG. 6 is a schematic diagram of the hysteresis window control module circuit of FIG. 4;
FIG. 7 is a diagram showing simulation results of the hysteresis window size in the hysteresis comparison circuit in a simulation experiment;
FIG. 8 is a schematic diagram of a simulation of the hysteresis window size and control code in the hysteresis comparison circuit herein in a simulation experiment;
FIG. 9 is a schematic diagram of a simulation of the hysteresis window size in the hysteresis comparison circuit herein as a function of input common mode in a simulation experiment;
FIG. 10 is a schematic diagram of a simulation of the hysteresis window size of the hysteresis comparison circuit according to the present invention as a function of temperature in a simulation experiment;
FIG. 11 is a schematic diagram of a simulation experiment in which the size of the hysteresis window in the hysteresis comparison circuit varies with the power supply voltage.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that the terms "first," "second," and the like, as used herein, may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first resistance may be referred to as a second resistance, and similarly, a second resistance may be referred to as a first resistance, without departing from the scope of the present application. Both the first resistor and the second resistor are resistors, but they are not the same resistor.
It is to be understood that in the following embodiments, "connected" is understood to mean "electrically connected", "communicatively connected", etc., if the connected circuits, modules, units, etc., have electrical or data transfer between them.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.
As shown in fig. 1, the hysteresis comparison circuit in one embodiment includes: the power supply circuit comprises a rail-to-rail input module 100, a bias power supply generating module 200, a hysteresis window control module 300, a hysteresis window generating module 400, a load module 500, a buffer 600 and a gain amplifying stage module 700.
The input end of the rail-to-rail input module 100 is used for receiving a negative input signal VIN and a positive input signal VIP, the output end of the rail-to-rail input module 100 is connected to the load module 500 and the hysteresis window generation module 400, the input end of the hysteresis window control module 300 is used for receiving a reference voltage VA, the control code a < N:0> and a feedback signal Z output by the hysteresis comparison circuit, the output end of the hysteresis window control module 300 is connected to the hysteresis window generation module 400, the output end of the hysteresis window generation module 400 is used for being connected to the load module 500, the output end of the load module 500 is used for being connected to the gain amplification stage module 700, the output end of the gain amplification stage module 700 is used for being connected to the buffer 600, the feedback signal Z of the hysteresis comparison circuit and the single-ended signal VOUT are output by the output end of the buffer 600, the input end of the bias power generation module 200 is used for receiving a reference current IREF, and the plurality of output ends of the bias power generation module 200 are respectively connected to the rail-to the rail input module 100, the hysteresis window generation module 400 and the gain amplification stage module 700.
The rail-to-rail input module 100 adopts a rail-to-rail differential input stage structure including a PMOS differential pair circuit and an NMOS source follower circuit, and is configured to generate corresponding differential current signals (Ip and In) according to a negative input signal VIN and a positive input signal VIP, that is, differential voltage signals, and output the differential current signals (Ip and In) to the load module 500, where the NMOS source follower circuit is used as an auxiliary circuit, and is configured to level shift the differential voltage signals, reduce a certain value, and then input the differential voltage signals to the PMOS differential pair circuit, so as to ensure that a common mode level range of the input signal at the whole input end is from a power supply voltage to a ground.
The hysteresis window control module 300 comprises a voltage dividing resistor string circuit and a logic gate circuit, wherein the voltage dividing resistor string circuit is used for dividing the voltage dividing resistor string into a plurality of groups of reference voltages with different sizes, the reference voltages are respectively connected to the input ends of a plurality of transmission gates, the feedback signal Z of the comparator circuit and the control code A < N:0> are used as the input of a logic device, a logic signal is generated for controlling the on and off of the transmission gates, and the output of the transmission gates is used as a voltage control signal VO < N:0> for controlling the hysteresis window generation module 400.
The hysteresis window generating module 400 includes two sets of hysteresis differential pair circuits, and correspondingly generates two hysteresis currents Ihysp and Ihysn, and the two hysteresis currents are controlled by the hysteresis window control module, so that the magnitudes of the hysteresis currents (Ihysp and Ihysn) can be automatically adjusted according to specific design requirements of the circuits, and the adjustability of hysteresis window voltages (Vp and Vn) is achieved.
The bias power supply generating module 200 mainly comprises a cascode circuit, and includes a first current summing circuit and a second current summing circuit, wherein the first current summing circuit generates a first current and a first voltage, the first current and the first voltage are output to the rail-to-rail input module 100 and are respectively used as tail current ISSP of the differential pair circuit and bias voltage VBN of the NMOS source follower circuit, and the second current summing circuit dynamically generates a second current consistent with the first current variation according to the first voltage and inputs the second current to the hysteresis window generating module to serve as tail current Itp of the hysteresis differential pair circuit. In this way, two currents with consistent variation can be generated by the module and used as tail currents in the differential pair circuit and the hysteresis differential pair circuit in the rail-to-rail input module 100 and the hysteresis window generating module 400 respectively, so that the generated hysteresis window voltages (Vp and Vn) are more stable. In addition, the module may also generate the tail current ISS required for the gain amplifier stage module to operate in an example.
The load module 500 is used as a load for converting differential current signals (Ip and In) generated by the rail-to-rail input module 100 into voltages, and the module can provide a larger gain for the hysteresis comparison circuit by selecting a proper structure.
In one embodiment, the hysteresis comparison circuit further includes a gain amplifier module 700, which provides greater gain and greater accuracy for a comparison circuit. In order to improve the precision of the hysteresis comparison circuit, the comparison circuit is composed of multiple stages of operational amplifiers, the gain amplification stage module is composed of the operational amplifiers except the first stage, and the structure and the gain of the module can be adjusted according to design requirements in practical application.
In the following, the working principle of the hysteresis comparison circuit presented herein is first analyzed by a simple embodiment. As shown in fig. 2, the hysteresis comparator circuit has a main body, whose constituent modules are substantially identical to those of the functional block diagram of fig. 1, and the bias power generation module 200 is omitted for convenience of analysis, and a current source is substituted in the circuit, and is configured as a rail-to-rail input module 100a, a hysteresis window control module 300a, a hysteresis window generation module 400a, a load module 500a and a gain amplifier stage module 700a, wherein the schematic diagram of the hysteresis window control module 300a is shown in fig. 3.
In the rail-to-rail input module 100a, the differential pair circuit includes a first PMOS differential pair circuit, a second PMOS differential pair circuit, and the NMOS source follower circuit includes two sets of source followers. The first PMOS differential pair circuit is composed of a first PMOS transistor P1 and a second PMOS transistor P2, the second PMOS differential pair circuit is composed of a third PMOS transistor P3 and a fourth PMOS transistor P4, one group of source followers is composed of a first NMOS transistor and a second current source I2, the other group of source followers is composed of a second NMOS transistor and a third current source I3, differential voltage signals VIP and VIN are input into the first PMOS input differential pair circuit and the NMOS source follower circuit at the same time, and the differential voltage signals are input into the second PMOS input differential pair circuit after being reduced through the NMOS source follower circuit.
Specifically, the differential voltage signals VIP and VIN are directly input to the gates of the first PMOS differential pair circuits P1 and P2, and are input to the gates of the second PMOS differential pair circuits P3 and P4 after level shifting of N1 and N2 in the source follower, wherein the current magnitudes of the two sets of source followers are I2 and I3, the tail currents of the first PMOS differential pair circuits P1 and P2 are I1, and the tail currents of the second PMOS differential pair circuits P3 and P4 are I0. Wherein i0=i3+i2, i0+i1=iref, iref is a reference current, and is a fixed value.
When the input common mode level is lower, N1 and N2 in the source follower are cut off, I2, I3 and I0 are 0, so that the first PMOS differential pair circuits P1 and P1 are cut off, and the second PMOS differential pair circuits P3 and P4 are conducted, and the current I1 is Iref; when the input common mode level is an intermediate value, the two differential pairs work normally and the tail current sum is Iref; when the input common mode level is higher, the second PMOS differential pair circuits P3 and P4 are turned off, the source follower is turned on, the input common mode level is reduced by a certain value and then is input into the differential pair P1 and P2, the P1 and P2 work normally, and the tail current I0 is Iref. This ensures that the common mode range of the input signal across the input is the supply voltage to ground.
The hysteresis window control module 300a mainly comprises a voltage dividing resistor string circuit and a logic gate circuit, wherein the voltage dividing resistor string circuit is connected with a reference voltage VA, and VA in the voltage dividing resistor string circuit is a reference voltage which does not change along with voltage and temperature and can be generated by a band gap reference. In this embodiment, VA is divided to generate three divided voltage signals V0, V1 and V2. The logic gate circuit includes a nand gate, an inverter, and 4 transfer gates. The two input ends of the NAND gate are used as the input ends of the logic gate circuit and are respectively used for receiving the control code and the feedback signal Z. Here, the control code is a hysteresis window enable signal hys_en, and control signals VO1 and VO2 for the hysteresis window generation module are output after passing through the logic gate circuit.
When the logic gate circuit is in a working state, when the input HYS_EN is logic 0, the hysteresis window generating module is not effective, and the hysteresis comparing circuit has no hysteresis effect; when the input HYS_EN is logic 1, the hysteresis window generation module is effective, and the output curve of the hysteresis comparator circuit generates a corresponding hysteresis window. When Z and hys_en pass through the nand gate NA1, a first logic signal S0N is output, the first logic signal S0N passes through the inverter INV1 to obtain a second logic signal S0, and the first logic signal S0N and the second logic signal S0 are used for controlling the on and off of the transmission gates TG1 to TG4, and output signals VO1 and VO2 are obtained. The output signals VO1 and VO2 are taken as first control signals, one of the divided voltage signals V1 is taken as a second control signal, and the first control signal and the second control signal are taken as control signals (V1, VO1, and VO 2) to be output to the hysteresis window generation module 400a.
After receiving the control signals V1, VO1, and VO2, the hysteresis window generating module 400a generates a corresponding hysteresis current according to the control signals. The hysteresis window generating module 400a includes a first hysteresis differential pair circuit 401a and a second hysteresis differential pair circuit 402a for generating a first hysteresis current Ihysp and a second hysteresis current Ihysn. In this embodiment, the first hysteresis differential pair circuit 401a is composed of a fifth PMOS transistor and a sixth PMOS transistor, and the tail current thereof is I4, and the magnitude of the tail current is equal to I0, that is, the magnitude of the tail current is consistent with the tail currents of the second PMOS differential pair circuits P3 and P4 in the rail-to-rail input module 100 a. The second hysteresis differential pair circuit 402a is composed of a seventh PMOS transistor and an eighth PMOS transistor, and the tail current thereof is I5, and the magnitude of the tail current is equal to I1, that is, the magnitude of the tail current is consistent with the tail currents of the first PMOS differential pair circuits P1 and P2 in the rail-to-rail input module 100 a.
Under the control of VO1 and VO2, P5 and P7 will generate hysteresis currents Ihysp, P6 and P8 will generate hysteresis currents Ihysn, which will regulate the differential currents Ip and In generated by the rail-to-rail input module 100a and act on the load module 500a to generate corresponding differential voltages. Then, the differential voltage is converted into a single-ended output signal through the differential input single-ended output AMP in the gain amplification stage module 700a, and buffered and shaped by the two buffers BUF1 and BUF2 to obtain the final comparison results Z and VOUT of the comparison circuit, wherein Z is fed back to 300 a.
The specific working principle of the hysteresis comparison circuit is described below, and the principle of keeping the hysteresis window voltage unchanged in the method is also described.
For simplicity, the above-mentioned simple embodiment, i.e. the hysteresis comparison circuit in fig. 2, is also taken as an example, and it is assumed that the enable signal hys_en is logic 1, the input voltage is in a low common mode state, i.e. the first PMOS differential pair circuits P1, P2 in the rail-to-rail input module 100a are operating normally, the tail current i1=iref, the second PMOS differential pair circuits P3, P4 are turned off, and only the P7 and P8 in the second hysteresis differential pair 402a are operating in the 400a hysteresis window generating module, and the tail current i5=iref. If the initial condition is VIP < VIN, the current IP1 flowing through the first PMOS transistor P1 is greater than the current IP2 flowing through the second PMOS transistor P2, and the feedback signal Z output by the hysteresis comparison circuit is 0, the control signal vo1=vo2=v1 generated in the hysteresis window control circuit 300a, and at this time, the hysteresis current ihysp=ihysn output by the second hysteresis differential pair 402a, the current il1=ip1+ihysp flowing through the load, il2=ip2+ihysn, and it is known that IL1> IL2 at this time.
Along with the increase of VIP, the current IP1 in the current first PMOS transistor gradually decreases, when VIP increases to a moment greater than VIN, the output result of the comparator turns over, at this moment Z is 1, the control signal VO1 '=v2' =v0 generated in the hysteresis window control circuit 300a, the corresponding hysteresis current Ihysp '< Ihysn', assuming that the difference between the two is Ihy, at this moment IP1'≡ip2', the current IL1 '=ip 1' +ihysp ', IL2' =ip 2'+ihysn' flowing through the load, and at this moment IL1'< IL2', the difference between the two is Ihy.
Due to the hysteresis current, the voltage of the rising input signal VIP required for switching the output result Z of the comparison circuit from low to high is higher than the voltage of the falling input signal VIP required for switching the output result Z of the comparator from high to low, and the difference between the two voltages is the magnitude of the hysteresis window Δv. The hysteresis window voltage Δv versus differential current flowing through the first PMOS differential pair P1, P2 and the second hysteresis differential pair P7, P8 can be expressed as:
1/2(VIP-VIN)×Gm in ＝ΔI 1
1/2(VO2-VO1)×Gm h ＝ΔI 2
in the above, gm in Refers to the transconductance of the first PMOS differential pair P1, P2 input in the rail-to-rail input module 100 a; gm (Gm) h Is the transconductance of the second hysteresis differential pair P7, P8 in the hysteresis window control module 400 a; gm is general crystal Transconductance of transistor, id is leakage current of transistor, vgs is gate-source voltage of transistor, vth is threshold voltage of transistor, μ represents carrier mobility of transistor, C ox W and L are the width and length of the transistor, respectively, representing the capacitance of the gate oxide layer per unit area; ΔI 1 And DeltaI 2 Is the corresponding differential current. ΔI when the comparator is about to flip 1 Will be equal to ΔI 2 Equal in size, then there are:
if can ensure Gm in ＝2×Gm h The magnitude of the hysteresis window DeltaV is (VO 2-VO 1)/2, and the change of DeltaV and Gm can be seen in And Gm h Related to the ratio of (1) if Gm can be ensured in And Gm h The constant hysteresis window voltage deltav can be ensured by keeping the ratio of the hysteresis window voltage deltav consistent.
In this embodiment, the differential pair transconductance of the rail-to-rail input module 100a will change along with the change of the input common mode and is easily affected by temperature and power supply voltage, but a hysteresis window insensitive to the input common mode, temperature and power supply voltage can be formed as long as the hysteresis differential pair is guaranteed to generate the same change amount. Due toUnder the condition that the parameters of the first PMOS differential pair P1, P2 and the second hysteresis differential pair P7, P8 transistors in the rail-to-rail input module 100a are consistent, the ratio of the transconductance of the two can be regarded as the ratio of the tail currents flowing through the two, and because the tail currents of the two are equal, i.e. i1=i5, the Gm in And Gm h The variation of deltav can be kept constant and eventually a hysteresis window can be formed that does not vary with temperature, supply voltage and input common mode range.
Similarly, the tail currents of the second PMOS differential pair P3, P4 and the first hysteresis differential pair P5, P6 are the same.
As shown in fig. 4, in another embodiment, a hysteresis comparator circuit is more preferable, and it should be noted that hereinafter, PMOS transistors and NMOS transistors with the same names as those in the foregoing description will appear, but actually refer to different MOS transistors. The hysteresis comparison circuit shown in fig. 4 has the same components as those in the functional block diagram of fig. 1, and includes a rail-to-rail input module 100b, a bias power supply generation module 200b, a hysteresis window control module 300b, a hysteresis window generation module 400b, a load module 500b and a gain amplifier stage module 700b, wherein the bias power supply generation module 200b is shown in fig. 5, and the hysteresis window control module circuit 300b is shown in fig. 6.
In this embodiment, the first PMOS differential pair circuit in the rail-to-rail input module 100b includes a first PMOS transistor P1 and a second PMOS transistor P2, gates of the first and second PMOS transistors P1 and P2 are respectively used as a positive input terminal and a negative input terminal to correspondingly receive the positive input signal VIP and the negative input signal VIN, sources of the first and second PMOS transistors P1 and P2 are connected to a first current ISSP, and the current is provided by the bias power supply generating module 200 b;
The NMOS source follower circuit comprises a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a seventh PMOS tube P7 and an eighth PMOS tube P8, wherein grid electrodes of the first NMOS tube P1 and the second NMOS tube P2 are respectively used as negative input ends and positive input ends to correspondingly receive negative input signals VIN and positive input signals VIP, after level shifting, the grid electrodes are respectively input into a second PMOS differential pair circuit through source electrodes of the first NMOS tube N1 and the second NMOS tube N2, source electrodes of the first NMOS tube N1 and the second NMOS tube N2 are correspondingly connected to drain electrodes of the third NMOS tube N3 and the fourth NMOS tube N4, grid electrodes of the third NMOS tube N3 and the fourth NMOS tube N4 are connected with first voltage, namely bias voltage VBN, source electrodes of the third NMOS tube N3 and the fourth NMOS tube N4 are grounded to form a current source, and simultaneously serve as loads of the source follower circuit. The drains of the first NMOS tube N1 and the second NMOS tube N2 are respectively connected with the drains of the seventh PMOS tube P7 and the eighth PMOS tube P8.
The second PMOS differential pair circuit includes a third PMOS transistor P3 and a fourth PMOS transistor P4, gates of the third and fourth PMOS transistors P3 and P4 are respectively connected with sources of the first and second NMOS transistors N1 and N2 to receive the negative input signal VIN and the positive input signal VIP after level shift, drains of the third and fourth PMOS transistors P3 and P4 are respectively connected with drains of the first and second PMOS transistors P1 and P2 to input differential current signals Ip and In to the load module 500b, and these two currents interact with hysteresis currents generated by the hysteresis window generating module 400b to be converted into IL1 and IL2 respectively, and after flowing through the load module 500b, they are converted into voltage signals again.
Further, the rail-to-rail input module 100b further includes a fifth PMOS transistor and a sixth PMOS transistor, gates of the fifth PMOS transistor and the sixth PMOS transistor are respectively connected with gates of the seventh PMOS transistor and the eighth PMOS transistor, sources of the seventh PMOS transistor and the eighth PMOS transistor are connected with a power supply voltage, the gates and the drains are connected to form a current mirror, currents are mirrored to the fifth PMOS transistor and the sixth PMOS transistor, drains of the fifth PMOS transistor and the sixth PMOS transistor are connected to sources of the third NMOS transistor and the fourth NMOS transistor, and the sources of the fifth PMOS transistor and the sixth PMOS transistor are connected with the second PMOS differential pair circuit to provide tail currents.
In the bias power supply generating module 200b, the first summing circuit includes 5 PMOS transistors each having a source connected to a power supply voltage and a gate connected to each other, which are a ninth PMOS transistor, a tenth PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, and a fourteenth PMOS transistor, respectively, a source connected to a drain of the tenth PMOS transistor, and a gate of the eleventh PMOS transistor is connected to a drain of the twelfth PMOS transistor and then grounded through a resistor R1, where the drain of the tenth PMOS transistor outputs the first current ISSP and the eleventh PMOS transistor outputs the first voltage VBN.
The second summing circuit comprises a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a fifteenth PMOS tube and a sixteenth PMOS tube, wherein the gates of the fifth NMOS tube, the seventh NMOS tube and the ninth NMOS tube are connected, the sources of the fifth NMOS tube, the seventh NMOS tube and the ninth NMOS tube are respectively connected with the drains of the sixth NMOS tube, the eighth NMOS tube and the tenth NMOS tube, the gates of the sixth NMOS tube, the eighth NMOS tube and the tenth NMOS tube are connected with each other, the sources of the sixth NMOS tube, the eighth NMOS tube and the tenth NMOS tube are grounded, the drain of the fifth NMOS tube is connected with a reference current IREF, the drain of the seventh NMOS tube is connected with the drain of the ninth PMOS tube, the drain of the ninth NMOS tube outputs a second current Itp and is connected with the drain of the PMOS tube, the fifteenth PMOS tube and the sixteenth NMOS tube form a current mirror, the drain of the sixteenth PMOS tube is connected with the drain of the twelfth NMOS tube, the drain of the twelfth NMOS tube and the eleventh NMOS tube forms a current mirror, and the drain of the twelfth NMOS tube is connected with the drain of the eleventh PMOS tube.
In this embodiment, the reference current IREF input into the bias power generation module 200b may be generated by a bandgap reference circuit so as to be kept relatively constant over a range of voltages and temperatures, thereby ensuring the stability of the bias circuit. Two current summing circuits are arranged in the module to respectively generate tail currents ISSP of a first PMOS differential pair of a first PMOS tube P1 and a second PMOS tube P2 in the rail-to-rail input module 100b and bias voltages VBN of a third NMOS tube N3 and a fourth NMOS tube N4 of a source follower load tube; the other can dynamically adjust the set of tail currents Itp of the hysteresis window generating module based on the magnitude of VBN.
IN this embodiment, the current level of IP9 is IREF, IP10 is 2×iref, IN9 is 2×iref, IP12 is IREF, the gate voltage of the eleventh PMOS is iref×r1, and ip11=in11, according to the above definition of the combination circuit, issp=ip10-ip11=2×iref-IP11, itp =in9-ip15=2×iref-IP11, so issp= Itp, vbn=vgs11, where IP9 is the current flowing through the ninth PMOS P9, IP10 is the current flowing through the tenth PMOS, IN9 is the current flowing through the ninth PMOS, IP12 is the current flowing through the twelfth PMOS, IP11 is the current flowing through the eleventh PMOS, IN11 is the current flowing through the eleventh NMOS, and R1 is the resistance of the resistor R1. It is understood that ISSP is equal in size to Itp and constant in sum to IP11 is 2 IREF, and IP11 determines VBN,
In this embodiment, the ISSP is the tail current of the first PMOS differential pair, the magnitude of which is affected by the input common mode level, the bias voltage VBN is the current source of the source followers N3 and N4, and the magnitude of which is also affected by the input common mode level, and it is known from the above-derived relationship that the relationship between the ISSP and VBN is related to the input common mode level.
When the input common mode level is low, the first PMOS differential pair P1 and P2 IN the rail-to-rail input module 100b is turned on, the second PMOS differential pair P3 and P4 is turned off, the ISSP is about 2×iref, the tail current flowing into P3 and P4 is about 0, the P11 is turned off IN the bias power supply generating module 200b, the values of IP11 and IN11 are about 0, and the vbn is small, so Itp is about 2×iref.
When the input common mode level is at the intermediate value, the first PMOS differential pair P1, P2 and the second PMOS differential pair P3, P4 in the rail-to-rail input module 100b are both turned on, and after the size of R1 is reasonably set, the size of IP11 can be exactly IREF, and the size of ISSP is also IREF; at this time, tail currents of the differential pairs P1, P2, P3, and P4 in the rail-to-rail input module 100b are IREF;
when the input common mode level is high, the differential pair P1, P2 IN the rail-to-rail input module 100b is turned off, the differential pair P3, P4 is turned on, the ISSP is about 0, the tail current flowing into the differential pair P3, P4 is 2×iref, the differential pair P11 IN the bias power generation module 200b is turned on, the values of IP11 and IN11 are about 2×iref, and the vbn is larger, and the value of vbn is about Itp is about 0.
By adopting the technology, when the rail-to-rail input module 100b receives the input common mode level in the full voltage range, tail currents of the two differential pairs can be adaptively changed, so that normal operation is maintained, and the problem that the existing hysteresis comparator cannot process the input common mode signal in the wide voltage range can be solved by adding a small amount of circuits.
Meanwhile, in the bias power generating module 200b, the currents flowing through the thirteenth PMOS transistor and the fourteenth PMOS transistor are used as the operating currents ISS1 and ISS2 of the gain amplifying stage module 700 b.
The hysteresis window control modules 300b are substantially identical in structure and function to the hysteresis window control modules 300a, except that more control codes are provided to cope with the requirements of different hysteresis windows. In this embodiment, the control code is one or more bits, and when the control code is more than one bit, the number of logic gates is increased to twice the number of control code bits, and the number of the first control signals obtained at this time is also increased to twice the number of control code bits.
As shown in the hysteresis window control module 300b of fig. 6, the hysteresis window control code a is 4 bits, and may sequentially generate a hysteresis window with a fixed step value, where the corresponding hysteresis window is minimum when the control code is 0000, and the corresponding hysteresis window is maximum when the control code is 1111. Since the number of control code bits is increased, the control signals output by 300b are also increased to 8, i.e., VO1 to VO8, respectively, and the number of transistors is additionally increased in the hysteresis window generating module 400b, and is controlled by V1, VO1 to VO 8.
As shown in fig. 4, the hysteresis window generating module 400b includes a first hysteresis differential pair circuit 401b and a second hysteresis differential pair circuit 402b for generating a first hysteresis current and a second hysteresis current;
each hysteresis differential circuit comprises two groups of PMOS (P-channel metal oxide semiconductor) tubes, each group of PMOS tubes comprises one PMOS tube (P18, P21, P24 and P27) for receiving a second control signal V1, and the number of the PMOS tubes in parallel connection for receiving first control signals (VO 1-VO 8) is consistent with the number of control code bits, and V01, V03, V05 and V07 in the first control signals are respectively received by P20<3:0> in the first hysteresis differential pair circuit 401b and P26<3:0> in the second hysteresis differential pair circuit 402 b; v02, V04, V06, and V08 in the first control signal are received by P19<3:0> in the first hysteresis differential pair circuit 401b and P25<3:0> in the second hysteresis differential pair circuit 402b, respectively. The two groups of PMOS tube gates belonging to the same hysteresis differential circuit are used for receiving corresponding control signals, the drains of the two groups of PMOS tube gates are respectively connected and then used for outputting hysteresis current, and the sources of the two groups of PMOS tube gates are connected and then used for receiving tail current.
In this embodiment, the second hysteresis differential pair circuit 402b further includes two PMOS transistors (P22 and P23) to form a current mirror circuit to mirror the second current Itp into the second hysteresis differential pair circuit 402b as the tail current, so that the tail currents of the first PMOS differential pair circuits P1 and P2 are consistent with the tail current of the second hysteresis differential pair circuit 402 b.
The first hysteresis differential pair circuit 401b further includes two drain electrodes connected, and a gate electrode connected to the sixteenth PMOS transistor P16 and the seventeenth PMOS transistor P17 of the seventh and eighth PMOS transistor gates of the rail-to-rail input module, respectively, for providing the first hysteresis differential pair circuit 401b with a tail current having a magnitude identical to that of the tail current in the second PMOS differential pair circuit.
In this embodiment, parameters of the PMOS transistors in the first PMOS differential pair circuit and the second PMOS differential pair circuit in the on-track input module and the hysteresis window generating module are identical, and parameters of the PMOS transistors in the second PMOS differential pair circuit and the first hysteresis differential circuit are identical. And parameters of the PMOS tubes in the two hysteresis differential circuits are kept consistent.
Next, the circuit implementation is performed for the optimized embodiment in fig. 4, and the actual circuit is built in Cadence to simulate. Firstly, simulation of a hysteresis window is carried out, a simulation result is shown in fig. 7, VIN in the diagram is the reference voltage of the comparator, the VIP is the input voltage, and direct current hysteresis scanning is carried out on the VIP under a default simulation environment of the simulator to obtain the result shown in fig. 7, wherein Z is the output of the comparator. As can be seen from the simulation results, as the VIP rises and falls, the output result Z of the comparator also changes and forms a hysteresis window, which is measured by a scale tool of the simulator, the size of the hysteresis window is seen to be 28.5mV, and the size of the hysteresis window is recorded as a variable Hyst_win to facilitate subsequent simulation.
Next, simulation of the hysteresis window size of the hysteresis comparator and the control code is performed, and the hysteresis window size corresponding to the control code a at different values is simulated, as shown in fig. 8. It can be seen that when the control code A is 0001, the hysteresis window obtained by simulation is 9mV; when the control code A is 0011, the hysteresis window obtained by simulation is 18.5mV; when the control code A is 0111, the hysteresis window is 18mV; when the control code A is 1111, the hysteresis window is 37.5mV; in these 4-bit control codes, the step size of each bit is very accurate 9.5mV.
As a result of simulating the influence of the change of the input common mode level on the size of the hysteresis window, as shown in FIG. 9, the simulation environment is the power supply voltage VDD=3.3V, the temperature TEMP=40deg.C, the change range of the input common mode level VCM is 0V-3.3V, and it can be found that the hysteresis window size Hyst_win is changed slightly from the lowest 28.5mV to the highest 31mV, the change rate is 8.3% along with the increase of the input common mode.
The influence of the change of the simulation temperature on the size of the hysteresis window is set to vdd=3.3v, the range of temp is-40-125 ℃, 3 typical conditions are selected from input common mode level, low common mode is 0.6V, intermediate value common mode is 1.65V and high common mode is 2.7V, the 3 conditions are respectively carried out, and the simulation result is shown in fig. 10. It can be found that in the low common mode case, the hysteresis window varies with temperature by 1mV; in the case of the intermediate value common mode, the hysteresis window varies by 2mV with temperature; in the case of the high common mode, the hysteresis window varies with temperature by 1.5mV. This illustrates that the size of the hysteresis window can remain substantially constant at various temperatures.
Finally, simulating the influence of the power supply voltage change on the size of a hysteresis window, and setting a simulation environment: the power supply voltage ranges from 2.97V to 3.63V, temp=40 ℃, the input common mode level still selects 3 typical conditions, and the simulation result is shown in fig. 11. It can be found that in the low common mode case the hysteresis window is constant at 28.5mV; in the case of the medium value common mode, the hysteresis window varies by 0.5mV with the supply voltage; in the case of the high common mode, the hysteresis window varies by 3mV with the supply voltage, corresponding to a 10% rate of change. This indicates that the size of the hysteresis window is insensitive to variations in supply voltage variations, and the rate of change is only 10% at maximum.
In the hysteresis comparison circuit, an input signal can work in the whole voltage range from a power supply voltage to the ground, a rail-to-rail input stage which is easy to realize is configured in the hysteresis comparison circuit, the total transconductance of the input stage is insensitive to the common mode level of the input voltage, and the hysteresis window voltage is stable and can be adjusted. The hysteresis comparison circuit in the application has high precision and high working speed, adopts a multistage operational amplifier cascade mode, can achieve very high gain, further improves the comparison precision of the comparator, and can further improve the working speed of the whole comparator by selecting a proper input stage load structure.
In the present application, there is also provided an electronic device including the hysteresis comparison circuit described in any one of the embodiments above.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. A hysteresis comparison circuit, comprising: the input end of the rail-to-rail input module is used for receiving positive and negative input signals, the output end of the rail-to-rail input module is connected to the load module and the hysteresis window generation module, the input end of the hysteresis window control module is used for receiving feedback signals output by a control code and a hysteresis comparison circuit, the output end of the hysteresis window control module is connected to the hysteresis window generation module, the output end of the hysteresis window generation module is used for being connected to the load module, the output end of the load module is used for being connected to the gain amplification stage module, the gain amplification stage module is connected to the buffer, the output end of the buffer outputs the feedback signals and single-ended output signals of the hysteresis comparison circuit, the input end of the bias power generation module is used for receiving reference currents, and the output ends of the bias power generation module are respectively connected to the rail-to-rail input module, the hysteresis window control module and the hysteresis window generation module;
The rail-to-rail input module comprises a PMOS differential pair circuit and an NMOS source follower circuit, and is used for generating corresponding differential current signals according to the positive and negative input signals, namely differential voltage signals, and outputting the differential current signals to the load module, wherein the differential voltage signals are reduced by the NMOS source follower circuit and then are input into the differential pair circuit;
the hysteresis window control module comprises a voltage dividing resistor string circuit and a logic gate circuit and is used for generating a control signal according to the logic relation between the control code and the feedback signal;
the hysteresis window generation module comprises two groups of hysteresis differential pair circuits, and is used for generating two hysteresis currents according to the control signals and acting on the differential current signals to adjust the hysteresis currents so that the load module generates hysteresis window voltages corresponding to the control signals;
the bias power supply generating module comprises a first current summing circuit and a second current summing circuit, wherein the first current summing circuit generates a first current and a first voltage, the first current and the first voltage are output to the rail-to-rail input module and are respectively used as tail currents of the differential pair circuit and bias voltages of the NMOS source follower circuit, and the second current summing circuit dynamically generates a second current consistent with the first current variable quantity according to the first voltage and inputs the second current to the hysteresis window generating module to be used as tail currents of the hysteresis differential pair circuit.
2. The hysteresis comparison circuit of claim 1, further comprising a gain amplifier stage module connected between the output of the load module and the input of the buffer module.
3. The hysteresis comparator circuit of claim 2, wherein in the rail-to-rail input module, the differential pair circuit comprises a first PMOS differential pair circuit and a second PMOS differential pair circuit, the differential voltage signal is simultaneously input into the first PMOS input differential pair circuit and an NMOS source follower circuit, and the differential voltage signal is reduced by the NMOS source follower circuit and then input into the second PMOS input differential pair circuit;
and the first current generated by the first current summation circuit is used as the tail current of the first PMOS differential pair circuit.
4. The hysteresis comparison circuit of claim 3, wherein,
the first PMOS differential pair circuit comprises a first PMOS tube and a second PMOS tube, the grid electrodes of the first PMOS tube and the second PMOS tube are respectively used as a positive input end and a negative input end for correspondingly receiving a positive input signal and a negative input signal, and the source electrodes of the first PMOS tube and the second PMOS tube are connected with the first current;
The NMOS source follower circuit comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a seventh PMOS tube and an eighth PMOS tube, wherein the grid electrodes of the first NMOS tube and the second NMOS tube are respectively used as negative input ends and positive input ends to correspondingly receive the positive input signals and the negative input signals, the grid electrodes of the first NMOS tube and the second NMOS tube are respectively input into the second PMOS differential pair circuit after level shifting, the source electrodes of the first NMOS tube and the second NMOS tube are respectively and correspondingly connected to the drain electrodes of the third NMOS tube and the fourth NMOS tube, the grid electrodes of the third NMOS tube and the fourth NMOS tube are connected with the first voltage, the source electrodes of the third NMOS tube and the fourth NMOS tube are grounded, the drain electrodes of the first NMOS tube and the second NMOS tube are respectively connected with the drain electrodes of the seventh PMOS tube and the eighth PMOS tube,
the second PMOS differential pair circuit comprises a third PMOS tube and a fourth PMOS tube, the grid electrodes of the third PMOS tube and the fourth PMOS tube are respectively connected with the source electrodes of the first NMOS tube and the second NMOS tube to receive positive input signals and negative input signals after level shifting, and the drain electrodes of the third PMOS tube and the fourth PMOS tube are respectively connected with the drain electrodes of the first PMOS tube and the second PMOS tube to input differential current signals to the load module;
the rail-to-rail input module further comprises a fifth PMOS tube and a sixth PMOS tube, the grid electrodes of the fifth PMOS tube and the sixth PMOS tube are respectively connected with the grid electrodes of the seventh PMOS tube and the eighth PMOS tube, the source electrodes of the seventh PMOS tube and the eighth PMOS tube are connected with a power supply voltage, the grid electrodes and the drain electrodes are connected to form a current mirror, currents are mirrored to the fifth PMOS tube and the sixth PMOS tube, and the drain electrodes of the fifth PMOS tube and the sixth PMOS tube are connected to the source electrodes of the third NMOS tube and the fourth NMOS tube to provide tail currents for the second PMOS differential pair circuit.
5. The hysteresis comparison circuit of claim 4, wherein in the hysteresis window control module:
the voltage dividing resistor string circuit is connected with reference voltage, and three voltage dividing voltage signals are obtained after the reference voltage is divided;
the logic gate circuit comprises a NAND gate, an inverter and 4 transmission gates;
the NAND gate is provided with two input ends respectively used for receiving the control code and the feedback signal and outputting a first logic signal, and the input end of the inverter is used for receiving the first logic signal and outputting a second logic signal;
and using each divided voltage signal as an input signal of a transmission gate, controlling the on and off of each transmission gate by using the first logic signal and the second logic signal to output corresponding first control signals, wherein the number of the first control signals is two, one divided voltage signal is used as a second control signal, and the first control signal and the second control signal are used as the control signals to be output to the hysteresis window generation module.
6. The hysteresis comparator circuit according to claim 5, wherein the control code is one or more bits, and when the control code is more than one bit, the number of logic gates is increased to twice the number of control code bits, and the number of first control signals obtained is also increased to twice the number of control code bits.
7. The hysteresis comparison circuit of claim 6, wherein the hysteresis window generation module comprises a first hysteresis differential pair circuit and a second hysteresis differential pair circuit for generating a first hysteresis current and a second hysteresis current;
each hysteresis differential circuit comprises two groups of PMOS (P-channel metal oxide semiconductor) tubes, each group of PMOS tubes comprises one PMOS tube for receiving the second control signal and a plurality of PMOS tubes in parallel connection for receiving the first control signal, the number of the PMOS tubes for receiving the first control signal is consistent with the number of control code bits, wherein two groups of PMOS tube grids belonging to the same hysteresis differential circuit are used for receiving corresponding control signals, the drains of the two groups of PMOS tubes are respectively connected and then used for outputting hysteresis current, and the sources of the two groups of PMOS tubes are connected and then used for receiving tail current;
the second hysteresis differential pair circuit further comprises a current mirror circuit formed by two PMOS tubes, and the second current is mirrored into the second hysteresis differential pair circuit to be used as tail current;
the first hysteresis differential pair circuit further comprises two PMOS tubes, wherein the drain electrodes of the two PMOS tubes are connected, the grid electrodes of the PMOS tubes are respectively connected to the seventh PMOS tube grid electrode and the eighth PMOS tube grid electrode of the rail-to-rail input module, and the PMOS tubes are used for providing tail currents with the same size as the tail currents in the second PMOS differential pair circuit for the first hysteresis differential pair circuit.
8. The hysteresis comparison circuit of claim 7, wherein in the bias power generation module:
the first summing circuit comprises 5 PMOS tubes, wherein the sources of the 5 PMOS tubes are connected with the power supply voltage, the gates of the 5 PMOS tubes are respectively a ninth PMOS tube, a tenth PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube and a fourteenth PMOS tube, the sources of the eleventh PMOS tube are connected with the drain electrode of the tenth PMOS tube, the gates of the eleventh PMOS tube are connected with the drain electrode of the twelfth PMOS tube and then grounded through a resistor, and the drain electrode of the tenth PMOS tube outputs the first current and the eleventh PMOS tube outputs the first voltage;
the second summing circuit comprises a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a fifteenth PMOS tube and a sixteenth PMOS tube, wherein the grid electrodes of the fifth NMOS tube, the seventh NMOS tube and the ninth NMOS tube are respectively connected with the drain electrodes of the sixth NMOS tube, the eighth NMOS tube and the tenth NMOS tube, the grid electrodes of the sixth NMOS tube, the eighth NMOS tube and the tenth NMOS tube are mutually connected, the source electrodes of the eighth NMOS tube are grounded, the drain electrode of the fifth NMOS tube is connected with the reference current, the drain electrode of the seventh NMOS tube is connected with the drain electrode of the ninth PMOS tube, the drain electrode of the ninth NMOS tube outputs the second current and is connected with the drain electrode of the fifteenth PMOS tube, the fifteenth PMOS tube and the sixteenth PMOS tube form a current mirror, the drain electrode of the sixteenth PMOS tube and the drain electrode of the twelfth NMOS tube are respectively connected with the drain electrode of the NMOS tube, the drain electrode of the twelfth PMOS tube and the eleventh tube form a current mirror.
9. The hysteresis comparison circuit according to any one of claims 1-8, wherein parameters of PMOS tubes in the first PMOS differential pair circuit and the second PMOS differential pair circuit are identical or proportioned in the rail-to-rail input module and the hysteresis window generation module; and the parameters of the PMOS tubes in the second PMOS differential pair circuit and the first hysteresis differential circuit are consistent or the proportion is the same.
10. An electronic device comprising the hysteresis comparison circuit of claim 9.
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