CN116435324B - Semiconductor structure, preparation method thereof and semiconductor device - Google Patents

Semiconductor structure, preparation method thereof and semiconductor device Download PDF

Info

Publication number
CN116435324B
CN116435324B CN202310681725.0A CN202310681725A CN116435324B CN 116435324 B CN116435324 B CN 116435324B CN 202310681725 A CN202310681725 A CN 202310681725A CN 116435324 B CN116435324 B CN 116435324B
Authority
CN
China
Prior art keywords
channel
gate
substrate
forming
isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202310681725.0A
Other languages
Chinese (zh)
Other versions
CN116435324A (en
Inventor
李赟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hubei Jiangcheng Chip Pilot Service Co ltd
Original Assignee
Hubei Jiangcheng Chip Pilot Service Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hubei Jiangcheng Chip Pilot Service Co ltd filed Critical Hubei Jiangcheng Chip Pilot Service Co ltd
Priority to CN202310681725.0A priority Critical patent/CN116435324B/en
Publication of CN116435324A publication Critical patent/CN116435324A/en
Application granted granted Critical
Publication of CN116435324B publication Critical patent/CN116435324B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H01L27/14616—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor characterised by the channel of the transistor, e.g. channel having a doping gradient
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The embodiment of the disclosure discloses a semiconductor structure, a preparation method thereof and a semiconductor device. The semiconductor structure includes: a substrate; at least two isolation structures, at least a portion of the isolation structures being located in the substrate; an active region between two adjacent isolation structures and in the substrate, comprising: a channel; a gate electrode, comprising: a first portion and a second portion; wherein the first portion is located over the channel; the second part is positioned between at least one of the two adjacent isolation structures and the channel; and the gate dielectric layer is positioned between the gate and the channel.

Description

Semiconductor structure, preparation method thereof and semiconductor device
Technical Field
The embodiment of the disclosure relates to the field of semiconductors, in particular to a semiconductor structure, a preparation method thereof and a semiconductor device.
Background
In a sub-micron image sensor (CMOS Image Sensor, CIS), increasing the full well capacity (Full Well Capacity, FWC) and reducing noise are two issues that need to be addressed. If the full well capacity is to be increased, the area of the pixel array needs to be increased; to reduce noise (e.g., random telegraph noise (Random Telegraph Signal, RTS)), the area of a Source Follower (SF) transistor needs to be increased. In the conventional design, the area of the pixel array and the source follower transistor cannot be increased at the same time without changing the size of the image sensor, which would affect electron transfer and even cause short circuit.
Therefore, how to reduce the noise of the image sensor without increasing the area of the source follower transistor is a technical problem to be solved.
Disclosure of Invention
According to a first aspect of embodiments of the present disclosure, there is provided a semiconductor structure comprising:
a substrate;
at least two isolation structures, at least a portion of which are located in the substrate;
an active region located between two adjacent isolation structures and in the substrate, comprising: a channel;
a gate electrode, comprising: a first portion and a second portion; wherein the first portion is located over the channel; the second portion is located between at least one of the two adjacent isolation structures and the channel;
and the gate dielectric layer is positioned between the gate and the channel.
In some embodiments, the channel includes opposing first and second sides;
the second portion covers at least a portion of the first side; and/or, the second portion covers at least part of the second side.
In some embodiments, the gate has a dimension greater than or equal to a dimension of the channel in a direction parallel to a plane in which the substrate lies when the second portion covers at least a portion of the first side and at least a portion of the second side.
In some embodiments, a surface of the isolation structure in contact with the second portion has a recess directed along the second portion toward the isolation structure.
In some embodiments, the sum of the dimensions of the second portion and the gate dielectric layer in a direction parallel to the plane of the substrate ranges from 10nm to 500nm.
According to a second aspect of embodiments of the present disclosure, there is provided a method for manufacturing a semiconductor structure, including:
providing a substrate;
forming at least two isolation structures, wherein at least part of the isolation structures are positioned in the substrate;
forming an active region, wherein the active region is positioned between two adjacent isolation structures and positioned in the substrate; wherein the active region comprises a channel;
forming a grid electrode; wherein the gate includes a first portion and a second portion; the first portion is located over the channel; the second portion is located between at least one of the two adjacent isolation structures and the channel;
and forming a gate dielectric layer between the gate and the channel.
In some embodiments, the channel includes opposing first and second sides;
the forming the gate includes:
forming said second portion overlying at least a portion of said first side; and/or forming said second portion covering at least part of said second side.
In some embodiments, the method of making further comprises:
forming a buffer layer covering the substrate;
forming at least two isolation trenches, wherein the isolation trenches penetrate through the buffer layer and part of the substrate;
forming an isolation material layer in the isolation trench;
the forming the gate includes:
etching a part of at least one of the two adjacent isolation material layers along the direction facing the substrate to form a groove; wherein the remaining isolation material layer constitutes the isolation structure; the groove is positioned between the isolation structure and the channel;
the second portion is formed in the recess.
In some embodiments, prior to forming the groove, the method of making further comprises:
forming a photoresist layer covering the buffer layer and the isolation material layer;
forming an opening in the photoresist layer; wherein the opening exposes a portion of at least one of the buffer layer and two adjacent layers of the isolation material covering the channel;
and performing doping treatment on the exposed buffer layer and the isolation material layer.
In some embodiments, the doping treated ions comprise: at least one of arsenic ions, phosphorus ions, or nitrogen ions.
In some embodiments, the etching process includes: and (5) wet etching.
According to a third aspect of the embodiments of the present disclosure, there is provided a semiconductor device including:
a semiconductor structure as described in any one of the embodiments above;
a pixel array coupled with the semiconductor structure, comprising: at least one pixel cell.
In some embodiments, the semiconductor device includes an image sensor.
In the embodiment of the disclosure, the gate comprises the first part and the second part, the first part is arranged on the channel, and the second part is arranged between the channel and at least one of the two adjacent isolation structures, so that the control area of the gate to the channel is increased, the control capability of the gate to the channel is increased, the leakage current of the transistor is reduced, and the short channel effect is inhibited.
In addition, in the embodiment of the disclosure, the second part of the gate is arranged between the isolation structure and the channel, and the second part of the gate is arranged by utilizing the space of part of the isolation structure, so that the control capability of the gate to the channel is enhanced, the size of the transistor is not increased, the area of the transistor is not increased, and the noise of the image sensor comprising the transistor is reduced.
Drawings
FIG. 1 is a schematic diagram of an image sensor shown according to an exemplary embodiment;
FIG. 2 is a scanning electron microscope image of a semiconductor structure shown according to an example embodiment;
fig. 3 is a schematic diagram of a semiconductor structure shown in accordance with an embodiment of the present disclosure;
fig. 4 is a flow chart illustrating a method of fabricating a semiconductor structure, in accordance with an embodiment of the present disclosure;
fig. 5a is a schematic illustration of a process for fabricating a semiconductor structure according to an embodiment of the disclosure;
fig. 5b is a schematic diagram of a second process for fabricating a semiconductor structure according to an embodiment of the disclosure;
fig. 5c is a schematic diagram three of a process for fabricating a semiconductor structure according to an embodiment of the disclosure;
fig. 5d is a schematic diagram of a process for fabricating a semiconductor structure according to an embodiment of the disclosure;
fig. 5e is a schematic diagram five of a process for fabricating a semiconductor structure according to an embodiment of the disclosure;
fig. 5f is a schematic diagram of a process for fabricating a semiconductor structure according to an embodiment of the disclosure.
Detailed Description
The technical scheme of the present disclosure will be further elaborated with reference to the drawings and examples. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The present disclosure is described more specifically in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the description in the following specification. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the disclosure.
In the presently disclosed embodiments, the terms "first," "second," and the like are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
The technical solutions described in the embodiments of the present disclosure may be arbitrarily combined without any conflict.
Fig. 1 is a schematic diagram of an image sensor 10, shown according to an exemplary embodiment. Referring to fig. 1, the image sensor 10 includes a source follower 20 and a pixel array 30, and in the case of ensuring that the area of the image sensor 10 is not changed, if the area of the source follower 20 is increased in order to reduce noise, the area of the pixel array 30 is reduced to reduce the full well capacity; if the area of the pixel array 30 is increased in order to increase the full well capacity, the area of the source follower 20 is reduced to increase noise; if the area of the source follower 20 and the pixel array 30 are required to be increased simultaneously in order to reduce noise and increase the full-well capacity, the area of the image sensor 10 is increased, which is disadvantageous in that the integration level and the size of the image sensor 10 are improved.
Fig. 2 is a schematic diagram of a semiconductor structure 100, according to an example embodiment. Referring to fig. 2, semiconductor structure 100 includes a substrate 110, shallow trench isolation 120, an active region, a gate 140, and a gate dielectric layer 150. The active region is located between two adjacent shallow trench isolations 120, the active region includes a channel 130, a gate 140 is located on the channel 130, and a gate dielectric layer 150 is located between the gate 140 and the channel 130. Since there is only one contact surface between the gate 140 and the channel 130, the control area of the gate 140 on the channel 130 is smaller, resulting in weaker control capability of the gate 140 on the channel 130, so that the leakage current of the transistor increases and the presence of short channel effect may generate noise in the image sensor. Here, the semiconductor structure 100 may be used as a source follower transistor in an image sensor.
In addition, as semiconductor devices are being developed toward higher bit densities and higher integration levels, the feature sizes of transistors are further reduced, so that the gate-to-channel controllability is further reduced, resulting in further increased noise of the image sensor.
In view of this, embodiments of the present disclosure provide a semiconductor structure, a method for manufacturing the same, and a semiconductor device.
Fig. 3 is a schematic diagram of a semiconductor structure 200, shown in accordance with an embodiment of the present disclosure. Referring to fig. 3, a semiconductor structure 200 includes:
a substrate 210;
at least two isolation structures 220, at least a portion of the isolation structures 220 being located in the substrate 210;
an active region located between two adjacent isolation structures 220 and in the substrate 210, comprising: a channel 230;
gate 240, comprising: a first portion 241 and a second portion 242; wherein the first portion 241 is located above the channel 230; the second portion 242 is located between at least one of the adjacent two isolation structures 220 and the channel 230;
a gate dielectric layer 250 is located between gate 240 and channel 230.
The semiconductor structure 200 includes a thin film transistor, for example, an amorphous silicon thin film transistor, a polysilicon thin film transistor, a metal oxide thin film transistor, or the like, and the type of the thin film transistor includes a P-type transistor or an N-type transistor. In other embodiments, semiconductor structure 200 may also be other types of field effect transistors. In one embodiment, the semiconductor structure 200 may be a source follower transistor.
The materials of the substrate 210 include: elemental semiconductor materials (e.g., silicon, germanium), group iii-v compound semiconductor materials, group ii-vi compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. In other embodiments, the substrate 210 may also be silicon-on-insulator or the like.
In some embodiments, the isolation structures 220 are located entirely within the substrate 210, with the surface of the isolation structures 220 being flush with the surface of the substrate 210.
In other embodiments, a portion of the isolation structure 220 is located in the substrate 210, another portion of the isolation structure 220 protrudes from the surface of the substrate 210, and the protruding portion of the isolation structure 220 has a dimension in the z-direction of 100 angstroms to 300 angstroms.
The material of the isolation structure 220 includes a dielectric material, such as at least one of silicon oxide, silicon nitride, or silicon oxynitride.
It should be noted that, although only two isolation structures 220 are shown in fig. 3, in the embodiment of the present disclosure, the number of isolation structures 220 is not limited to two, and may be three or more.
The active regions are located in the substrate 210, and an isolation structure 220 isolates adjacent two active regions. The active region includes a source, a channel 230, and a drain disposed in parallel along the y-direction, the channel 230 being located between the source and the drain. The number of active regions may be one or more, and the present disclosure is not particularly limited thereto.
It should be noted that, in the embodiment of the present disclosure, the z direction is perpendicular to the plane of the substrate 210, the x direction and the y direction are parallel to the plane of the substrate 210, the x direction and the y direction intersect, and an included angle between the x direction and the y direction includes an acute angle, a right angle, or an obtuse angle. In one embodiment, the angles between the x-direction and the y-direction are right angles, i.e., the x-direction, the y-direction, and the z-direction are perpendicular.
In an example, the gate 240 includes a first portion 241 and a second portion 242a, the first portion 241 is located above the channel 230, and the second portion 242a is located between one of the two adjacent isolation structures 220 and the channel 230, such that a control area of the gate 240 on the channel 230 is increased, and a control capability of the gate 240 on the channel 230 is increased, which is beneficial for reducing a leakage current of the transistor and suppressing a short channel effect.
In another example, the gate 240 includes a first portion 241 and a second portion 242b, the first portion 241 being located over the channel 230, the second portion 242b being located between the other of the two adjacent isolation structures 220 and the channel 230, such that the control area of the gate 240 over the channel 230 is increased, the control capability of the gate 240 over the channel 230 is increased, which is beneficial for reducing leakage current of the transistor and suppressing short channel effects.
In yet another example, the gate 240 includes a first portion 241, a second portion 242a, and a second portion 242b, where the first portion 241 is located above the channel 230, and the second portion 242a and the second portion 242b are located between two adjacent isolation structures and the channel 230, respectively, so that the control area of the gate 240 on the channel 230 is further increased, and the control capability of the gate 240 on the channel 230 is further increased, which is beneficial to further reducing the leakage current of the transistor and suppressing the short channel effect.
It should be noted that the second portion 242a and the second portion 242b each represent the second portion 242, and different reference numerals are only used to distinguish the second portion 242 at different positions, and are not necessarily used to describe a specific order or sequence.
The material of the gate 240 includes a conductive material, for example, at least one of polysilicon, doped polysilicon, titanium nitride, tungsten nitride, tantalum nitride, tungsten, tantalum, platinum, titanium, or aluminum. In some embodiments, gate 240 may be a single layer film. In other embodiments, gate 240 may be a composite film of multiple film layers.
Gate dielectric layer 250 is located between channel 230 and gate 240, and the materials of gate dielectric layer 250 include: silicon oxide, silicon nitride, or silicon oxynitride, etc.
In the embodiment of the disclosure, the gate comprises the first part and the second part, the first part is arranged on the channel, and the second part is arranged between the channel and at least one of the two adjacent isolation structures, so that the control area of the gate to the channel is increased, the control capability of the gate to the channel is increased, the leakage current of the transistor is reduced, and the short channel effect is inhibited.
In addition, in the embodiment of the disclosure, the second part of the gate is arranged between the isolation structure and the channel, and the second part of the gate is arranged by utilizing the space of part of the isolation structure, so that the control capability of the gate to the channel is enhanced, the size of the transistor is not increased, the area of the transistor is not increased, and the noise of the image sensor comprising the transistor is reduced.
In some embodiments, channel 230 includes opposing first and second sides 231a, 231b; the second portion 242a covers at least a portion of the first side 231a; and/or, the second portion 242b covers at least a portion of the second side 231b. The first side 231a and the second side 231b are located at opposite sides of the channel 230 in the x-direction.
In an example, the gate 240 includes a second portion 242a, the second portion 242a being located between the isolation structure 220 and the first side 231a, the second portion 242a covering at least a portion of the first side 231a. Here, the second portion 242a may partially cover the first side 231a or may entirely cover the first side 231a, and as the area of the second portion 242a covering the first side 231a increases, the control capability of the gate electrode 240 with respect to the channel 230 increases.
In another example, the gate 240 includes a second portion 242b, the second portion 242b being located between the isolation structure 220 and the second side 231b, the second portion 242b covering at least a portion of the second side 231b. Here, the second portion 242b may partially cover the second side 231b or may entirely cover the second side 231b, and as the area of the second portion 242b covering the second side 231b increases, the control capability of the gate electrode 240 with respect to the channel 230 increases.
In yet another example, the gate 240 includes a second portion 242a and a second portion 242b, the second portion 242a being located between the isolation structure 220 and the first side 231a, the second portion 242b being located between the isolation structure 220 and the second side 231b. Here, the second portion 242a may partially or completely cover the first side 231a; and/or the second portion 242b may partially or completely cover the second side 231b, as the area of the second portion 242a covering the first side 231a and the second portion 242b covering the second side 231b further increases, the control of the gate 240 over the channel 230 further increases.
In an embodiment of the disclosure, at least a portion of the first side of the channel is covered by providing a second portion of the gate; and/or the second part covers at least part of the second side surface of the channel, so that the control area of the grid electrode on the channel is increased, the control capability of the grid electrode on the channel is increased, and the leakage current of the transistor is reduced, and the short channel effect is restrained.
In some embodiments, the gate 240 has a dimension greater than or equal to the dimension of the channel 230 in a direction parallel to the plane of the substrate 210 when the second portion 242 covers at least a portion of the first side 231a and at least a portion of the second side 231b.
In an example, the top surface width of the isolation structure 220 is equal to the bottom surface width of the isolation structure 220, and thus, the cross section of the channel 230 between two adjacent isolation structures 220 is rectangular, and the gate 240 covers the channel 230, and the size of the gate 240 is larger than the size of the channel 230 in the x-direction.
In another example, the top surface width of the isolation structure 220 is greater than the bottom surface width of the isolation structure 220, and thus, the cross section of the channel 230 between two adjacent isolation structures 220 is trapezoidal, and when the gate 240 completely covers the channel 230, the size of the gate 240 is greater than the size of the channel 230 in the x-direction; when the gate 240 partially covers the channel 230, the size of the gate 240 is equal to the size of the channel 230 in the x-direction.
In other embodiments, the size of gate 240 may be smaller than the size of channel 230 in the x-direction.
In the embodiment of the disclosure, the size of the gate is larger than or equal to the size of the channel by being arranged in the direction parallel to the plane of the substrate, so that the control area of the gate to the channel is increased, the control capability of the gate to the channel is increased, and the leakage current of the transistor is reduced and the short channel effect is restrained.
In some embodiments, the surface of the isolation structure 220 that contacts the second portion 242 has a depression that is directed toward the isolation structure 220 along the second portion 242.
Referring to fig. 3, at least one isolation structure 220 has a recess in which the second portion 242 is located, and by disposing the second portion of the gate in the recess of the isolation structure, the second portion of the gate can be disposed using a space of a portion of the isolation structure, enhancing the gate-to-channel control capability without increasing the size of the transistor.
The surface of the isolation structure 220 in contact with the second portion 242 includes: plane or curved. Here, the recess is located on a side of the isolation structure 220 relatively close to the channel 230. The cross-sectional shape of the recess includes: rectangular, inverted triangular, inverted trapezoidal, etc. The cross-sectional shape of the recess may also be other shapes known in the art, which is not particularly limited in this disclosure.
In some embodiments, the sum of the dimensions of second portion 242 and gate dielectric layer 250 ranges from 10nm to 500nm in a direction parallel to the plane of substrate 210.
In one embodiment, the sum of the dimensions of the second portion 242a and the gate dielectric layer 250 in the x-direction in the recess ranges from 10nm to 500nm.
In another embodiment, the sum of the dimensions of the second portion 242b and the gate dielectric layer 250 in the x-direction in the recess ranges from 10nm to 500nm.
In the embodiment of the disclosure, the sum of the dimensions of the second portion and the gate dielectric layer between the second portion and the first side surface is in the range of 10nm to 500nm, so that the control area of the gate to the channel is increased on the premise of not weakening the isolation function of the isolation structure, and the control capability of the gate to the channel is enhanced.
In some embodiments, the semiconductor structure 200 further comprises: buffer layer 260 is located on substrate 210, buffer layer 260 having a size in the z-direction ranging from 30 angstroms to 150 angstroms. The material of the buffer layer 260 includes silicon oxide, silicon nitride, silicon oxynitride, or the like.
Based on the semiconductor structure, the embodiment of the disclosure also provides a preparation method of the semiconductor structure.
Fig. 4 is a flow chart illustrating a method of fabricating a semiconductor structure according to an embodiment of the present disclosure. Referring to fig. 4, the preparation method at least includes the following steps:
s301: providing a substrate;
s302: forming at least two isolation structures, at least part of which are positioned in the substrate;
s303: forming an active region, wherein the active region is positioned between two adjacent isolation structures and positioned in the substrate; wherein the active region comprises a channel;
s304: forming a grid electrode; wherein the gate includes a first portion and a second portion; the first portion is located over the channel; the second part is positioned between at least one of the two adjacent isolation structures and the channel;
s305: and forming a gate dielectric layer between the gate and the channel.
It should be noted that the steps shown in fig. 4 are not exclusive and that other steps may be performed before, after, or between any of the steps in the illustrated operations; the steps shown in fig. 4 can be sequentially adjusted according to actual requirements.
Fig. 5 a-5 f are schematic views illustrating a process for fabricating a semiconductor structure according to embodiments of the present disclosure. The method for manufacturing the semiconductor structure according to the embodiments of the present disclosure will be described in detail with reference to fig. 4 and 5a to 5 f.
In step S301, as shown with reference to fig. 5a, a substrate 310 is provided. The materials of the substrate 310 include: elemental semiconductor materials (e.g., silicon, germanium), group iii-v compound semiconductor materials, group ii-vi compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. In other embodiments, the substrate 310 may also be silicon-on-insulator or the like.
In step S302, referring to fig. 5f, at least two isolation structures 320 are formed, at least a portion of the isolation structures 320 being located in the substrate 310.
In some embodiments, isolation structures 320 are located entirely within substrate 310, with the surface of isolation structures 320 being flush with the surface of substrate 310.
In other embodiments, a portion of the isolation structure 320 is located in the substrate 310, another portion of the isolation structure 320 protrudes from the surface of the substrate 310, and the protruding portion of the isolation structure 320 has a dimension in a direction perpendicular to the plane of the substrate 310 of 100 to 300 angstroms.
The material of the isolation structure 320 includes a dielectric material, such as at least one of silicon oxide, silicon nitride, or silicon oxynitride. A part of the isolation structure is located in the substrate and another part of the isolation structure is located above the substrate will be described below as an example.
In some embodiments, referring to fig. 5a, the preparation method further includes: forming a buffer layer 360 covering the substrate 310; forming at least two isolation trenches 320a, the isolation trenches 320a penetrating the buffer layer 360 and a portion of the substrate 310; an isolation material layer 320b is formed in the isolation trench 320a.
The buffer layer 360 covering the substrate 310 may be formed using a thin film deposition process, the buffer layer 360 and a portion of the substrate 310 are etched in a direction toward the substrate 310, at least two isolation trenches 320a are formed in the substrate 310, and a dielectric material is filled into the isolation trenches 320a to form an isolation material layer 320b. Here, the isolation material layer 320b is used to form the isolation structure 320 in a subsequent process.
In some embodiments, the above preparation method further comprises: forming a mask layer (not shown) covering the buffer layer 360; the forming at least two isolation trenches 320a includes: the mask layer, the buffer layer 360, and a portion of the substrate 310 are etched in a direction toward the substrate 310, forming at least two isolation trenches 320a. After forming the isolation material layer 320b in the isolation trenches 320a, the mask layer may also be removed, thereby forming the structure shown in fig. 5 a. The mask layer material comprises silicon oxide, silicon nitride or silicon oxynitride, etc. In a specific example, the material of the mask layer may be silicon nitride.
Buffer layer 360 is 30 angstroms to 150 angstroms thick, and the materials of buffer layer 360 include: silicon oxide, silicon nitride, or silicon oxynitride, etc.
The thin film deposition process includes: chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), atomic layer deposition (Atomic Layer Deposition, ALD), or combinations thereof.
The etching process includes any one of dry etching and wet etching or a combination thereof.
In some embodiments, at least two isolation trenches 320a may be etched simultaneously or sequentially; the cross-sectional shapes of the at least two isolation trenches 320a may be the same or different, and the present disclosure is not particularly limited.
In step S303, an active region is formed, the active region being located between two adjacent isolation structures 320 and in the substrate 310; wherein the active region includes a channel 330 as shown in fig. 5 a. The active region includes a source (not shown), a channel 330 and a drain (not shown) disposed in parallel, the channel 330 being located between the source and drain.
Here, the active region may be formed by doping the substrate, and the number of active regions may be one or more, which is not particularly limited by the present disclosure. When the number of active regions is plural, the isolation structure 320 isolates two adjacent active regions.
In some embodiments, the channel 330 includes opposing first and second sides 331a, 331b. Here, the first side 331a is a side of the channel 330 adjacent to one of the two adjacent isolation structures 320, and the second side 331b is a side of the channel 330 adjacent to the other of the two adjacent isolation structures 320.
In step S304, as shown with reference to fig. 5f, a gate 340 is formed; wherein the gate 340 includes a first portion 341 and a second portion 342; first portion 341 is located over channel 330; the second portion 342 is located between at least one of the two adjacent isolation structures 320 and the channel 330.
In an example, the gate 340 includes a first portion 341 and a second portion 342a, where the first portion 341 is located above the channel 330, and the second portion 342a is located between one of the two adjacent isolation structures 320 and the channel 330, so that the control area of the gate 340 on the channel 330 is increased, and the control capability of the gate 340 on the channel 330 is increased, which is beneficial to reducing the leakage current of the transistor and suppressing the short channel effect.
In another example, the gate 340 includes a first portion 341 and a second portion 342b, the first portion 341 is located above the channel 330, and the second portion 342b is located between the other of the two adjacent isolation structures 320 and the channel 330, such that the control area of the gate 340 on the channel 330 is increased, the control capability of the gate 340 on the channel 330 is increased, which is beneficial to reduce the leakage current of the transistor and suppress short channel effects.
In yet another example, the gate 340 includes a first portion 341, a second portion 342a, and a second portion 342b, where the first portion 341 is located above the channel 330, and the second portion 342a and the second portion 342b are located between two adjacent isolation structures 320 and the channel 330, respectively, so that the control area of the gate 340 on the channel 330 is further increased, and the control capability of the gate 340 on the channel 330 is further increased, which is beneficial to further reducing the leakage current of the transistor and suppressing the short channel effect.
It should be noted that the second portion 342a and the second portion 342b each represent the second portion 342, and different reference numerals are only used to distinguish the second portion 342 at different positions, and are not necessarily used to describe a specific order or sequence.
The material of the gate electrode 340 includes a conductive material, for example, at least one of polysilicon, doped polysilicon, titanium nitride, tungsten nitride, tantalum nitride, tungsten, tantalum, platinum, titanium, or aluminum. In some embodiments, gate 340 may be a single layer film. In other embodiments, gate 340 may be a composite film of multiple layers.
In some embodiments, still referring to fig. 5f, step S304 includes: forming a second portion 342a covering at least a portion of the first side 331a; and/or forming a second portion 342b that covers at least a portion of the second side 331b.
In one example, as shown in connection with fig. 5f, a second portion 342a is formed covering at least a portion of the first side 331a, the second portion 342a being located between the isolation structure 320 and the first side 331 a. Here, the second portion 342a may partially cover the first side 331a or may entirely cover the first side 331a, and when the area of the second portion 342a covering the first side 331a increases, the control capability of the gate 340 on the channel 330 increases.
In another example, as shown in connection with fig. 5f, a second portion 342b is formed covering at least a portion of the second side 331b, the second portion 342b being located between the isolation structure 320 and the second side 331b. Here, the second portion 342b may partially cover the second side 331b or may entirely cover the second side 331b, and when an area of the second portion 342b covering the second side 331b increases, the control capability of the gate 340 with respect to the channel 330 increases.
In yet another example, the second portion 342a is formed to cover at least a portion of the first side 331a and the second portion 342b is formed to cover at least a portion of the second side 331b, the second portion 342a being located between the isolation structure 320 and the first side 331a, the second portion 342b being located between the isolation structure 320 and the second side 331b. Here, the second portion 342a may partially or completely cover the first side 331a; and/or the second portion 342b may partially or completely cover the second side 331b, as the area of the second portion 342a covering the first side 331a and the second portion 342b covering the second side 331b further increases, the control of the gate 340 over the channel 330 further increases.
In some embodiments, referring to fig. 5c to 5f, the step S304 includes: etching portions of at least one of the adjacent two isolation material layers 320b in a direction toward the substrate 310 to form a groove 370; wherein the remaining isolation material layer constitutes an isolation structure 320; the recess 370 is located between the isolation structure 320 and the channel 330; the second portion 342 is formed in the recess 370.
Here, at least one of the two isolation material layers 320b shown in fig. 5c may be etched to form the groove 370, which is not particularly limited in the present disclosure. In one embodiment, both adjacent isolation material layers 320b may be etched, and corresponding grooves 370 may be formed in each of the two isolation material layers 320b, as shown in fig. 5 d.
In some embodiments, the etching process includes: and (5) wet etching. In one embodiment, referring to fig. 5c, a wet etching solution may be used to etch away a portion of the isolation material layer 320b, forming a recess 370, as shown in fig. 5 d. The wet etching solution is a solution having a higher selectivity to the isolation structures 320. In this example, isolation structure 320 is silicon oxide and the wet etching solution is hydrofluoric acid. In other examples, isolation structures 320 may also be other materials, and the wet etch solution may also be other solutions.
In some embodiments, referring to fig. 5b and 5c, the method further comprises, prior to forming the groove 370: forming a photoresist layer 380 covering the buffer layer 360 and the isolation material layer 320 b; forming an opening in the photoresist layer 380; wherein the opening reveals portions of at least one of buffer layer 360 and two adjacent isolation material layers 320b covering channel 330; doping treatment is performed on the exposed buffer layer 360 and isolation material layer 320b.
Here, the photoresist layer 380 may be formed through a photoresist coating process, including but not limited to a spin coating process; an opening may be formed in the photoresist layer 380 through an exposure and development process, the opening being used to form a recess in a subsequent process. The material of the photoresist layer 380 includes at least one of a light shielding material, a polymer material, a polymerizable monomer, a dispersing agent, and a photoinitiator.
Note that when only one of the adjacent two isolation material layers 320b is etched, the other isolation material layer 320b that is not etched is covered with the photoresist layer 380.
In the embodiment of the disclosure, shallow doping of a channel can be realized by executing doping treatment, so that the control voltage of the grid electrode of the transistor is regulated and controlled, and the leakage current of the transistor is reduced.
In some embodiments, the doping treated ions comprise: the N-type dopant ions, for example, at least one of arsenic ions, phosphorus ions, or nitrogen ions. In other embodiments, the doping treated ions may also be P-type dopant ions.
In some embodiments, the dimension of the opening-exposed isolation material layer 320b in a direction parallel to the plane of the substrate 310 ranges from 10nm to 500nm. Here, the dimensions include the length and/or width of the spacer material layer 320b.
It should be noted that, the oversized isolation material layer 320b exposed by the opening may cause the isolation material layer 320b to be removed too much during the subsequent etching to form the recess, so that the isolation performance of the finally formed isolation structure 320 is degraded. In the embodiment of the disclosure, the size range of the isolation material layer exposed by the opening is 10nm to 500nm, so that the second part of the grid can be arranged by utilizing the space of part of the isolation structure while the isolation performance of the isolation structure is ensured, and the control capability of the grid on the channel is improved.
In step S305, as shown with reference to fig. 5e and 5f, a gate dielectric layer 350 is formed between the gate 340 and the channel 330. The materials of gate dielectric layer 350 include: silicon oxide, silicon nitride, or silicon oxynitride, etc. For example, after forming the recess 370, the gate dielectric layer 350 is formed, as shown in fig. 5 e.
In some embodiments, the forming the gate dielectric layer 350 includes: forming a first sub-gate dielectric layer covering the exposed channel 330; forming a second sub-gate dielectric layer covering the first sub-gate dielectric layer; the first sub-gate dielectric layer is located between the channel 330 and the second sub-gate dielectric layer, and the second sub-gate dielectric layer is located between the first sub-gate dielectric layer and the gate 340. Here, the forming process of the first sub-gate dielectric layer includes: a thin film deposition process or a thermal oxidation process, for example, a thermal oxidation process may be performed on the exposed channel 330 to form a first sub-gate dielectric layer; the forming process of the second sub-gate dielectric layer comprises the following steps: thin film deposition process.
In this example, the gate dielectric layer 350 includes a composite film layer formed by the first sub-gate dielectric layer and the second sub-gate dielectric layer. In other examples, gate dielectric layer 350 may be a single layer film, depending on the actual process requirements.
In some embodiments, the surface of isolation structure 320 in contact with second portion 342 comprises: plane or curved. Here, the groove 370 is located at a side of the isolation structure 320 relatively close to the channel 330, and a sectional shape of the groove 370 includes: rectangular, inverted triangular, inverted trapezoidal, etc. The cross-sectional shape of the groove 370 may also be other shapes known in the art, which is not particularly limited in this disclosure.
Based on the above semiconductor structure, the embodiments of the present disclosure further provide a semiconductor device, including:
a semiconductor structure 200 as described in any of the embodiments;
a pixel array coupled to the semiconductor structure 200, comprising: at least one pixel cell.
In some embodiments, the semiconductor device includes an image sensor.
In some embodiments, the semiconductor device further includes a gain block, a reset block, a select block, and a floating diffusion. The gain block controls the gain of the pixels by implementing dual conversion gain or the like, the reset block may selectively reset the pixel components, the selection block may support selecting signals of the pixels from the pixel array in response to control signals or the like received via the bus, the semiconductor structure 200 may support converting the output from the pixel array into electrical signals indicative of optical information detected by the pixel array, and the floating diffusion may be used to accumulate charge.
The semiconductor device provided by the embodiment of the disclosure comprises the semiconductor structure, so that the noise of the semiconductor device is reduced, the area of the pixel array is not sacrificed, and the full well capacity of the semiconductor device is ensured.
In addition, the semiconductor structure provided by the embodiment of the disclosure increases the control area of the grid electrode to the channel, so that the performance of the semiconductor structure is improved, and the area of the semiconductor structure can be further reduced, thereby creating space for increasing the area of the pixel array.
In addition, the semiconductor device provided by the embodiment of the disclosure can be formed without adding an extra photoresist, so that the performance of the semiconductor device is improved without increasing the production cost.
The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it should be covered in the protection scope of the disclosure.

Claims (12)

1. A method of fabricating a semiconductor structure, comprising:
providing a substrate;
forming a buffer layer covering the substrate;
forming at least two isolation structures, wherein the isolation structures penetrate through the buffer layer and part of the substrate;
forming an active region, wherein the active region is positioned between two adjacent isolation structures and positioned in the substrate; wherein the active region comprises a channel;
forming a photoresist layer covering the buffer layer and the isolation structure;
forming an opening in the photoresist layer; wherein the opening exposes a portion of at least one of the buffer layer and two adjacent isolation structures covering the channel;
performing doping treatment on the exposed buffer layer and the isolation structure;
forming a grid electrode; wherein the gate includes a first portion and a second portion; the first portion is located over the channel; the second portion is located between at least one of the two adjacent isolation structures and the channel;
and forming a gate dielectric layer between the gate and the channel.
2. The method of manufacturing of claim 1, wherein the channel comprises opposing first and second sides;
the forming the gate includes:
forming said second portion overlying at least a portion of said first side; and/or forming said second portion covering at least part of said second side.
3. The process according to claim 1 or 2, wherein,
the forming the gate includes:
etching a part of at least one of the two adjacent isolation structures along the direction facing the substrate to form a groove; wherein the groove is positioned between the rest of the isolation structure and the channel;
the second portion is formed in the recess.
4. A method of preparing as claimed in claim 3, wherein the doping treated ions comprise: at least one of arsenic ions, phosphorus ions, or nitrogen ions.
5. A method of manufacturing as claimed in claim 3, wherein the etching process comprises: and (5) wet etching.
6. A semiconductor structure prepared by the method of any one of claims 1 to 5; the semiconductor structure includes:
a substrate;
at least two isolation structures, at least a portion of which are located in the substrate;
an active region located between two adjacent isolation structures and in the substrate, comprising: a channel; the width of the top surface of the channel between two adjacent isolation structures is smaller than that of the bottom surface of the channel;
a gate electrode, comprising: a first portion and a second portion; wherein the first portion is located over the channel; the second portion is located between at least one of the two adjacent isolation structures and the channel; the size of the grid electrode is equal to the size of the channel along the direction parallel to the plane of the substrate;
and the gate dielectric layer is positioned between the gate and the channel.
7. The semiconductor structure of claim 6, wherein the channel comprises opposing first and second sides;
the second portion covers at least a portion of the first side; and/or, the second portion covers at least part of the second side.
8. The semiconductor structure of claim 7, wherein a dimension of the gate is greater than or equal to a dimension of the channel in a direction parallel to a plane in which the substrate lies when the second portion covers at least a portion of the first side and at least a portion of the second side.
9. The semiconductor structure of claim 6, wherein a surface of the isolation structure in contact with the second portion has a recess directed toward the isolation structure along the second portion.
10. The semiconductor structure of claim 6, wherein a sum of dimensions of the second portion and the gate dielectric layer along a direction parallel to a plane in which the substrate lies is in a range of 10nm to 500nm.
11. A semiconductor device, comprising:
the semiconductor structure of any one of claims 6 to 10;
a pixel array coupled with the semiconductor structure, comprising: at least one pixel cell.
12. The semiconductor device according to claim 11, wherein the semiconductor device comprises an image sensor.
CN202310681725.0A 2023-06-09 2023-06-09 Semiconductor structure, preparation method thereof and semiconductor device Active CN116435324B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310681725.0A CN116435324B (en) 2023-06-09 2023-06-09 Semiconductor structure, preparation method thereof and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310681725.0A CN116435324B (en) 2023-06-09 2023-06-09 Semiconductor structure, preparation method thereof and semiconductor device

Publications (2)

Publication Number Publication Date
CN116435324A CN116435324A (en) 2023-07-14
CN116435324B true CN116435324B (en) 2023-09-26

Family

ID=87094700

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310681725.0A Active CN116435324B (en) 2023-06-09 2023-06-09 Semiconductor structure, preparation method thereof and semiconductor device

Country Status (1)

Country Link
CN (1) CN116435324B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1812112A (en) * 2004-10-20 2006-08-02 三星电子株式会社 Solid image sensor device with nonplanar transistor and manufacture method thereof
CN103515437A (en) * 2012-06-14 2014-01-15 台湾积体电路制造股份有限公司 Structure and method for a field effect transistor
CN109786436A (en) * 2017-11-14 2019-05-21 台湾积体电路制造股份有限公司 Integrated chip and forming method thereof
CN113383427A (en) * 2019-03-14 2021-09-10 索尼半导体解决方案公司 Semiconductor element, semiconductor device, and methods for manufacturing semiconductor element and semiconductor device
CN113892169A (en) * 2021-08-31 2022-01-04 长江存储科技有限责任公司 Manufacturing method of semiconductor device and semiconductor device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002151688A (en) * 2000-08-28 2002-05-24 Mitsubishi Electric Corp Mos type semiconductor device and manufacturing method thereof
US6909186B2 (en) * 2003-05-01 2005-06-21 International Business Machines Corporation High performance FET devices and methods therefor
US7915691B2 (en) * 2007-10-30 2011-03-29 International Business Machines Corporation High density SRAM cell with hybrid devices
US7960286B2 (en) * 2009-06-17 2011-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Narrow channel width effect modification in a shallow trench isolation device
US11626433B2 (en) * 2020-03-25 2023-04-11 Omnivision Technologies, Inc. Transistors having increased effective channel width

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1812112A (en) * 2004-10-20 2006-08-02 三星电子株式会社 Solid image sensor device with nonplanar transistor and manufacture method thereof
CN103515437A (en) * 2012-06-14 2014-01-15 台湾积体电路制造股份有限公司 Structure and method for a field effect transistor
CN109786436A (en) * 2017-11-14 2019-05-21 台湾积体电路制造股份有限公司 Integrated chip and forming method thereof
CN113383427A (en) * 2019-03-14 2021-09-10 索尼半导体解决方案公司 Semiconductor element, semiconductor device, and methods for manufacturing semiconductor element and semiconductor device
CN113892169A (en) * 2021-08-31 2022-01-04 长江存储科技有限责任公司 Manufacturing method of semiconductor device and semiconductor device

Also Published As

Publication number Publication date
CN116435324A (en) 2023-07-14

Similar Documents

Publication Publication Date Title
US6483158B1 (en) Semiconductor memory device and fabrication method therefor
JP4444596B2 (en) Method for manufacturing hybrid element isolation structure of image sensor
US20060276014A1 (en) Self-aligned high-energy implantation for deep junction structure
US20020111025A1 (en) Modified gate processing for optimized difinition of array and logic devices on same chip
US7518175B2 (en) Semiconductor memory device and method for fabricating the same
US7118956B2 (en) Trench capacitor and a method for manufacturing the same
US5221852A (en) Charge coupled device and method of producing the same
US6410377B1 (en) Method for integrating CMOS sensor and high voltage device
US6339237B1 (en) Semiconductor device having a memory cell region and peripheral circuit region and method of manufacturing the same
CN116435324B (en) Semiconductor structure, preparation method thereof and semiconductor device
US20070077678A1 (en) Method of fabricating image sensors
KR20080061476A (en) Method of manufacturing a non volatile memory device
CN111916399B (en) Preparation method of semiconductor device and semiconductor device
CN211929495U (en) Grid structure
US5593928A (en) Method of making a semiconductor device having floating source and drain regions
US20020013016A1 (en) Method for fabricating semiconductor device
US7157318B2 (en) Method of fabricating SRAM device
CN117525117B (en) Transistor device and method for manufacturing the same
CN113972257B (en) Semiconductor structure and forming method thereof
CN113284953B (en) Shielding gate groove type MOSFET structure and manufacturing method thereof
KR100575617B1 (en) Drain forming method of semiconductor device
KR100951573B1 (en) Semiconductor device and method for fabricating the same
KR100609999B1 (en) method for manufacturing semiconductor devices
CN115842051A (en) Semiconductor device and manufacturing method thereof
KR0132507B1 (en) Semiconductor device and its manufacturing method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant