CN116414174A - Band gap reference circuit, starting circuit and starting method thereof - Google Patents

Band gap reference circuit, starting circuit and starting method thereof Download PDF

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Publication number
CN116414174A
CN116414174A CN202310594122.7A CN202310594122A CN116414174A CN 116414174 A CN116414174 A CN 116414174A CN 202310594122 A CN202310594122 A CN 202310594122A CN 116414174 A CN116414174 A CN 116414174A
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control module
band gap
reference source
starting
circuit
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CN116414174B (en
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吴硕硕
高专
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Core Microelectronics Technology Zhuhai Co ltd
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Core Microelectronics Technology Zhuhai Co ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
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  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

The invention discloses a band gap reference circuit, a starting circuit and a starting method thereof. The band gap reference circuit comprises a band gap reference source and a starting circuit; the starting circuit comprises a first control module, a second control module and a feedback module; the first control module is used for pulling up the potential of the starting end of the band gap reference source when the control voltage PD is at a first level; the second control module is used for pulling the starting end potential of the band gap reference source low when the control voltage PD is at a second level; the feedback module is used for turning off the starting circuit after the band gap reference source is started. According to the invention, the first control module and the second control module are respectively controlled by the external control voltage PD, so that the starting end voltage of the band gap reference source is adjusted, the problem of degeneracy point of the band gap reference source when zero current is generated is avoided, the band gap reference source is normally started, the second control module is automatically disconnected after the band gap reference source is normally started by the feedback module, and the band gap reference source is further normally operated to reach a desired stable working point.

Description

Band gap reference circuit, starting circuit and starting method thereof
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a band gap reference circuit, a starting circuit and a starting method thereof.
Background
Bandgap reference circuits are widely used in integrated circuits to provide a reference voltage that does not vary with temperature and supply voltage. The starting problem of a general low-voltage band-gap reference source circuit is that a plurality of degeneracy points exist, and the whole circuit can generate a zero-current state, which is undesirable, so that the starting circuit is needed to avoid the phenomenon.
Disclosure of Invention
Aiming at the defects or improvement demands of the prior art, the invention provides a band gap reference circuit, a starting circuit and a starting method thereof, which can effectively avoid the problem of degeneracy point of a band gap reference source when zero current is generated, so that the band gap reference source is normally started to reach expected stable working points.
To achieve the above object, according to one aspect of the present invention, there is provided a bandgap reference circuit including a bandgap reference source and a start-up circuit; the starting circuit comprises a first control module, a second control module and a feedback module; the first control module is used for pulling up the potential of the starting end of the band gap reference source when the control voltage PD is at a first level; the second control module is used for pulling the starting end potential of the band gap reference source low when the control voltage PD is at a second level; the feedback module is used for after the band gap reference source is started, the start-up circuit is turned off.
In some embodiments, the first end of the first control module is used for connecting with a power supply, the second end of the first control module is used for acquiring the control voltage PD, and the third end of the first control module is connected with the first end of the second control module, the input end of the feedback module and the starting end of the band gap reference source; the second end of the second control module is used for acquiring the control voltage PD, the third end of the control module is used for being grounded, and the fourth end of the control module is connected with the output end of the feedback module.
In some embodiments, when the control voltage PD is at the first level, the first control module is turned on, the second control module is turned off, the starting end potential of the bandgap reference source is pulled up to the power supply voltage, and the bandgap reference source is not started; when the control voltage PD is at a second level, the first control module is turned off, the second control module is turned on, the potential of the starting end of the band gap reference source is pulled down to the ground, and the band gap reference source is started; after the band gap reference source is started, the feedback module pulls the fourth end level of the second control module down to the ground, so that the second control module is turned off.
In some embodiments, the first control module includes a PMOS transistor M2, a source of the PMOS transistor M2 forms a first end of the first control module, a gate of the PMOS transistor M2 forms a second end of the first control module, and a drain of the PMOS transistor M2 forms a third end of the first control module.
In some embodiments, the second control module includes an NMOS transistor NM0 and an NMOS transistor NM1, where a drain of the NMOS transistor NM0 forms a first end of the second control module, a source of the NMOS transistor NM0 is connected to a drain of the NMOS transistor NM1, a gate of the NMOS transistor NM0 forms a second end of the second control module, a source of the NMOS transistor NM1 forms a third end of the second control module, and a gate of the NMOS transistor NM1 forms a fourth end of the second control module.
In some implementations, the feedback module includes a first inverter and a second inverter; the input end of the first inverter forms the input end of the feedback module, the output end of the first inverter is connected with the input end of the second inverter, and the output end of the second inverter forms the output end of the feedback module.
In some embodiments, the first inverter includes a PMOS transistor M3 and an NMOS transistor NM3; the grid electrode of the PMOS tube M3 is connected with the grid electrode of the NMOS tube NM3 to form the input end of the first inverter; the drain electrode of the PMOS tube M3 is connected with the drain electrode of the NMOS tube NM3 to form the output end of the first inverter; the source electrode of the PMOS tube M3 is used for being connected with a power supply, and the source electrode of the NMOS tube NM3 is used for being grounded.
In some embodiments, the first inverter includes a PMOS transistor M3 and a resistor R1; the grid electrode of the PMOS tube M3 forms the input end of the first inverter; the drain electrode of the PMOS tube M3 is connected with the first end of the resistor R1 to form the output end of the first inverter; the source of the PMOS tube M3 is used for being connected with a power supply, and the second end of the resistor R1 is used for being grounded.
In some embodiments, the second inverter includes a PMOS transistor M4, a PMOS transistor M5, a PMOS transistor M6, and an NMOS transistor NM2; the grid electrode of the PMOS tube M4 is connected with the grid electrode of the PMOS tube M5, the grid electrode of the PMOS tube M6 and the grid electrode of the NMOS tube NM2 to form the input end of the second inverter; the drain electrode of the PMOS tube M4 is connected with the source electrode of the PMOS tube M5, the drain electrode of the PMOS tube M5 is connected with the source electrode of the PMOS tube M6, and the drain electrode of the PMOS tube M6 is connected with the drain electrode of the NMOS tube NM2 to form the output end of the second inverter; the source of the PMOS tube M4 is used for connecting a power supply, and the source of the NMOS tube NM2 is used for grounding.
In some embodiments, the bandgap reference source includes a PMOS transistor M0, a PMOS transistor M1, a resistor R0, a bipolar transistor T1, a bipolar transistor T2, and an operational amplifier a; the source electrode of the PMOS tube M0 and the source electrode of the PMOS tube M1 are used for being connected with a power supply, the drain electrode of the PMOS tube M0 is connected with the emitter electrode of the bipolar transistor T1, the drain electrode of the PMOS tube M1 is connected with the first end of a resistor R0, the second end of the resistor R0 is connected with the emitter electrode of the bipolar transistor T2, and the base electrode and the collector electrode of the bipolar transistor T1 and the base electrode and the collector electrode of the bipolar transistor T2 are used for being grounded; the reverse input end of the operational amplifier A is connected with the common end of the PMOS tube M0 and the bipolar transistor T1, the forward input end of the operational amplifier A is connected with the common end of the PMOS tube M1 and the resistor R0, and the output end of the operational amplifier A is connected with the grid electrode of the PMOS tube M0 and the grid electrode of the PMOS tube M1 to form the starting end of the band gap reference source.
According to another aspect of the present invention, there is provided a start-up circuit comprising a first control module, a second control module and a feedback module; the first control module is used for pulling up the potential of the starting end of the band gap reference source when the control voltage PD is at a first level; the second control module is used for pulling the starting end potential of the band gap reference source low when the control voltage PD is at a second level; the feedback module is used for turning off the starting circuit after the band gap reference source is started.
In some embodiments, when the control voltage PD is at the first level, the first control module is turned on, the second control module is turned off, the starting end potential of the bandgap reference source is pulled up to the power supply voltage, and the bandgap reference source is not started; when the control voltage PD is at a second level, the first control module is turned off, the second control module is turned on, the potential of the starting end of the band gap reference source is pulled down to the ground, and the band gap reference source is started; after the band gap reference source is started, the feedback module enables the second control module to be automatically turned off.
According to another aspect of the present invention, there is provided a method of starting a bandgap reference circuit, the bandgap reference circuit comprising a bandgap reference source and a starting circuit, the starting circuit comprising a first control module, a second control module and a feedback module, the method comprising:
the control voltage PD is made to be a first level, the first control module is utilized to pull up the potential of the starting end of the band gap reference source under the action of the control voltage PD, and the starting circuit is marked to be in an S0 state at the moment;
the control voltage PD is made to be a second level, the second control module is utilized to pull the potential of the starting end of the band gap reference source down under the action of the control voltage PD, and the starting circuit is marked to be in an S1 state at the moment;
the level of the control voltage PD is kept unchanged, and the starting circuit is turned off by using the feedback module to mark that the starting circuit is in an S2 state at the moment;
the S0 state, the S1 state, and the S2 state are different from each other.
In general, the above technical solutions conceived by the present invention have the following beneficial effects compared with the prior art: the starting circuit is connected with the starting end of the band gap reference source, the first control module and the second control module in the starting circuit are respectively controlled through the external control voltage PD, the starting end voltage of the band gap reference source is adjusted, the problem of degeneracy point of the band gap reference source during zero current is avoided, the band gap reference source is enabled to be normally started, the second control module is enabled to be automatically disconnected after the band gap reference source is normally started through the feedback module, and then the band gap reference source is enabled to normally work, and a desired stable working point is achieved.
Drawings
FIG. 1 is a schematic diagram of a bandgap reference circuit;
FIG. 2 is a schematic diagram of a bandgap reference circuit according to one embodiment of the invention;
FIG. 3 is a schematic diagram of a bandgap reference circuit according to another embodiment of the invention;
FIG. 4 is a schematic diagram of a bandgap reference circuit according to yet another embodiment of the invention;
fig. 5 is a flowchart of a starting method of the bandgap reference circuit according to an embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. As will be recognized by those of skill in the pertinent art, the described embodiments may be modified in various different ways without departing from the spirit or scope of the present application. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.
The bandgap reference circuit shown in fig. 1 includes a bandgap reference source 101 and a start-up circuit 103.
The bandgap reference source 101 comprises a first current path and a second current path, the first current path comprises a first bipolar transistor T1 and a first PMOS tube M0, the second current path comprises a second bipolar transistor T2, a first resistor R0 and a second PMOS tube M1, a common end of the first bipolar transistor T1 and the first PMOS tube M0 is connected with an inverted input end of the operational amplifier A, and a common end of the second PMOS tube M1 and the first resistor R0 is connected with a same-direction input end of the operational amplifier A. The emitter area of the second bipolar transistor T2 is n times the emitter area of the first bipolar transistor T1, and n is greater than 1.
The starting circuit 103 includes a third PMOS transistor M2, a second resistor R1, and a capacitor C1.
The starting principle of the band gap reference circuit is as follows: when the power supply voltage is increased from 0 to VDD, the initial state of the gate voltage of the third PMOS transistor M2 is low, and at this time, the third PMOS transistor M2 will pull the gate voltages of the first PMOS transistor M0 and the second PMOS transistor M1 to low, the PMOS transistor M0 and the PMOS transistor M1 are turned on, and both the first current path and the second current path will have current; along with the continuous charging of the capacitor C1 by VDD, the voltage on the capacitor C1 will reach VDD, so that the third PMOS transistor M2 is turned off, and the starting process is ended.
However, the bandgap reference circuit has a state in which the respective branch currents are 0, that is, a state in which both the current of the first current path and the current of the second current path of the bandgap reference source 101 in fig. 1 are 0. Specifically, when the power supply voltage is slowly increased from 0 to VDD, the voltage on the capacitor C1 will follow the power supply change, so that the third PMOS transistor M2 will not be turned on all the time, and the start-up circuit will fail.
As shown in fig. 2, the bandgap reference circuit of the embodiment of the invention includes a bandgap reference source 101 and a start-up circuit 201. The start-up circuit 201 is used to provide a start-up voltage for the bandgap reference source 101.
In the band gap reference source 101, a source electrode of a first PMOS tube M0 and a source electrode of a second PMOS tube M1 are used for connecting a power supply, a grid electrode of the first PMOS tube M0 is connected with a grid electrode of the second PMOS tube M1, a drain electrode of the first PMOS tube M0 is connected with an emitter electrode of a first bipolar transistor T1, a drain electrode of the second PMOS tube M1 is connected with a first end of a first resistor R0, a second end of the first resistor R0 is connected with an emitter electrode of a second bipolar transistor T2, and a base electrode and a collector electrode of the first bipolar transistor T1 and a base electrode and a collector electrode of the second bipolar transistor T2 are used for grounding; the reverse input end of the operational amplifier A is connected with the common end of the first PMOS tube M0 and the first bipolar transistor T1, the forward input end of the operational amplifier A is connected with the common end of the second PMOS tube M1 and the first resistor R0, and the output end of the operational amplifier A is connected with the grid electrode of the first PMOS tube M0 and the grid electrode of the second PMOS tube M1 to form the starting end of the band gap reference source 101.
The start-up circuit 201 includes a first control module 2011, a second control module 2013, and a feedback module 2015. The first end of the first control module 2011 is used for being connected with a power supply, the second end of the first control module 2011 is used for obtaining a control voltage PD, and the third end of the first control module 2011 is connected with the first end of the second control module 2013, the input end of the feedback module 2015 and the starting end of the band gap reference source 101; a second end of the second control module 2013 is used for acquiring the control voltage PD, a third end of the control module 2013 is used for grounding, and a fourth end of the control module 2013 is connected to an output end of the feedback module 2015.
The first control module 2011 is configured to pull up the start-up terminal potential of the bandgap reference source 101 to the supply voltage when the control voltage PD is at a first level; the second control module 2013 is configured to pull the voltage at the start end of the bandgap reference source 101 down to ground when the control voltage PD is at the second level, so as to start the bandgap reference source 101; the feedback module 2015 is configured to pull the fourth terminal level of the second control module 2013 low to ground after the bandgap reference source 101 is started, so as to turn off the second control module 2013.
Specifically, when the power supply reaches the normal voltage VDD, the initial state of the control voltage PD is 0, at this time, the first control module 2011 is turned on, the second control module 2013 is turned off, the voltage at the start end of the bandgap reference source 101 is pulled up to VDD, and the current in the bandgap reference source 101 is 0. At this time, only the control voltage PD needs to be changed to a high level (e.g., VDD), the first control module 2011 is turned off, the second control module 2013 is turned on, the starting end potential of the bandgap reference source 101 is pulled down to ground, and the first bipolar transistor T1 and the second bipolar transistor T2 have current passing through, so that the bandgap reference source 101 is started, and the degeneracy point of zero current of the triode is avoided. After the bandgap reference source 101 is started, the feedback module 2015 pulls the fourth terminal level Vstar of the second control module 2013 down to ground, so that the second control module 2013 is turned off, and the bandgap reference source 101 will work normally.
In some implementations, the feedback module 2015 includes a first inverter and a second inverter. The input end of the first inverter forms the input end of the feedback module, the output end of the first inverter is connected with the input end of the second inverter, and the output end of the second inverter forms the output end of the feedback module.
In some embodiments, the bandgap reference source 101 further comprises other elements, and the bandgap reference source 101 is configured to form a reference voltage source or a reference current source.
Fig. 3 is a schematic diagram of a bandgap reference circuit according to another embodiment of the invention, in which the start-up circuit 201 in fig. 2 is implemented as the start-up circuit 301 in fig. 3.
As shown in fig. 3, the first control module includes a third PMOS transistor M2, a source of the third PMOS transistor M2 forms a first end of the first control module, a gate of the third PMOS transistor M2 forms a second end of the first control module, and a drain of the third PMOS transistor M2 forms a third end of the first control module. The second control module comprises a first NMOS tube NM0 and a second NMOS tube NM1, wherein the drain electrode of the first NMOS tube NM0 forms the first end of the second control module, the source electrode of the first NMOS tube NM0 is connected with the drain electrode of the second NMOS tube NM1, the grid electrode of the first NMOS tube NM0 forms the second end of the second control module, the source electrode of the second NMOS tube NM1 forms the third end of the second control module, the grid electrode of the second NMOS tube NM1 forms the fourth end of the second control module, and the level mark is Vstar.
The first inverter comprises a fourth PMOS tube M3 and a fourth NMOS tube NM3, and the grid electrode of the fourth PMOS tube M3 is connected with the grid electrode of the fourth NMOS tube NM3 to form the input end of the first inverter; the drain electrode of the fourth PMOS tube M3 is connected with the drain electrode of the fourth NMOS tube NM3 to form the output end of the first inverter; the source electrode of the fourth PMOS tube M3 is used for being connected with a power supply, and the source electrode of the fourth NMOS tube NM3 is used for being grounded. The second inverter comprises a fifth PMOS tube M4, a sixth PMOS tube M5, a seventh PMOS tube M6 and a third NMOS tube NM2. The grid electrode of the fifth PMOS tube M4 is connected with the grid electrode of the sixth PMOS tube M5, the grid electrode of the seventh PMOS tube M6 and the grid electrode of the third NMOS tube NM2 to form the input end of the second inverter; the drain electrode of the fifth PMOS tube M4 is connected with the source electrode of the sixth PMOS tube M5, the drain electrode of the sixth PMOS tube M5 is connected with the source electrode of the seventh PMOS tube M6, the drain electrode of the seventh PMOS tube M6 is connected with the drain electrode of the third NMOS tube NM2 to form the output end of the second inverter, and the level mark is Vstar; the source electrode of the fifth PMOS tube M4 is used for connecting a power supply, and the source electrode of the third NMOS tube NM2 is used for being grounded.
The operating states of the start-up circuit of the bandgap reference circuit are shown in the following table:
S0 S1 S2
PD 0 1 1
Vstar 1 1 0
the starting principle of the bandgap reference circuit shown in fig. 3 is as follows in combination with the operating state table of the starting circuit of the bandgap reference circuit.
When the power supply reaches the normal voltage VDD, the initial state of the control voltage PD is 0, the current flowing through the first PMOS transistor M0 and the second PMOS transistor M1 is 0, the drain voltages of the first PMOS transistor M0 and the second PMOS transistor M1 are both 0, and the gate voltages of the first PMOS transistor M0 and the second PMOS transistor M1 are both VDD, i.e., the start-up circuit 301 is in the S0 state in the operating state table.
At this time, only the control voltage PD needs to be changed to a high level (e.g., VDD), both the first NMOS transistor NM0 and the second NMOS transistor NM1 will be turned on, so that the gate voltages of the first PMOS transistor M0 and the second PMOS transistor M1 are pulled down, the first PMOS transistor M0 and the second PMOS transistor M1 are turned on, the current flowing through the first bipolar transistor T1 and the second bipolar transistor T2 will be non-zero, and the degenerated point of the zero current of the triode is avoided, that is, the starting circuit 301 is in the S1 state in the operating state table.
After the bandgap reference circuit is started, the gate voltages of the fourth PMOS transistor M3 and the fourth NMOS transistor NM3 are also pulled down, at this time, the drain voltages of the fourth PMOS transistor M3 and the fourth NMOS transistor NM3 are pulled up, correspondingly, the gate voltages of the fifth PMOS transistor M4, the sixth PMOS transistor M5, the seventh PMOS transistor M6 and the third NMOS transistor NM2 are changed from low level to high level, then the voltage Vstar is pulled down, the second NMOS transistor NM1 is turned off, the starting circuit 301 stops working, and the bandgap reference circuit will work normally, i.e. the starting circuit is in the S2 state in the working state table.
As can be seen from the above working principle, the starting circuit 301 is automatically hopped from the S1 state to the S2 state, and is not controlled by external voltage.
Fig. 4 is a schematic diagram of a bandgap reference circuit according to another embodiment of the invention, in which the start-up circuit 201 in fig. 2 is implemented as the start-up circuit 501 in fig. 4.
Compared to the start-up circuit 301, the start-up circuit 501 replaces the fourth NMOS transistor NM3 in the first inverter with the second resistor R1. As shown in fig. 4, a first end of the second resistor R1 is connected to the drain of the fourth PMOS transistor M3, that is, the first end of the second resistor R1 is connected to the common source amplifier formed by the fourth PMOS transistor M3, a second end of the second resistor R1 is connected to ground, the gate of the fourth PMOS transistor M3 forms an input end of the first inverter, and the first end of the second resistor R1 forms an output end of the first inverter. The fourth PMOS transistor M3 and the second resistor R1 together implement a logic function substantially identical to that of the inverter formed by the fourth PMOS transistor M3 and the fourth NMOS transistor NM3, and all invert the gate voltage of the fourth PMOS transistor M3.
The working principle of the bandgap reference circuit is identical to that of the bandgap reference circuit shown in fig. 2, and thus, a detailed description thereof is omitted.
In some embodiments, the number of PMOS transistors and the number of NMOS transistors in the second inverter may be selected according to actual needs. For example, the total of three PMOS transistors of the fifth PMOS transistor M4, the sixth PMOS transistor M5 and the seventh PMOS transistor M6 can be reduced to a single PMOS transistor; an NMOS transistor may be added between the third NMOS transistor NM2 and ground, and gates of all the NMOS transistors are connected to form an input terminal of the second inverter.
In addition, as shown in fig. 5, the embodiment of the present invention further provides a method for starting the bandgap reference circuit, including:
step S601: the power supply voltage is brought to the normal voltage VDD.
Step S603: the control voltage PD is set to a first level (e.g., 0), and the first control module is used to pull up the start-up terminal potential of the bandgap reference source (e.g., VDD) under the action of the control voltage PD (e.g., turn on the first control module), so as to mark that the start-up circuit is in S0 state.
In some embodiments, the second control module is turned off when the start-up circuit is in the S0 state, and the current in the bandgap reference source is 0.
Step S605: and the control voltage PD is set to a second level (such as VDD), and the second control module is utilized to pull the potential of the starting end of the band gap reference source low (such as 0) under the action of the control voltage PD (such as the conduction of the second control module), so that the starting circuit is in an S1 state at the moment.
In some embodiments, when the starting circuit is in the S1 state, the first control module is turned off, the bandgap reference source is started, and current passes through the bandgap reference source, so that degeneracy of zero current of the triode in the bandgap reference source is avoided.
Step S607: the level of the control voltage PD is kept unchanged, and the starting circuit is turned off by the feedback module to mark that the starting circuit is in the S2 state at the moment.
In some embodiments, when the starting circuit is in the S1 state, the level of the control voltage PD is kept unchanged, and the feedback module feeds back the voltage Vstar to the second control module, so that the second control module is automatically turned off, and further the starting circuit is automatically stopped, and the bandgap reference source is brought into a normal working state.
In some embodiments, the S0 state, S1 state, and S2 state of the start-up circuit are different from each other, as detailed in the operating state table of the start-up circuit of the bandgap reference circuit shown above.
Further details of the method for starting the bandgap reference circuit are described in the description of the bandgap reference circuit, and may be directly incorporated herein.
The band gap reference circuit provided by the embodiment of the invention comprises a band gap reference source and a starting circuit, wherein the starting circuit is connected with the starting end of the band gap reference source, the first control module and the second control module in the starting circuit are respectively controlled by external control voltage PD, the starting end voltage of the band gap reference source is adjusted, the problem of degeneracy point when the band gap reference source is in zero current is avoided, the band gap reference source is normally started, the second control module is automatically disconnected after the band gap reference source is normally started by the feedback module, and the band gap reference source is further normally operated to reach a desired stable working point.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Any process or method description in a flowchart or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more (two or more) executable instructions for implementing specific logical functions or steps of the process. And the scope of the preferred embodiments of the present application includes additional implementations in which functions may be performed in a substantially simultaneous manner or in an opposite order from that shown or discussed, including in accordance with the functions that are involved.
Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions.
It is to be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. All or part of the steps of the methods of the embodiments described above may be performed by a program that, when executed, comprises one or a combination of the steps of the method embodiments, instructs the associated hardware to perform the method.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules described above, if implemented in the form of software functional modules and sold or used as a stand-alone product, may also be stored in a computer-readable storage medium. The storage medium may be a read-only memory, a magnetic or optical disk, or the like.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think of various changes or substitutions within the technical scope of the present application, and these should be covered in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (13)

1. The band gap reference circuit is characterized by comprising a band gap reference source and a starting circuit; the starting circuit comprises a first control module, a second control module and a feedback module; the first control module is used for pulling up the potential of the starting end of the band gap reference source when the control voltage PD is at a first level; the second control module is used for pulling the starting end potential of the band gap reference source low when the control voltage PD is at a second level; the feedback module is used for turning off the starting circuit after the band gap reference source is started.
2. The bandgap reference circuit of claim 1, wherein a first end of said first control module is for connection to a power supply, a second end of said first control module is for obtaining a control voltage PD, and a third end of said first control module is connected to a first end of said second control module, an input end of said feedback module, and a start-up end of said bandgap reference source; the second end of the second control module is used for acquiring control voltage PD, the third end of the control module is used for being grounded, and the fourth end of the control module is connected with the output end of the feedback module.
3. The bandgap reference circuit of claim 2, wherein when said control voltage PD is a first level, said first control module is turned on, said second control module is turned off, a start-up terminal potential of said bandgap reference source is pulled up to a supply voltage, said bandgap reference source is not started up; when the control voltage PD is at a second level, the first control module is turned off, the second control module is turned on, the starting end potential of the band gap reference source is pulled down to the ground, and the band gap reference source is started; and after the band gap reference source is started, the feedback module pulls the fourth end level of the second control module down to the ground, so that the second control module is turned off.
4. The bandgap reference circuit of claim 2, wherein said first control module comprises a PMOS transistor M2, a source of said PMOS transistor M2 forming a first end of said first control module, a gate of said PMOS transistor M2 forming a second end of said first control module, and a drain of said PMOS transistor M2 forming a third end of said first control module.
5. The bandgap reference circuit of claim 2, wherein said second control module comprises an NMOS transistor NM0 and an NMOS transistor NM1, a drain of said NMOS transistor NM0 forming a first end of said second control module, a source of said NMOS transistor NM0 being connected to a drain of said NMOS transistor NM1, a gate of said NMOS transistor NM0 forming a second end of said second control module, a source of said NMOS transistor NM1 forming a third end of said second control module, a gate of said NMOS transistor NM1 forming a fourth end of said second control module.
6. The bandgap reference circuit of claim 2, wherein said feedback module includes a first inverter and a second inverter; the input end of the first inverter forms the input end of the feedback module, the output end of the first inverter is connected with the input end of the second inverter, and the output end of the second inverter forms the output end of the feedback module.
7. The bandgap reference circuit as claimed in claim 6, wherein said first inverter comprises a PMOS transistor M3 and an NMOS transistor NM3; the grid electrode of the PMOS tube M3 is connected with the grid electrode of the NMOS tube NM3 to form the input end of the first inverter; the drain electrode of the PMOS tube M3 is connected with the drain electrode of the NMOS tube NM3 to form the output end of the first inverter; the source electrode of the PMOS tube M3 is used for being connected with a power supply, and the source electrode of the NMOS tube NM3 is used for being grounded.
8. The bandgap reference circuit as claimed in claim 6, wherein said first inverter comprises a PMOS transistor M3 and a resistor R1; the grid electrode of the PMOS tube M3 forms the input end of the first inverter; the drain electrode of the PMOS tube M3 is connected with the first end of the resistor R1 to form the output end of the first inverter; the source electrode of the PMOS tube M3 is used for being connected with a power supply, and the second end of the resistor R1 is used for being grounded.
9. The bandgap reference circuit as claimed in claim 6, wherein said second inverter comprises a PMOS transistor M4, a PMOS transistor M5, a PMOS transistor M6 and an NMOS transistor NM2; the grid electrode of the PMOS tube M4 is connected with the grid electrode of the PMOS tube M5, the grid electrode of the PMOS tube M6 and the grid electrode of the NMOS tube NM2 to form the input end of the second inverter; the drain electrode of the PMOS tube M4 is connected with the source electrode of the PMOS tube M5, the drain electrode of the PMOS tube M5 is connected with the source electrode of the PMOS tube M6, and the drain electrode of the PMOS tube M6 is connected with the drain electrode of the NMOS tube NM2 to form the output end of the second inverter; the source electrode of the PMOS tube M4 is used for being connected with a power supply, and the source electrode of the NMOS tube NM2 is used for being grounded.
10. The bandgap reference circuit of any one of claims 1 to 9, wherein said bandgap reference source comprises PMOS transistor M0, PMOS transistor M1, resistor R0, bipolar transistor T1, bipolar transistor T2 and operational amplifier a; the source electrode of the PMOS tube M0 and the source electrode of the PMOS tube M1 are used for being connected with a power supply, the drain electrode of the PMOS tube M0 is connected with the emitter electrode of the bipolar transistor T1, the drain electrode of the PMOS tube M1 is connected with the first end of the resistor R0, the second end of the resistor R0 is connected with the emitter electrode of the bipolar transistor T2, and the base electrode and the collector electrode of the bipolar transistor T1 and the base electrode and the collector electrode of the bipolar transistor T2 are used for being grounded; the reverse input end of the operational amplifier A is connected with the common end of the PMOS tube M0 and the bipolar transistor T1, the forward input end of the operational amplifier A is connected with the common end of the PMOS tube M1 and the resistor R0, and the output end of the operational amplifier A is connected with the grid electrode of the PMOS tube M0 and the grid electrode of the PMOS tube M1 to form the starting end of the band gap reference source.
11. The starting circuit is characterized by comprising a first control module, a second control module and a feedback module; the first control module is used for pulling up the potential of the starting end of the band gap reference source when the control voltage PD is at a first level; the second control module is used for pulling the potential of the starting end of the band gap reference source down when the control voltage PD is at a second level; the feedback module is used for turning off the starting circuit after the band gap reference source is started.
12. The start-up circuit of claim 11, wherein when the control voltage PD is a first level, the first control module is turned on, the second control module is turned off, the start-up terminal potential of the bandgap reference source is pulled up to the supply voltage, and the bandgap reference source is not started up; when the control voltage PD is at a second level, the first control module is turned off, the second control module is turned on, the starting end potential of the band gap reference source is pulled down to the ground, and the band gap reference source is started; after the band gap reference source is started, the feedback module enables the second control module to be automatically turned off.
13. A method of starting a bandgap reference circuit, the bandgap reference circuit comprising a bandgap reference source and a starting circuit, the starting circuit comprising a first control module, a second control module and a feedback module, the method comprising:
the control voltage PD is made to be a first level, the first control module is utilized to pull up the starting end potential of the band gap reference source under the action of the control voltage PD, and the starting circuit is marked to be in an S0 state at the moment;
the control voltage PD is made to be a second level, and the second control module is utilized to pull the potential of the starting end of the band gap reference source low under the action of the control voltage PD, so that the starting circuit is marked to be in an S1 state at the moment;
the level of the control voltage PD is kept unchanged, the starting circuit is turned off by the feedback module, and the starting circuit is marked to be in an S2 state at the moment;
the S0 state, the S1 state, and the S2 state are different from each other.
CN202310594122.7A 2023-05-25 2023-05-25 Band gap reference circuit, starting circuit and starting method thereof Active CN116414174B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107943182A (en) * 2017-11-30 2018-04-20 上海华虹宏力半导体制造有限公司 Band gap reference start-up circuit
CN109613951A (en) * 2018-11-30 2019-04-12 宁波德晶元科技有限公司 A kind of band-gap reference source circuit with self-start circuit
US20230046259A1 (en) * 2021-08-12 2023-02-16 Ferroelectric Memory Gmbh Startup circuit and methods thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107943182A (en) * 2017-11-30 2018-04-20 上海华虹宏力半导体制造有限公司 Band gap reference start-up circuit
CN109613951A (en) * 2018-11-30 2019-04-12 宁波德晶元科技有限公司 A kind of band-gap reference source circuit with self-start circuit
US20230046259A1 (en) * 2021-08-12 2023-02-16 Ferroelectric Memory Gmbh Startup circuit and methods thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
低压低功耗CMOS带隙电压基准及启动电路设计: "低压低功耗CMOS带隙电压基准及启动电路设计", 半导体学报, vol. 26, no. 10, pages 2022 - 2027 *

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