CN110196388A - Integrated chip and its test method - Google Patents
Integrated chip and its test method Download PDFInfo
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- CN110196388A CN110196388A CN201910539980.5A CN201910539980A CN110196388A CN 110196388 A CN110196388 A CN 110196388A CN 201910539980 A CN201910539980 A CN 201910539980A CN 110196388 A CN110196388 A CN 110196388A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
- G01R31/2889—Interfaces, e.g. between probe and tester
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31713—Input or output interfaces for test, e.g. test pins, buffers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
- G01R31/31726—Synchronization, e.g. of test, clock or strobe signals; Signals in different clock domains; Generation of Vernier signals; Comparison and adjustment of the signals
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
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- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The present invention provides a kind of integrated chip and its test methods, are related to integrated chip technology field, which includes: low speed general-purpose interface, eFPGA circuit and at least one functional circuit；Low speed general-purpose interface is connected with eFPGA circuit, and eFPGA circuit is connected with each functional circuit；Low speed general-purpose interface is used to receive the test file that external intelligent terminal is sent, and test file is sent to eFPGA circuit；EFPGA circuit is used to obtain the test signal of objective function circuit based on the test file received, and the test signal that will acquire feeds back to low speed general-purpose interface；The test signal that low speed general-purpose interface is also used to receive is sent to intelligent terminal, so that intelligent terminal obtains the functional test results of objective function circuit based on test signal.Limitation of the chip signal rate to functional test can also be effectively relieved in I/O interface quantity needed for the present invention can effectively reduce functional test.
Description
Technical field
The present invention relates to integrated chip technology fields, more particularly, to a kind of integrated chip and its test method.
Background technique
With the increasingly increase of electronic equipment processing capability requirements, chip is main as decision electronic equipment processing capacity
One of factor, interior design is also increasingly sophisticated, and the available sufficient verifying of the function in order to guarantee chip interior complexity is surveyed
Examination, most chips can increase Testability Design in inside.Presently mainly by the IO of chip (Input/Output, input/
Output) interface realizes that the function to chip is tested, therefore the quantity available of IO just determines the testability energy of chip,
Can not be by functional test for high speed signal additionally, due to existing chip, therefore the functional test of chip is by chip I/O interface
The limitation of quantity and chip signal rate.
Summary of the invention
In view of this, function can be effectively reduced the purpose of the present invention is to provide a kind of integrated chip and its test method
I/O interface quantity needed for capable of testing, can also be effectively relieved limitation of the chip signal rate to functional test.
In a first aspect, the embodiment of the invention provides a kind of integrated chips, comprising: low speed general-purpose interface, eFPGA circuit and
At least one functional circuit；The low speed general-purpose interface is connected with the eFPGA circuit, and the eFPGA circuit and each institute
Functional circuit is stated to be connected；Wherein, the low speed general-purpose interface is used to receive the test file that external intelligent terminal is sent, and
The test file is sent to the eFPGA circuit；The eFPGA circuit based on the test file received for being obtained
The test signal of objective function circuit is taken, and the test signal that will acquire feeds back to the low speed general-purpose interface；Wherein, institute
Stating objective function circuit is test file functional circuit to be measured；The low speed general-purpose interface is also used to the institute that will be received
It states test signal and is sent to the intelligent terminal, so that the intelligent terminal is based on the test signal and obtains the objective function
The functional test results of circuit.
With reference to first aspect, the embodiment of the invention provides the first possible embodiments of first aspect, wherein institute
Stating eFPGA circuit includes the interface controller connecting with the low speed general-purpose interface, and connect with the interface controller
Configuration module and signal sampling module；Wherein, the configuration module is used to configure the operating mode of the interface controller；It is described
Interface controller is used to adjust the timing of the low speed general-purpose interface according to the operating mode of configuration；The low speed is general to be connect
The test file is sent to institute for receiving the test file that the intelligent terminal is sent based on the timing by mouth
State eFPGA circuit；The interface controller is also used to generate signal-obtaining request based on the test file, and by the signal
Read requests are sent to the signal sampling module；The signal sampling module is used to acquire the test of the objective function circuit
Signal, and the test signal is sent to the interface controller when receiving signal-obtaining request.
The possible embodiment of with reference to first aspect the first, the embodiment of the invention provides second of first aspect
Possible embodiment, wherein the eFPGA circuit further includes the signal cache module connecting with the signal sampling module；
Wherein, the signal sampling module is also used to cache the test signal to the signal cache module, and receiving
Read the test signal of caching when stating signal-obtaining request from the signal cache module, and by the test of reading
Signal is sent to the interface controller.
The possible embodiment of second with reference to first aspect, the embodiment of the invention provides the third of first aspect
Possible embodiment, wherein the eFPGA circuit further includes and the configuration module, the signal sampling module and described
The connected clock module of signal cache module；Wherein, the configuration module is also used to configure the frequency letter of the clock module
Breath；The clock module is used for according to the frequency information, and Xiang Suoshu signal sampling module and the signal cache module provide
Work clock.
The possible embodiment of second with reference to first aspect, the embodiment of the invention provides the 4th kind of first aspect
Possible embodiment, wherein the configuration module is also connected with the signal cache module；The chip further includes successively connecting
The internal processor and bus connect；The bus is connected with the configuration module；The internal processor is for receiving the intelligence
The test instruction that energy terminal is sent, and pass through the bus and configuration module reading institute when receiving test instruction
The test signal of signal cache module caching is stated, and the test signal will be read and be sent to the intelligent terminal, with
The intelligent terminal is set to obtain the functional test results of the objective function circuit based on the test signal.
With reference to first aspect, the embodiment of the invention provides the 5th kind of possible embodiments of first aspect, wherein institute
Stating low speed general-purpose interface includes jtag interface, I2One of C interface, SPI interface or UART interface are a variety of.
Second aspect, the embodiment of the present invention also provide a kind of test method of integrated chip, and the method is applied to integrated
Chip, the integrated chip include: low speed general-purpose interface, eFPGA circuit and at least one functional circuit；The low speed is general to be connect
Mouth is connected with the eFPGA circuit, and the eFPGA circuit is connected with each functional circuit, which comprises logical
It crosses low speed general-purpose interface and receives the test file that external intelligent terminal is sent；The test file is based on by eFPGA circuit
The test signal of objective function circuit is obtained, and the test signal that will acquire feeds back to the low speed general-purpose interface；Wherein,
The objective function circuit is test file functional circuit to be measured；The institute that will be received by the low speed general-purpose interface
It states test signal and is sent to the intelligent terminal, so that the intelligent terminal is based on the test signal and obtains the objective function
The functional test results of circuit.
In conjunction with second aspect, the embodiment of the invention provides the first possible embodiments of second aspect, wherein institute
Stating eFPGA circuit includes: interface controller and configuration module；It is described that external intelligent terminal hair is received by low speed general-purpose interface
The step of test file sent, comprising: the operating mode of the interface controller is configured by the configuration module；By described
Interface controller adjusts the timing of the low speed general-purpose interface according to the operating mode of configuration；It is connect by the way that the low speed is general
Mouth receives the test file that external intelligent terminal is sent based on the timing.
In conjunction with the first possible embodiment of second aspect, the embodiment of the invention provides second of second aspect
Possible embodiment, wherein the eFPGA circuit further include: signal sampling module；It is described that institute is based on by eFPGA circuit
State the step of test file obtains the test signal of objective function circuit, comprising: the survey is based on by the interface controller
The request of file generated signal-obtaining is tried, and signal-obtaining request is sent to the signal sampling module；Pass through the letter
Number sampling module acquires the test signal of the objective function circuit, and when receiving signal-obtaining request by the survey
Trial signal is sent to the interface controller.
In conjunction with second of possible embodiment of second aspect, the embodiment of the invention provides the third of second aspect
Possible embodiment, wherein the eFPGA circuit further include: clock module and signal cache module；It is described to pass through the letter
Number sampling module acquires the test signal of the objective function circuit, and when receiving signal-obtaining request by the survey
Trial signal is sent to the step of interface controller, comprising: the frequency of the clock module is configured by the configuration module
Information；It is mentioned by the clock module according to the frequency information, Xiang Suoshu signal sampling module and the signal cache module
For work clock；The test signal is cached to the signal cache module by the signal sampling module, and is being received
To the test signal for reading caching when signal-obtaining request from the signal cache module, and will be described in reading
Test signal is sent to the interface controller.
The embodiment of the present invention bring it is following the utility model has the advantages that
A kind of integrated chip and its test method provided in an embodiment of the present invention, including low speed general-purpose interface, it is logical with low speed
EFPGA (e-Field-Programmable Gate Array, the embedded field programmable gate array) electricity being connected with interface
Road, and at least one functional circuit being connected with eFPGA circuit, low speed general-purpose interface are used to receive external intelligent terminal hair
The test file sent, eFPGA circuit is used to obtain the test signal of objective function circuit based on test file, general by low speed
The test signal is sent to intelligent terminal by interface, so that intelligent terminal obtains the function of objective function circuit based on the test signal
It can test result.The embodiment of the present invention realizes the communication between smart machine and eFPGA circuit by low speed general-purpose interface, because
Low speed general-purpose interface occupies I/O interface negligible amounts, therefore I/O interface quantity needed for can effectively reducing functional test；In addition,
EFPGA circuit supports the signal of higher rate in the present invention, therefore chip signal rate can be effectively relieved to functional test
Limitation.
Other features and advantages of the present invention will illustrate in the following description, also, partly become from specification
It obtains it is clear that understand through the implementation of the invention.The objectives and other advantages of the invention are in specification, claims
And specifically noted structure is achieved and obtained in attached drawing.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate
Appended attached drawing, is described in detail below.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art be briefly described, it should be apparent that, it is described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is a kind of structural schematic diagram of integrated chip provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram of another integrated chip provided in an embodiment of the present invention；
Fig. 3 is a kind of flow diagram of the test method of integrated chip provided in an embodiment of the present invention；
Fig. 4 is the flow diagram of the test method of another integrated chip provided in an embodiment of the present invention.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with embodiment to this hair
Bright technical solution is clearly and completely described, it is clear that and described embodiments are some of the embodiments of the present invention, without
It is whole embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not before making creative work
Every other embodiment obtained is put, shall fall within the protection scope of the present invention.
Currently, being tested integrated chip (ASIC, Application Specific Integrated Circuit)
When, digital I/O interface usually will not be specially designed for the test circuit of chip, carried out with the function I/O interface of chip itself
There are biggish limitation when being multiplexed, but testing by function of the I O multiplexing to chip, it is primarily due to IO quantity on chip
Limited, most pins cannot be multiplexed in functional test, and the I/O pin quantity as the input of test circuit activation or result output
It is extremely limited, lead to limit the quantity of the test signal got when test；Secondly, the Digital I/O working frequency of chip is little
In 100MHz, and high speed digital I/O is used mostly as clock or differential data signals, can not be used as test I/O, while big
The high speed digital I/O of amount, which uses, also will increase chip power-consumption, and high speed signal can not be by that can test circuit output core in chip
Built-in testing.
Based on this, the present invention implements the integrated chip and its test method provided, can effectively reduce needed for functional test
I/O interface quantity, limitation of the chip signal rate to functional test can also be effectively relieved.
To be carried out first to a kind of integrated chip disclosed in the embodiment of the present invention detailed convenient for understanding the present embodiment
Thin to introduce, a kind of structural schematic diagram of integrated chip shown in Figure 1, the chip includes: low speed general-purpose interface 110, eFPGA
Circuit 120 and at least one functional circuit 130, low speed general-purpose interface 110 is connected with eFPGA circuit 120, and eFPGA circuit 120
It is connected with each functional circuit 130.
Low speed general-purpose interface 110 is used to receive the test file that external intelligent terminal is sent, and test file is sent
Give eFPGA circuit.Low speed general-purpose interface is for realizing the communication between smart machine and eFPGA circuit, in a kind of embodiment
In, the quantity that low speed general-purpose interface occupies digital I/O interface is generally 5 to 6, therefore can be effective using low speed general-purpose interface
Reduce the demand that test circuit is multiplexed digital I/O interface.Test file can be circuit meshwork list file, connect by the way that low speed is general
Mouthful by circuit meshwork list file download into eFPGA circuit, so that eFPGA circuit is based on the circuit meshwork list file to functional circuit
Corresponding function is tested, and in the specific implementation, user writes hardware RTL (Register Transfer by intelligent terminal
Level, buffer shift grade circuit) code, then utilizing EDA (Electronics Design Automation, electronics
Design automation) RTL code is generated as aforementioned test file by tool, and low speed general-purpose interface receives the test file, and will survey
Examination file is sent to ePFGA circuit.
EFPGA circuit 120 is used to obtain the test signal of objective function circuit based on the test file received, and will obtain
The test signal taken feeds back to low speed general-purpose interface.Wherein, objective function circuit is test file functional circuit to be measured.
EFPGA circuit namely the programmable circuit in asic chip is embedded in by embedded FPGA technology, eFPGA circuit is that one kind can
Reconstructed number circuit is made of the programmable logic junior unit interconnected, when not carrying out functional test to asic chip, eFPGA
Circuit can be used as the use of the functional module in chip；It, can be with when needing to be acquired observation to the signal in asic chip
Using the programmable reconstruct feature of eFPGA circuit, the corresponding test circuit of addition is re-downloaded based on test file, and utilize
Eda software carries out the crawl and test of test signal.Also, eFPGA circuit supports the signal of higher rate, therefore can be effective
Alleviate limitation of the chip signal rate to functional test.
The test signal that low speed general-purpose interface is also used to receive is sent to intelligent terminal, so that intelligent terminal is based on surveying
Trial signal obtains the functional test results of objective function circuit.After eFPGA collects the test signal of objective function circuit, just
It is sent to intelligent terminal by signal is tested by low speed general-purpose interface, to complete the functional test of objective function circuit.Wherein,
Test content may include register SCAN boundary scan, storage built-in testing (MBIST), IO test and IP (Internet
Protocol, net association) technologies such as self-test also may include that the customization of its internal concrete function for chip can be tested and be patrolled
Volume.
A kind of integrated chip provided in an embodiment of the present invention, including low speed general-purpose interface are connected with low speed general-purpose interface
EFPGA circuit, and at least one functional circuit being connected with eFPGA circuit, low speed general-purpose interface is for receiving external intelligence
The test file that energy terminal is sent, eFPGA circuit are used to be obtained the test signal of objective function circuit based on test file, passed through
The test signal is sent to intelligent terminal by low speed general-purpose interface, so that intelligent terminal is based on the test signal and obtains objective function
The functional test results of circuit.The embodiment of the present invention is realized between smart machine and eFPGA circuit by low speed general-purpose interface
Communication, because low speed general-purpose interface occupies I/O interface negligible amounts, I/O interface needed for can effectively reducing functional test
Quantity；In addition, eFPGA circuit supports the signal of higher rate in the present invention, therefore chip signal rate pair can be effectively relieved
The limitation of functional test.
For convenient for understanding above-described embodiment, the embodiment of the invention also provides another integrated chips, referring to fig. 2
Shown in another kind integrated chip structural schematic diagram, on the basis of Fig. 1, also illustrate interface controller 121, configuration mould
Block 122, signal sampling module 123, signal cache module 124, clock module 125 and bus 140.
Wherein, eFPGA circuit 120 includes the interface controller 121 connecting with low speed general-purpose interface 110, and and interface
The configuration module 122 and signal sampling module 123 that controller 121 connects.
Configuration module 122 is used to configure the operating mode of interface controller 121.Interface controller 121 is used for according to configuration
Operating mode adjustment low speed general-purpose interface 110 timing.Wherein, interface controller can be JTAG (Joint Test
Action Group, joint test working group) controller.In view of different intelligent terminal is to the timing requirements of low speed general-purpose interface
It is different, it is therefore desirable to be configured by operating mode of the configuration module to interface controller, interface controller is based on Working mould
Formula adjusts the timing of low speed general-purpose interface, so that the timing of low speed general-purpose interface meets the requirement of intelligent terminal, to pass through tune
Low speed general-purpose interface after saving timing completes the communication between eFPGA circuit and intelligent terminal.
Low speed general-purpose interface 110 is also used to receive the test file that intelligent terminal is sent based on timing, and by test file
It is sent to eFPGA circuit.
Interface controller 121 is also used to generate signal-obtaining request based on test file, and signal-obtaining is requested to send
To signal sampling module.After interface controller receives test file again, need to obtain objective function circuit observation signal (
That is, aforementioned test signal), and observation signal is back to by intelligent terminal by low speed general-purpose interface.In one embodiment,
In order to obtain the observation signal of objective function circuit, signal can be generated based on test file and read after receiving test file
Request is taken, so that the observation signal of objective function circuit is back to interface control circuit by signal sampling module.
Signal sampling module 123 is used to acquire the test signal of objective function circuit, and is receiving signal-obtaining request
When will test signal be sent to interface controller.Further, eFPGA circuit 120 further includes connecting with signal sampling module 123
Signal cache module 124.Signal sampling module 123 is also used to test signal and caches to signal cache module 124, and is connecing
The test signal for reading caching when signal-obtaining request from signal cache module 124 is received, and the test signal of reading is sent out
It send to interface controller 121.Because the debugging process of asic chip is more slow, real-time sampling cannot achieve, and adopt in real time
Collection signal is easy to appear the phenomenon that information is lost, and because functional test needs to obtain the change of objective function circuit in a period of time
Change, therefore signal sampling module first caches collected test signal to signal cache module, and is receiving signal-obtaining
When request, the test signal is read from signal cache module, and test signal is sent to interface controller.
In some embodiments, eFPGA circuit 120 further includes and configuration module 122, signal sampling module 123 and letter
Number connected clock module 125 of cache module 124.Wherein, configuration module 122 is also used to the frequency of configurable clock generator module 125
Information, clock module 125 is used for according to frequency information, when providing work to signal sampling module 123 and signal cache module 124
Clock.Clock module can be configurable clock phase-locked loop.
Further, eFPGA circuit can built-in high speed phase-locked loop circuit, so as to realize high speed signal in asic chip
Observation.
In view of intelligent terminal may not have low speed general-purpose interface, therefore in order to which the embodiment of the invention also provides one kind
Candidate scheme, configuration module 122 are also connected with signal cache module 124, also, chip further includes sequentially connected inter-process
Device (CPU, Central Processing Unit/Processor) and bus 140, bus 140 are connected with configuration module 122.
Wherein, internal processor is used to receive the test instruction of intelligent terminal transmission, and when receiving test instruction by bus and
Configuration module reads the test signal of signal cache module caching, and will read test signal and be sent to intelligent terminal, so that
Intelligent terminal obtains the functional test results of objective function circuit based on test signal.When it is implemented, being compiled by smart machine
Test instruction is write, and test instruction is sent to innernal CPU by communicating with innernal CPU, is referred to so that innernal CPU executes this
It enables, when innernal CPU goes to the instruction of read test signal, is read in signal cache module and delayed by bus and configuration module
The test signal read is just returned to intelligent terminal by the test signal deposited, innernal CPU.Wherein, core on chip designs have bus,
The asic chip of innernal CPU is referred to as SoC (System on Chip, system level chip) chip.
Further, configuration module and signal sampling module can pass through alternative module and signal cache module phase
Even, i.e., it when intelligent terminal is provided with corresponding low speed general-purpose interface, is read in signal cache module by signal sampling module
The test signal of caching reads signal caching by configuration module when the not set corresponding low speed general-purpose interface of intelligent terminal
The test signal cached in module.
In view of the demand of asic chip is different, low speed general-purpose interface 110 includes jtag interface, I2C (Inter-
Integrated Circuit, inter-integrated circuit) interface, SPI (Serial Peripheral Interface, serial peripheral
Interface) interface or UART (Universal Asynchronous Receiver/Transmitter, universal asynchronous receiving-transmitting transmission
Device) one of interface or a variety of, to meet the interface requirements of different asic chips.In addition, above-mentioned intelligent terminal can be PC
(Personal Compute, personal computer) machine.
For convenient for understanding above-described embodiment, the embodiment of the invention also provides a kind of collection that design has high speed to exchange
There is the integrated chip of high speed DDR (Double Data Rate, Double Data Rate) at chip and a kind of design.
Wherein, the integrated chip for thering is high speed to exchange design, since the transmission rate of protocol circuit is generally at Gbit grades
Not, so the working frequency of its internal digital circuit is generally in 100MHz between 400MHz.Signal working frequency is high, and data
Bit wide is larger, and programmable debug circuit of the invention (that is, aforementioned eFPGA circuit) can satisfy the sampling of such high speed signal
Demand.Simultaneously as the reconfigurability of eFPGA circuit, therefore the high speed exchange integrated chip also designed can also support high speed
The partial function of protocol controller in protocol circuit, to reach the function that can test circuit multiplexer.
There is the integrated chip of high speed DRR for design, since current high speed DDR controller supports depositing for DRR3 or more again
When storing up particle, internal operating frequencies are generally in 200MHz or more, and its internal data bit width is also at least in 32bit or more.
And the initial stage situation that DDR controller is debugged in chip is more complicated, needs the detailed data knot to DDR controller internal signal
Fruit, phase relation and control sequential are observed debugging, and eFPGA circuit provided by the invention can satisfy high speed just
The demand that DDR controller grabs various signals.It can be realized using eFPGA circuit as DDR numerical portion controller a part
In demand chip, while supporting normal function, necessary test signals samples function is supported.
In conclusion the embodiment of the present invention can achieve at least one following features:
(1) programmable circuit combination ASIC architecture design is used, so that whole debug circuit can pass through external downloading mode
It is customizable to support debug circuit, so that it is higher to debug logic flexibility in chip.
(2) may be programmed can use high-speed phase-locked loop sampled signal inside debug circuit, and use caching record sampled result, make
It obtains signal observation bandwidth to increase, Observable range of signal is wider.
(3) it may be programmed the output of debug circuit result, cache way read by low speed general-purpose interface and is realized, wherein JTAG
Interface occupies Digital I/O quantity and is generally 5~6, reduces demand of the test circuit to digital I O multiplexing, reduces chip survey
Function restriction when examination.
(4) it may be programmed debug circuit since circuit is restructural, so first preferentially can be used as functional circuit support chip function
Can, download debug circuit again when needing to debug and be observed, reduce chip as debugging logic and caused by area overhead.
(5) it can be read by the bus in chip as a result, being suitable for intelligent terminal does not have eda software or corresponding low
It is more to be applicable in debugging scenarios for functional test when fast general-purpose interface.
For the integrated chip that previous embodiment provides, the embodiment of the invention also provides a kind of test sides of integrated chip
Method, a kind of flow diagram of the test method of integrated chip shown in Figure 3, this method are applied to integrated chip, integrate
Chip includes: low speed general-purpose interface, eFPGA circuit and at least one functional circuit；Low speed general-purpose interface and eFPGA circuit phase
Even, and eFPGA circuit is connected with each functional circuit, and this method may comprise steps of:
Step S302 receives the test file that external intelligent terminal is sent by low speed general-purpose interface.
User writes hardware RTL code by intelligent terminal, and utilize according to the test sample demand of chip interior function
Eda tool is based on hardware RTL code generative circuit net meter file, using the circuit meshwork list file as test file.
Step S304, the test signal of objective function circuit is obtained by eFPGA circuit based on test file, and will acquire
Test signal feed back to low speed general-purpose interface.
Wherein, objective function circuit is test file functional circuit to be measured.EFPGA circuit is receiving test file
Afterwards, the test signal of objective function circuit is obtained, and the test signal is fed back into low speed general-purpose interface.
The test signal received is sent to intelligent terminal by low speed general-purpose interface by step S306, so that intelligence is eventually
End group obtains the functional test results of objective function circuit in test signal.
A kind of test method of integrated chip provided in an embodiment of the present invention obtains intelligence by low speed general-purpose interface first
The test file that terminal is sent, then the test signal by eFPGA circuit based on test file acquisition objective function circuit, finally
It is sent to intelligent terminal by signal is tested by low speed general-purpose interface, so that intelligent terminal is based on test signal and obtains objective function
The functional test results of circuit.The embodiment of the present invention is realized between smart machine and eFPGA circuit by low speed general-purpose interface
Communication, because low speed general-purpose interface occupies I/O interface negligible amounts, I/O interface needed for can effectively reducing functional test
Quantity；In addition, eFPGA circuit supports the signal of higher rate in the present invention, therefore chip signal rate pair can be effectively relieved
The limitation of functional test.
To understand that the embodiment of the present invention also provides convenient for the test method to integrated chip provided by the above embodiment
Another test method of integrated chip, the flow diagram of the test method of another integrated chip shown in Figure 4,
This method may comprise steps of:
Step S402 configures the operating mode of interface controller by configuration module.
Wherein, eFPGA circuit circuit includes interface controller and configuration module.
Step S404 adjusts the timing of low speed general-purpose interface by interface controller according to the operating mode of configuration.
Because different PC machine are different to the timing requirements of low speed general-purpose interface, it is therefore desirable to by configuration module to interface control
The operating mode of device processed is configured, and then adjusts low speed general-purpose interface based on the operating mode after accompanying by interface controller
Working sequence so that the timing of low speed general-purpose interface meets PC machine demand.
Step S406 receives the test file that external intelligent terminal is sent based on timing by low speed general-purpose interface.
Step S408 is based on test file by interface controller and generates signal-obtaining request, and signal-obtaining is requested
It is sent to signal sampling module.
Wherein, eFPGA circuit further includes signal sampling module, and signal sampling module is used to read the survey of objective function circuit
Trial signal.
Step S410 is acquired the test signal of objective function circuit by signal sampling module, and read receiving signal
It takes and test signal is sent to interface controller when request.
Further, eFPGA circuit further includes clock module and signal cache module, and the embodiment of the invention also provides one
Kind acquires the test signal of objective function circuit by signal sampling module, and will test letter when receiving signal-obtaining request
The step of number being sent to interface controller, which includes the following steps (1) to step (4):
Step (1), passes through the frequency information of configuration module configurable clock generator module.It should be understood that because different function electricity
The frequency information on road is different, therefore in order to obtain the test signal of objective function circuit, needs signal acquisition module and signal
The frequency of buffer module is adjusted in frequency corresponding with objective function circuit, and the present invention passes through configuration module configurable clock generator mould
The frequency information of block, to be adjusted by frequency of the clock module to signal acquisition module and signal cache module.
Step (2) provides work to signal sampling module and signal cache module by clock module according to frequency information
Clock.
Step (3) is cached signal is tested to signal cache module by signal sampling module, and read receiving signal
The test signal for reading caching when request from signal cache module is taken, and the test signal of reading is sent to Interface Controller
Device.
The test signal received is sent to intelligent terminal by low speed general-purpose interface by step S412, so that intelligence is eventually
End group obtains the functional test results of objective function circuit in test signal.
For convenient for understanding above-described embodiment, the embodiment of the invention also provides the test sides of another integrated chip
Method, referring to following steps 1 to step 5:
Step 1, according to the test sample demand of chip interior function, function connects are adopted to signal in eFPGA circuit
In egf block.That is, the frequency information to clock module configures, by making clock module adjustment signal sampling module, with
It is in signal sampling module and objective function circuit in same frequency, to complete objective function circuit and signal sampling module
Connection.
Step 2, according to testing requirement, samples storage size, reasonable distribution test resource are customized.In view of eFPAG circuit
In limited memory, it is therefore desirable to the samples storage of eFPAG circuit is allocated, in one embodiment, can basis
The quantity of required measuring signal distributes the storage size to eFPAG circuit.Wherein, test resource namely storage size.
Step 3, jtag interface is connected to PC machine, PC machine is downloaded to test file in integrated chip by jtag interface
EFPGA circuit in.
Step 4, the frequency information of configurable clock generator module.
Step 5, by interface controller enabling signal sampling module, signal sampling module starts to objective function circuit
Test signal is read out.
Step 6, signal sampling module receives the signal-obtaining request from interface controller, will be in signal cache module
Interface controller is sent in test signal reading.
Step 7, PC machine is back to for signal is tested by jtag interface.
The technical effect and aforementioned device embodiment phase of method provided by the embodiment of the present invention, realization principle and generation
Together, to briefly describe, embodiment of the method part does not refer to place, can refer to corresponding contents in aforementioned device embodiment.
Finally, it should be noted that embodiment described above, only a specific embodiment of the invention, to illustrate the present invention
Technical solution, rather than its limitations, scope of protection of the present invention is not limited thereto, although with reference to the foregoing embodiments to this hair
It is bright to be described in detail, those skilled in the art should understand that: anyone skilled in the art
In the technical scope disclosed by the present invention, it can still modify to technical solution documented by previous embodiment or can be light
It is readily conceivable that variation or equivalent replacement of some of the technical features；And these modifications, variation or replacement, do not make
The essence of corresponding technical solution is detached from the spirit and scope of technical solution of the embodiment of the present invention, should all cover in protection of the invention
Within the scope of.Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. a kind of integrated chip characterized by comprising low speed general-purpose interface, eFPGA circuit and at least one functional circuit；
The low speed general-purpose interface is connected with the eFPGA circuit, and the eFPGA circuit is connected with each functional circuit；
Wherein,
The low speed general-purpose interface is used to receive the test file that external intelligent terminal is sent, and the test file is sent
To the eFPGA circuit；
The eFPGA circuit is used to obtain the test signal of objective function circuit based on the test file received, and will
The test signal obtained feeds back to the low speed general-purpose interface；Wherein, the objective function circuit is the test file
Functional circuit to be measured；
The test signal that the low speed general-purpose interface is also used to receive is sent to the intelligent terminal, so that the intelligence
Energy terminal obtains the functional test results of the objective function circuit based on the test signal.
2. chip according to claim 1, which is characterized in that the eFPGA circuit includes and the low speed general-purpose interface
The interface controller of connection, and the configuration module and signal sampling module that are connect with the interface controller；Wherein,
The configuration module is used to configure the operating mode of the interface controller；
The interface controller is used to adjust the timing of the low speed general-purpose interface according to the operating mode of configuration；It is described low
Fast general-purpose interface is used to receive the test file that the intelligent terminal is sent based on the timing, and by the test file
It is sent to the eFPGA circuit；The interface controller is also used to generate signal-obtaining request based on the test file, and will
The signal-obtaining request is sent to the signal sampling module；
The signal sampling module is used to acquire the test signal of the objective function circuit, and is receiving the signal-obtaining
The test signal is sent to the interface controller when request.
3. chip according to claim 2, which is characterized in that the eFPGA circuit further includes and the signal sampling mould
The signal cache module of block connection；Wherein,
The signal sampling module is also used to cache the test signal to the signal cache module, and described receiving
Signal-obtaining reads the test signal of caching from the signal cache module when requesting, and the test of reading is believed
Number it is sent to the interface controller.
4. chip according to claim 3, which is characterized in that the eFPGA circuit further includes and the configuration module, institute
State the clock module that signal sampling module is connected with the signal cache module；Wherein,
The configuration module is also used to configure the frequency information of the clock module；
The clock module is used for according to the frequency information, and Xiang Suoshu signal sampling module and the signal cache module provide
Work clock.
5. chip according to claim 3, which is characterized in that the configuration module also with the signal cache module phase
Even；
The chip further includes sequentially connected internal processor and bus；The bus is connected with the configuration module；
The internal processor is used to receive the test instruction that the intelligent terminal is sent, and when receiving test instruction
The test signal of the signal cache module caching is read by the bus and the configuration module, and will read institute
It states test signal and is sent to the intelligent terminal, so that the intelligent terminal is based on the test signal and obtains the objective function
The functional test results of circuit.
6. chip according to claim 1, which is characterized in that the low speed general-purpose interface includes jtag interface, I2C interface,
One of SPI interface or UART interface are a variety of.
7. a kind of test method of integrated chip, which is characterized in that the method is applied to integrated chip, the integrated chip packet
It includes: low speed general-purpose interface, eFPGA circuit and at least one functional circuit；The low speed general-purpose interface and the eFPGA circuit phase
Even, and the eFPGA circuit is connected with each functional circuit, which comprises
The test file that external intelligent terminal is sent is received by low speed general-purpose interface；
The test signal of objective function circuit, and the survey that will acquire are obtained based on the test file by eFPGA circuit
Trial signal feeds back to the low speed general-purpose interface；Wherein, the objective function circuit is test file function electricity to be measured
Road；
The test signal received is sent to the intelligent terminal by the low speed general-purpose interface, so that the intelligence
Terminal obtains the functional test results of the objective function circuit based on the test signal.
8. the method according to the description of claim 7 is characterized in that the eFPGA circuit includes: interface controller and configuration mould
Block；
The described the step of test file that external intelligent terminal is sent is received by low speed general-purpose interface, comprising:
The operating mode of the interface controller is configured by the configuration module；
The timing of the low speed general-purpose interface is adjusted according to the operating mode of configuration by the interface controller；
The test file that external intelligent terminal is sent is received based on the timing by the low speed general-purpose interface.
9. according to the method described in claim 8, it is characterized in that, the eFPGA circuit further include: signal sampling module；
The described the step of test signal of objective function circuit is obtained based on the test file by eFPGA circuit, comprising:
The test file is based on by the interface controller and generates signal-obtaining request, and the signal-obtaining is requested to send out
It send to the signal sampling module；
The test signal of the objective function circuit is acquired by the signal sampling module, and is receiving the signal-obtaining
The test signal is sent to the interface controller when request.
10. according to the method described in claim 9, it is characterized in that, the eFPGA circuit further include: clock module and signal
Cache module；
The test signal that the objective function circuit is acquired by the signal sampling module, and receiving the signal
The step of test signal is sent to the interface controller when read requests, comprising:
The frequency information of the clock module is configured by the configuration module；
It is provided by the clock module according to the frequency information, Xiang Suoshu signal sampling module and the signal cache module
Work clock；
The test signal is cached to the signal cache module by the signal sampling module, and is receiving the letter
Read the test signal of caching when number read requests from the signal cache module, and by the test signal of reading
It is sent to the interface controller.
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