CN117452998B - PMOS power tube LDO circuit with feedforward zero point stability compensation - Google Patents
PMOS power tube LDO circuit with feedforward zero point stability compensation Download PDFInfo
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- CN117452998B CN117452998B CN202211186970.6A CN202211186970A CN117452998B CN 117452998 B CN117452998 B CN 117452998B CN 202211186970 A CN202211186970 A CN 202211186970A CN 117452998 B CN117452998 B CN 117452998B
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- 239000003990 capacitor Substances 0.000 claims abstract description 20
- 230000003071 parasitic effect Effects 0.000 abstract description 9
- 230000001052 transient effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
A PMOS power tube LDO circuit with feedforward zero point stability compensation relates to an integrated circuit technology. The invention comprises a primary amplifier (EA), a secondary amplifier (A), a PMOS power tube (MPOWER), a fourth PMOS tube, a first PMOS tube, a second PMOS tube, a third NMOS tube, a first NMOS tube, a fourth NMOS tube, a second NMOS tube and a fifth NMOS tube. By adopting the invention, the LDO as compensation can realize stability without parasitic ESR resistance of a capacitor, and the overshoot voltage is less than 50mV when the LDO jumps from no load to heavy load (1A).
Description
Technical Field
The present invention relates to electronic technology, and more particularly to integrated circuit technology.
Background
In the existing LDO with the PMOS power tube, the stability of the LDO is difficult to realize. Stability compensation involves the process of light load and heavy load output poles changing from very low frequency to high frequency. The change of the frequency of the output pole brings great challenges to the stability compensation of the LDO, and the parasitic ESR resistance of the output capacitor is generally required to bring a zero point to compensate the poles of various frequencies inside the LDO by adopting a common circuit structure. The parasitic ESR resistance increases transient overshoot, which can lead to performance degradation in LDOs with fast transient response, and the tantalum capacitance with the parasitic ESR resistance is characterized by instability.
In order to realize the stability of LDOs, many LDOs require that the output capacitor needs a parasitic ESR resistor, and a zero is obtained by connecting the ESR resistor and the output capacitor in series, and the zero can be applied to the compensation of an internal pole in the LDO. However, for a high-power rapid transient response LDO, the parasitic ESR resistor can seriously increase transient overshoot, which causes performance degradation, and the tantalum capacitor with the parasitic ESR resistor has the characteristic of instability, which can bring risks to the application party, and many application parties do not select the tantalum capacitor as an output capacitor.
FIG. 1 is a prior art LDO circuit diagram employing a PMOS power tube as the output terminal, with gain provided by the error amplifier EA1 and the PMOS output terminal. The unit gain amplifier in the figure is used for reducing the grid equivalent resistance of the PMOS power tube, and the poles within the unit gain bandwidth of the LDO comprise output poles, output ends poles of the error amplifier (generally adding Miller compensation) and grid poles of the power tube, so that the overall stability is difficult to realize.
Chinese patent CN111638742B discloses a pole-zero tracking frequency compensated fast settling LDO circuit, see fig. 2. The stability compensation scheme of the circuit is that the output node of the first stage of the error amplifier is pushed to low frequency through the function of a Miller capacitor and is used as a main pole point of the LDO, the output pole of the LDO changes along with the change of a load, the frequency of the output pole is positioned at the extremely low frequency when the LDO is in idle load, and the pole moves to high frequency along with the increase of the output load. According to the invention, the MC tube and the CC capacitor are serially connected to introduce a zero to trace an output pole, so that the influence of the output pole on stability is counteracted, and meanwhile, a high-frequency pole is introduced into an output node of the second-stage error amplifier. The limitation of the invention is that the zero cannot accurately track the change of the output pole along with the change of the load current, so that the scheme can only be applied to the application with small current change. The seventh MOS transistor Mc of the patent is connected in series with a capacitor, has no path to ground, and therefore works in a deep linear region, and the on-resistance of the transistor is
The output power tube works in a saturation region, and the output impedance is approximately R L
When Z is MC And P L When the frequencies are equal, the zero poles exactly cancel, but R MC And R is L With variation of load, R is not uniform MC Inversely proportional to the overdrive voltage of the power tube, R L Inversely proportional to the square of the overdrive voltage of the power tube. Therefore, the stability compensation can only be applied to the condition of small load current when the current is as large as R MC And R is L When the gap is large, the LDO becomes unstable.
In addition, chinese patent CN 202110462U discloses an LDO based on a dynamic pole-zero tracking technique, and the dynamic zero generation mode is the same as that of the aforementioned patent CN111638742B, and the problems are the same.
Disclosure of Invention
The invention aims to solve the technical problem of providing a feedforward zero stability compensation LDO circuit, which adopts a feedforward circuit mode to introduce a medium-high frequency zero and compensate phase roll-off caused by poles.
The technical proposal adopted by the invention for solving the technical problems is that the feedforward zero point stability compensation LDO circuit comprises a primary amplifier, a secondary amplifier and a PMOS power tube, wherein the drain electrode of the PMOS power tube is used as the output end of the LDO to be grounded through a first resistor and a second resistor which are connected in series, the serial connection point of the first resistor and the second resistor is connected to the negative input end of the primary amplifier,
further comprises:
a grid electrode and a drain electrode of the fourth PMOS tube are connected with a first reference point, and a source electrode of the fourth PMOS tube is connected with a voltage input point;
the grid electrode of the first PMOS tube is connected with a first reference point, the source electrode of the first PMOS tube is connected with a voltage input point, and the drain electrode of the first PMOS tube is connected with the negative input end of the secondary amplifier;
the grid electrode of the second PMOS tube is connected with the first reference point, the source electrode of the second PMOS tube is connected with the voltage input point, the drain electrode of the second PMOS tube is connected with the positive input end of the secondary amplifier, and the drain electrode of the second PMOS tube is also connected with the first output end;
the grid electrode of the third PMOS tube is connected with the output end of the secondary amplifier, and the source electrode of the third PMOS tube is connected with the negative input end of the secondary amplifier;
the grid electrode of the third NMOS tube is connected with the second voltage input end, and the drain electrode of the third NMOS tube is connected with the drain electrode of the third PMOS tube;
the grid electrode of the first NMOS tube is grounded through a first capacitor, the source electrode of the first NMOS tube is grounded, and the drain electrode of the first NMOS tube is connected with the source electrode of the third NMOS tube;
the grid electrode of the fourth NMOS tube is connected with the second voltage input end, and the drain electrode of the fourth NMOS tube is connected with the positive input end of the secondary amplifier;
the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube, the source electrode of the second NMOS tube is grounded, the drain electrode of the second NMOS tube is connected with the source electrode of the fourth NMOS tube, the grid electrode of the second NMOS tube is also connected with the drain electrode of the third NMOS tube, and the grid electrode of the second NMOS tube is grounded through a first capacitor;
and the grid electrode of the fifth NMOS tube is connected with the output end of the primary amplifier, the source electrode of the fifth NMOS tube is grounded, and the drain electrode of the fifth NMOS tube is connected with the first reference point.
The circuit of the invention can realize the stability of the LDO with large bandwidth and rapid transient response. The invention generates a zero point of a middle frequency band at a middle and high frequency through the feedforward circuit, and the zero point compensates phase roll-off caused by an LDO pole. By adopting the invention, the LDO as compensation can realize stability without parasitic ESR resistance of a capacitor, and the overshoot voltage is less than 50mV when the LDO jumps from no load to heavy load (1A).
Drawings
Fig. 1 is a circuit diagram of a common prior art.
Fig. 2 is a circuit diagram of chinese patent CN 111638742B.
Fig. 3 is a circuit diagram of the present invention.
Detailed Description
See fig. 3. The respective numbers in fig. 3 are described as follows:
MPOWER: PMOS power tube
MP1: first PMOS tube
MP2: second PMOS tube
MP3: third PMOS tube
MP4: fourth PMOS tube
MN1: first NMOS tube
MN2: second NMOS tube
MN3: third NMOS tube
MN4: fourth NMOS tube
MN5: fifth NMOS tube
C1: first capacitor
EA: primary amplifier
A: secondary amplifier
R1: first resistor
R2: second resistor
R L : load resistor
C L : load capacitor
V OUT : LDO output end
V OUT1 : first outputEnd of the device
V A : first reference point
VB: a second voltage input terminal
VREF: reference voltage input terminal
VRB: feedback voltage input terminal
V IN : voltage input point
The feedforward zero point stability compensation LDO circuit comprises a primary amplifier EA, a secondary amplifier A and a PMOS power tube MPOWER, wherein the drain electrode of the PMOS power tube MPOWER is used as an LDO output end V OUT The first resistor R1 and the second resistor R2 which are connected in series are grounded, and the serial connection point of the first resistor R1 and the second resistor R2 is connected to the negative input end of the primary amplifier, and the method further comprises the following steps:
a fourth PMOS tube MP4 having its gate and drain connected to the first reference point and its source connected to the voltage input point V IN ；
The first PMOS tube MP1 has its gate connected to the first reference point and its source connected to the voltage input point V IN The drain electrode is connected with the negative input end of the secondary amplifier;
a second PMOS tube MP2 having a gate connected to the first reference point and a source connected to the voltage input point V IN The drain electrode is connected with the positive input end of the secondary amplifier, and the drain electrode is also connected with the first output end V OUT1 ；
The grid electrode of the third PMOS tube MP3 is connected with the output end of the secondary amplifier, and the source electrode of the third PMOS tube MP3 is connected with the negative input end of the secondary amplifier;
the grid electrode of the third NMOS tube MN3 is connected with the second voltage input end VB, and the drain electrode of the third NMOS tube MN3 is connected with the drain electrode of the third PMOS tube MP 3;
the grid electrode of the first NMOS tube MN1 is grounded through a first capacitor C1, the source electrode of the first NMOS tube MN1 is grounded, and the drain electrode of the first NMOS tube MN3 is connected with the source electrode of the third NMOS tube MN 3;
the grid electrode of the fourth NMOS tube MN4 is connected with the second voltage input end VB, and the drain electrode of the fourth NMOS tube MN4 is connected with the positive input end of the secondary amplifier;
the gate of the second NMOS transistor MN2 is connected with the gate of the first NMOS transistor MN1, the source is grounded, the drain is connected with the source of the fourth NMOS transistor MN4, the gate of the second NMOS transistor MN2 is also connected with the drain of the third NMOS transistor MN3, and the gate is grounded through the first capacitor C1.
In FIG. 3, R L And C L Representing load resistance and load capacitance.
The invention changes the structure of the output stage on the basis of the prior art, and the output stage is driven by a current mirror. Will first reference point V A Seen as an input to the driver stage, there are three different paths from the input to the output.
The first path is the input signal of the driving stage (the primary amplifier EA outputs to the first reference point V in the figure) A The signal of (a) is converted into a current signal by a first PMOS tube MP1, buffered by a third PMOS tube MP3, converted into a voltage signal by a diode-connected first NMOS tube MN1 (the branch is of an OTA structure), and amplified to a first output end V by a second NMOS tube MN2 OUT1 。
The second path is that the input signal of the driving stage is amplified to the first output end V by the second PMOS tube MP2 OUT1 . A first output terminal V OUT1 And LDO output terminal V OUT The third path is that the input signal of the driving stage is amplified to the output end V of the LDO by the PMOS power tube MPOWER by bonding the lead wire to the same PAD OUT . The input signals reach the output end through different paths to generate zero points at a certain frequency point, and the zero points are positioned on the left half plane or the right half plane and the size of the zero points are obtained through a calculation formula.
Wherein R is OUT For the LDO equivalent output impedance of the invention, V OUT G is the output voltage of LDO MP1 Transconductance g of the first PMOS tube MP2 The transconductance of the second PMOS tube; g MN1 Transconductance g of the first NMOS tube MN2 Transconductance g of the second NMOS tube MPOWER Is the transconductance of the PMOS power tube MPOWER.
In the invention, the current and the width-to-length ratio W/L of the first PMOS tube MP1 are consistent with those of the second PMOS tube MP2, so g MP1 Equal to g MP2 The method comprises the steps of carrying out a first treatment on the surface of the The current and the width-to-length ratio W/L of the first NMOS transistor MN1 are consistent with those of the second NMOS transistor MN2, so g MN1 Equal to g MN2 。
Based on the above design, the circuit transfer function can be reduced to the following formula.
The above equation is the frequency domain transfer function, the complex function, and the Laplace transform of the time function f (t) is denoted as H (S). The time domain variable t is a real number and the complex frequency domain H(s) variable s is a complex number. The variable S is also called "complex frequency". The Laplace transform establishes a relationship between the time domain and the complex frequency domain (S domain).
S=jw, where j is a complex unit, w=2pi f.
SC 1 Refers to S×C 1 ，C 1 Is the capacitance value of the first capacitor C1.
From the transfer function equation H (S), the feedforward compensation of this design produces a left half-plane zero and a left half-plane pole, the frequencies of the zero poles being f, respectively P1 ,f Z1 。
By designing the sizes of the PMOS power tube MPOWER, the first PMOS tube MP1 and the first NMOS tube MN1, the frequency of the zero is lower than that of the pole, and the frequency difference between the zero and the pole is kept large enough, so that the phase margin of the loop can be compensated through the zero.
In the feedforward path, a common gate tube, namely a third PMOS tube MP3, is adopted to buffer the leakage current of the first PMOS tube MP1, the third PMOS tube MP3 adopts a feedback structure, and the equivalent resistance seen from the source electrode of the third PMOS tube MP3 isA is output connected to MP3 pipe gridGain, g, of polar secondary amplifier MP3 Is the transconductance of the third PMOS tube MP3, so the first PMOS tube MP1 is opposite to the parasitic capacitance C GDMP1 The Miller effect of (2) is small, the pole frequency in the loop is higher, and the structure of the common-source common-gate is very suitable for high-frequency application. Experiments prove that the unit gain bandwidth of the LDO adopting the invention can reach more than 10M under the condition of loading 1A current.
Claims (2)
1. The PMOS power tube LDO circuit with feedforward zero point stability compensation comprises a primary amplifier (EA), a secondary amplifier (A) and a PMOS power tube (MPOWER), wherein the drain electrode of the PMOS power tube (MPOWER) is used as an LDO output end (V) OUT ) The series connection point of the first resistor (R1) and the second resistor (R2) is connected to the negative input end of the primary amplifier through the first resistor (R1) and the second resistor (R2) which are connected in series,
characterized by further comprising:
a fourth PMOS tube (MP 4) having its gate and drain connected to the first reference point (V A ) The source electrode is connected with the voltage input point (V IN ）；
A first PMOS tube (MP 1) with its gate connected to a first reference point (V A ) The source electrode is connected with the voltage input point (V IN ) The drain electrode is connected with the negative input end of the secondary amplifier;
a second PMOS tube (MP 2) with its gate connected to the first reference point (V A ) The source electrode is connected with the voltage input point (V IN ) The drain is connected to the positive input of the secondary amplifier, and the drain is also connected to the first output (V OUT1 ）；
The grid electrode of the third PMOS tube (MP 3) is connected with the output end of the secondary amplifier, and the source electrode of the third PMOS tube is connected with the negative input end of the secondary amplifier;
the grid electrode of the third NMOS tube (MN 3) is connected with the second voltage input end (VB), and the drain electrode of the third NMOS tube (MP 3) is connected with the drain electrode of the third PMOS tube;
the grid electrode of the first NMOS tube (MN 1) is grounded through a first capacitor (C1), the source electrode of the first NMOS tube is grounded, and the drain electrode of the first NMOS tube is connected with the source electrode of the third NMOS tube (MN 3);
a grid electrode of the fourth NMOS tube (MN 4) is connected with the second voltage input end (VB), and a drain electrode of the fourth NMOS tube is connected with the positive input end of the secondary amplifier;
the grid electrode of the second NMOS tube (MN 2) is connected with the grid electrode of the first NMOS tube (MN 1), the source electrode of the second NMOS tube is grounded, the drain electrode of the second NMOS tube is connected with the source electrode of the fourth NMOS tube (MN 4), the grid electrode of the second NMOS tube is also connected with the drain electrode of the third NMOS tube (MN 3), and the grid electrode of the second NMOS tube is grounded through a first capacitor (C1);
a fifth NMOS transistor (MN 5) having a gate connected to the output of the primary amplifier, a source connected to ground, and a drain connected to a first reference point (V A ）。
2. The PMOS power transistor LDO circuit of claim 1, wherein the first PMOS transistor (MP 1) and the second PMOS transistor (MP 2) have the same aspect ratio, and the first NMOS transistor (MN 1) and the second NMOS transistor (MN 2) have the same aspect ratio.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211186970.6A CN117452998B (en) | 2022-09-28 | 2022-09-28 | PMOS power tube LDO circuit with feedforward zero point stability compensation |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211186970.6A CN117452998B (en) | 2022-09-28 | 2022-09-28 | PMOS power tube LDO circuit with feedforward zero point stability compensation |
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| CN117452998A CN117452998A (en) | 2024-01-26 |
| CN117452998B true CN117452998B (en) | 2024-04-02 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20100005756A (en) * | 2008-07-08 | 2010-01-18 | 한양대학교 산학협력단 | Low dropout regulator with replica load |
| CN102063146A (en) * | 2011-01-21 | 2011-05-18 | 东南大学 | Adaptive frequency-compensation linear voltage stabilizer with low voltage difference |
| CN109460105A (en) * | 2018-12-24 | 2019-03-12 | 中国电子科技集团公司第五十八研究所 | A kind of dynamic zero pole point tracking and compensating circuit |
| CN113342108A (en) * | 2021-06-08 | 2021-09-03 | 成都华微电子科技有限公司 | Parallel operational amplifier zero compensation circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120212200A1 (en) * | 2011-02-22 | 2012-08-23 | Ahmed Amer | Low Drop Out Voltage Regulator |
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- 2022-09-28 CN CN202211186970.6A patent/CN117452998B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20100005756A (en) * | 2008-07-08 | 2010-01-18 | 한양대학교 산학협력단 | Low dropout regulator with replica load |
| CN102063146A (en) * | 2011-01-21 | 2011-05-18 | 东南大学 | Adaptive frequency-compensation linear voltage stabilizer with low voltage difference |
| CN109460105A (en) * | 2018-12-24 | 2019-03-12 | 中国电子科技集团公司第五十八研究所 | A kind of dynamic zero pole point tracking and compensating circuit |
| CN113342108A (en) * | 2021-06-08 | 2021-09-03 | 成都华微电子科技有限公司 | Parallel operational amplifier zero compensation circuit |
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| CN117452998A (en) | 2024-01-26 |
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