CN116130410A - Preparation method of interconnection structure - Google Patents

Preparation method of interconnection structure Download PDF

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Publication number
CN116130410A
CN116130410A CN202211258134.4A CN202211258134A CN116130410A CN 116130410 A CN116130410 A CN 116130410A CN 202211258134 A CN202211258134 A CN 202211258134A CN 116130410 A CN116130410 A CN 116130410A
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base layer
semiconductor base
groove
layer
forming
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王欢欢
刘欢
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National Center for Advanced Packaging Co Ltd
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National Center for Advanced Packaging Co Ltd
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Priority to CN202211258134.4A priority Critical patent/CN116130410A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a preparation method of an interconnection structure, which comprises the following steps: providing a first semiconductor base layer and a second semiconductor base layer; forming a first groove in a first semiconductor base layer with partial thickness; forming a first conductive element in the first groove; forming a second groove in a second semiconductor base layer with partial thickness; forming a second conductive element in the second groove; bonding the first and second conductive members together while bonding the first and second semiconductor substrates together; thinning one side surface of the first semiconductor base layer, which faces away from the second semiconductor base layer, until the first conductive piece is exposed; and thinning a side surface of the second semiconductor base layer, which faces away from the first semiconductor base layer, until the second conductive piece is exposed. The preparation method of the interconnection structure is not easy to cause the first semiconductor base layer and the second semiconductor base layer to crack, and the formed interconnection structure has higher depth-to-width ratio and higher conductivity.

Description

Preparation method of interconnection structure
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of an interconnection structure.
Background
The 3D-TSV integration technology is one of the microelectronic core technologies, and currently, among many new 3D packaging technologies, TSV technology is a key technology for multi-chip stacking integration and electrical interconnection in the 3D field, and has the following advantages: the interconnection length can be shortened to be equal to the thickness of the chip, so that the logic modules are vertically stacked to replace the horizontal distribution; delay and inductance effects are remarkably reduced, and the digital signal transmission speed and microwave transmission are improved; high density, high aspect ratio connections can be achieved, enabling complex multi-chip all-silicon system integration, densities many times higher than current physical packages for advanced multi-chip modules, while being more energy efficient, TSVs are expected to reduce power consumption of the chip by about 40%. However, due to process limitations, some current process steps can only be completed with aspect ratios less than 10:1, such as CVD insulating layer, PVD seed layer, and plating fill. If the aspect ratio is greater than 10:1 is difficult to achieve from the process and has the risk of cracking, and a new method for preparing the interconnection structure is needed.
Disclosure of Invention
Therefore, the technical problem to be solved by the invention is to overcome the defects that the preparation method of the interconnection structure in the prior art has the risk of cracking and the depth-to-width ratio of the formed interconnection structure is smaller, so that the preparation method of the interconnection structure is provided.
The invention provides a preparation method of an interconnection structure, which comprises the following steps: providing a first semiconductor base layer and a second semiconductor base layer; forming a first groove in a first semiconductor base layer with partial thickness; forming a first conductive element in the first groove; forming a second groove in a second semiconductor base layer with partial thickness; forming a second conductive element in the second groove; bonding the first and second conductive members together while bonding the first and second semiconductor substrates together; thinning one side surface of the first semiconductor base layer, which faces away from the second semiconductor base layer, until the first conductive piece is exposed; and thinning a side surface of the second semiconductor base layer, which faces away from the first semiconductor base layer, until the second conductive piece is exposed.
Optionally, the first semiconductor base layer has opposite first and second faces; the second semiconductor base layer has opposite third and fourth sides; before bonding the first semiconductor base layer and the second semiconductor base layer together, the first groove extends from the first face into a part of the first semiconductor base layer, and the second groove extends from the third face into a part of the second semiconductor base layer; the preparation method of the interconnection structure further comprises the following steps: forming a first passivation layer on the inner wall surface of the first groove and the first face around the first groove before forming the first conductive member; forming a second passivation layer on the inner wall surface of the second groove and a third face around the second groove before forming the second conductive member; bonding the first semiconductor base layer and the second semiconductor base layer together by bonding the first passivation layer and the second passivation layer; in the process of thinning the surface of one side of the first semiconductor base layer, which is away from the second semiconductor base layer, a first passivation layer between the first conductive piece and the second surface is removed; and removing the second passivation layer between the second conductive element and the fourth surface in the thinning process of the side surface of the second semiconductor base layer, which is away from the first semiconductor base layer.
Optionally, after the thinning treatment of the side surface of the first semiconductor base layer facing away from the second semiconductor base layer and before the thinning treatment of the side surface of the second semiconductor base layer facing away from the first semiconductor base layer, forming a first rewiring layer on the side surface of the first conductive element facing away from the second conductive element; and after the thinning treatment of the side surface of the second semiconductor base layer, which is away from the first semiconductor base layer, forming a second redistribution layer on the side surface of the second conductive piece, which is away from the first conductive piece.
Optionally, the method further comprises: providing a temporary carrier plate; bonding the first semiconductor base layer and the temporary carrier plate before thinning the side surface of the second semiconductor base layer, which is away from the first semiconductor base layer, after forming a first rewiring layer on the side surface of the first conductive element, which is away from the second conductive element; and after a second rewiring layer is formed on the surface of one side, away from the first conductive piece, of the second conductive piece, the temporary carrier plate is peeled off from the first semiconductor base layer.
Optionally, the ratio of the depth to the width of the first groove is 5:1 to 10:1.
optionally, the depth of the first groove is 20 micrometers to 200 micrometers; the width of the first groove is 2-50 microns.
Optionally, the ratio of the depth to the width of the second groove is 5:1 to 10:1.
optionally, the depth of the second groove is 20 micrometers-200 micrometers; the width of the second groove is 2-50 microns.
Optionally, the thickness of the first passivation layer is 0.1-5 micrometers; the thickness of the second passivation layer is 0.1-5 microns.
The technical scheme of the invention has the following advantages:
the invention provides a preparation method of an interconnection structure, which comprises the steps of providing a first semiconductor base layer and a second semiconductor base layer; forming a first groove in a first semiconductor base layer with partial thickness; forming a first conductive element in the first groove; forming a second groove in a second semiconductor base layer with partial thickness; forming a second conductive element in the second groove; bonding the first and second conductive members together while bonding the first and second semiconductor substrates together; the first conductive member and the second conductive member are directly bonded together to facilitate improving conductivity and aspect ratio of the interconnect structure. Thinning one side surface of the first semiconductor base layer, which faces away from the second semiconductor base layer, until the first conductive piece is exposed; and thinning the surface of the second semiconductor base layer, which is far away from the first semiconductor base layer, until the second conductive piece is exposed, bonding the first semiconductor base layer and the second semiconductor base layer together, and thinning the surface of the first semiconductor base layer, which is far away from the second semiconductor base layer, and thinning the surface of the second semiconductor base layer, which is far away from the first semiconductor base layer, so that cracking is avoided in the bonding process of the first semiconductor base layer and the second semiconductor base layer. Therefore, the preparation method of the interconnection structure is not easy to cause the first semiconductor base layer and the second semiconductor base layer to crack, and the formed interconnection structure has higher depth-to-width ratio and higher conductivity.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of a method for manufacturing an interconnection structure according to an embodiment of the present invention;
fig. 2 to fig. 9 are schematic structural diagrams illustrating a process for manufacturing an interconnection structure according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
The invention provides a preparation method of an interconnection structure, referring to fig. 1, comprising the following steps:
step S1: providing a first semiconductor base layer and a second semiconductor base layer;
step S2: forming a first groove in a first semiconductor base layer with partial thickness;
step S3: forming a first conductive element in the first groove;
step S4: forming a second groove in a second semiconductor base layer with partial thickness;
step S5: forming a second conductive element in the second groove;
step S6: bonding the first and second conductive members together while bonding the first and second semiconductor substrates together;
step S7: thinning one side surface of the first semiconductor base layer, which faces away from the second semiconductor base layer, until the first conductive piece is exposed;
step S8: and thinning a side surface of the second semiconductor base layer, which faces away from the first semiconductor base layer, until the second conductive piece is exposed.
In the method for manufacturing an interconnection structure provided in this embodiment, the first semiconductor base layer and the second semiconductor base layer are bonded together, and the first conductive member and the second conductive member are bonded together at the same time; the first conductive member and the second conductive member are directly bonded together to facilitate improving conductivity and aspect ratio of the interconnect structure. Thinning one side surface of the first semiconductor base layer, which faces away from the second semiconductor base layer, until the first conductive piece is exposed; and thinning the surface of the second semiconductor base layer, which is far away from the first semiconductor base layer, until the second conductive piece is exposed, bonding the first semiconductor base layer and the second semiconductor base layer together, and thinning the surface of the first semiconductor base layer, which is far away from the second semiconductor base layer, and thinning the surface of the second semiconductor base layer, which is far away from the first semiconductor base layer, so that cracking is avoided in the bonding process of the first semiconductor base layer and the second semiconductor base layer. Therefore, the preparation method of the interconnection structure is not easy to cause the first semiconductor base layer and the second semiconductor base layer to crack, and the formed interconnection structure has higher depth-to-width ratio and higher conductivity.
The method of manufacturing the interconnect structure is described in detail below with reference to fig. 2-9.
Referring to fig. 2 and 3 in combination, a first semiconductor base layer 1 and a second semiconductor base layer 2 are provided; forming a first groove C1 in a first semiconductor base layer 1 of a partial thickness; a first groove C1 is formed in the second semiconductor base layer 2 of a partial thickness.
In one embodiment, the first semiconductor base layer 1 has opposite first and second faces; the second semiconductor base layer 2 has opposite third and fourth faces; the first recess C1 extends from the first face into a part of the first semiconductor base layer 1 and the second recess C2 extends from the third face into a part of the second semiconductor base layer 2 before bonding the first semiconductor base layer 1 and the second semiconductor base layer 2 together.
In one embodiment, the process of forming the first recess C1 in the partial thickness first semiconductor base layer 1 includes a photolithography or dry etching process, and in other embodiments, the process of forming the first recess in the partial thickness first semiconductor base layer may further include other etching processes.
In one embodiment, the process of forming the second recess C2 in the partial thickness second semiconductor base layer 2 includes a photolithography or dry etching process, and in other embodiments, the process of forming the second recess in the partial thickness second semiconductor base layer may further include other etching processes.
In one embodiment, the thickness of the first semiconductor base layer 1 is 700 micrometers to 850 micrometers, for example 750 micrometers.
In one embodiment, the material of the first semiconductor base layer 1 comprises glass, silicon carbide or gallium arsenide; in other embodiments, the material of the first semiconductor base layer may also include other semiconductor materials.
In one embodiment, the thickness of the second semiconductor base layer 2 is 700 micrometers to 850 micrometers, for example 780 micrometers.
In one embodiment, the material of the second semiconductor base layer 2 comprises glass, silicon carbide or gallium arsenide; in other embodiments, the material of the second semiconductor base layer may also include other semiconductor materials.
In one embodiment, the ratio of the depth to the width of the first groove is 5:1 to 10:1, for example 6:1, if the ratio of the depth to the width of the first groove is less than 5:1, the depth-to-width ratio of the interconnection structure is improved to a small extent.
In one embodiment, the first grooves have a depth of 20 microns to 200 microns, such as 150 microns; if the depth of the first groove is smaller than 20 micrometers, the depth-to-width ratio of the interconnection structure is improved to a small extent; if the depth of the first groove is greater than 200 micrometers, the process difficulty is increased.
In one embodiment, the first grooves have a width of 2 microns to 50 microns, such as 30 microns; if the width of the first groove is smaller than 2 microns, the process difficulty is increased; if the width of the first groove is greater than 50 micrometers, the depth-to-width ratio of the interconnection structure is improved to a smaller extent.
In one embodiment, the ratio of the depth to the width of the second groove is 5:1 to 10:1, for example 6:1, if the ratio of the depth to the width of the second groove is less than 5:1, the depth-to-width ratio of the interconnection structure is improved to a small extent.
In one embodiment, the second grooves have a depth of 20 microns to 200 microns, such as 150 microns; if the depth of the second groove is smaller than 20 micrometers, the depth-to-width ratio of the interconnection structure is improved to a small extent; if the depth of the second groove is greater than 200 micrometers, the process difficulty is increased.
In one embodiment, the second grooves have a width of 2 microns to 50 microns, such as 25 microns; if the width of the second groove is smaller than 2 microns, the process difficulty is increased; if the width of the second groove is greater than 50 micrometers, the depth-to-width ratio of the interconnection structure is improved to a smaller extent.
Referring to fig. 4 and 5 in combination, a first conductive member 3 is formed in the first groove C1; a second conductive member 4 is formed in the second groove C2.
In one embodiment, the material of the first conductive element 3 comprises copper, and in other embodiments, the material of the first conductive element may also comprise other metals.
In one embodiment, the material of the second conductive element 4 comprises copper, and in other embodiments, the material of the second conductive element may also comprise other metals.
In one embodiment, the process of forming the first conductive member 3 in the first groove C1 includes a plating process, and the process of forming the second conductive member 4 in the second groove C2 includes a plating process.
With continued reference to fig. 4 and fig. 5, the method for preparing the interconnection structure further includes: before forming the first conductive member 3, forming a first passivation layer 5 on the inner wall surface of the first groove C1 and the first face around the first groove C1; before forming the second conductive member 4, a second passivation layer 6 is formed on the inner wall surface of the second groove C2 and the third face around the second groove C2.
In one embodiment, after forming the first passivation layer 5 on the inner wall surface of the first groove C1 and the first face around the first groove C1, before forming the first conductive member 3, it further includes: a first seed layer (not shown) is formed on the surface of the first passivation layer 5 on the inner wall surface of the first groove C1.
The first seed layer may improve the conductivity of the interconnection structure, which is beneficial to the formation of the first conductive element 3.
In one embodiment, after forming the second passivation layer 6 on the inner wall surface of the second groove C2 and the third face around the second groove C2, before forming the second conductive member 4, it further includes: a second seed layer (not shown) is formed on the surface of the second passivation layer 6 on the inner wall surface of the second groove C2.
The second seed layer may improve the conductivity of the interconnection structure, which is beneficial to the formation of the second conductive element 4.
In one embodiment, the process of forming the first passivation layer 5 includes a plasma enhanced chemical vapor deposition process; in other embodiments, the process of forming the first passivation layer may also include other deposition processes.
In one embodiment, the process of forming the second passivation layer 6 includes a plasma enhanced chemical vapor deposition process; in other embodiments, the process of forming the second passivation layer may also include other deposition processes.
In one embodiment, the first passivation layer 5 is silicon dioxide; in other embodiments, the material of the first passivation layer may also be other organic insulating materials or inorganic insulating materials, such as silicon nitride.
In one embodiment, the second passivation layer 6 is silicon dioxide; in other embodiments, the material of the second passivation layer may also be other organic insulating materials or inorganic insulating materials, such as silicon nitride.
In one embodiment, the thickness of the first passivation layer 5 is 0.1 to 5 microns, for example 0.5 microns; if the thickness of the first passivation layer is smaller than 0.1 micron, the oxidation or corrosion speed of the first conductive piece is retarded to a small extent; if the thickness of the first passivation layer is greater than 5 micrometers, the width of the formed first conductive member is too small, and the degree of improving the aspect ratio of the interconnection structure is small.
In one embodiment, the second passivation layer 6 has a thickness of 0.1 to 5 microns, for example 0.5 microns; if the thickness of the second passivation layer is less than 0.1 micron, the oxidation or corrosion speed of the second conductive element is retarded to a small extent; if the thickness of the second passivation layer is greater than 5 micrometers, the width of the formed second conductive member is too small, and the degree of improving the aspect ratio of the interconnection structure is small.
Referring to fig. 6, after the first conductive member 3 is formed in the first groove C1 and the second conductive member 4 is formed in the second groove C2, the first passivation layer 5 and the second passivation layer 6 are bonded together by bonding the first semiconductor base layer 1 and the second semiconductor base layer 2, and the first conductive member 3 and the second conductive member 4 are aligned to bond during the bonding of the first passivation layer 5 and the second passivation layer 6.
The first passivation layer 5 of the inner wall surface of the first groove C1 facilitates insulation between the first conductive member 3 and the first semiconductor base layer 1; the first passivation layer 5 of the first face around the first recess C1 facilitates the bonding between the first semiconductor base layer 1 and the second semiconductor base layer 2; the second passivation layer 6 of the inner wall surface of the second groove C2 facilitates insulation between the second conductive member 4 and the second semiconductor base layer 2; the second passivation layer 6 of the third face around the second recess C2 facilitates the bonding between the first semiconductor base layer 1 and the second semiconductor base layer 2.
The first conductive member 3 and the second conductive member 4 formed by the method for manufacturing an interconnection structure provided in this embodiment are directly bonded together, and the aspect ratio of the first conductive member 3 and the second conductive member 4 stacked together is greater than 10:1, the aspect ratio of the first conductive piece 3 and the second conductive piece 4 stacked together is large, the integration level of the interconnection structure is improved, the thickness of the formed interconnection structure is increased, and the strength of the interconnection structure is improved.
In one embodiment, bonding the first semiconductor base layer 1 and the second semiconductor base layer 2 together is performed under high temperature and high pressure, specifically, the temperature at which the first semiconductor base layer 1 and the second semiconductor base layer 2 are bonded together is 100 ℃ to 500 ℃, for example, 250 ℃; the pressure at which the first semiconductor base layer 1 and the second semiconductor base layer 2 are bonded together is 0.1KN to 50KN, for example 30KN.
Referring to fig. 7, after the first semiconductor base layer 1 and the second semiconductor base layer 2 are bonded together, a first passivation layer 5 between the first conductive member 3 and the second surface is removed during the thinning process of the side surface of the first semiconductor base layer 1 facing away from the second semiconductor base layer 2, and a first rewiring layer 7 is formed on the side surface of the first conductive member 3 facing away from the second conductive member 4 after the thinning process of the side surface of the first semiconductor base layer 1 facing away from the second semiconductor base layer 2 and before the thinning process of the side surface of the second semiconductor base layer 2 facing away from the first semiconductor base layer 1.
Referring to fig. 8, after the first redistribution layer 7 is formed on the side surface of the first conductive element 3 facing away from the second conductive element 4, the second redistribution layer 8 is formed on the side surface of the second conductive element 4 facing away from the first conductive element 3 after the thinning process is performed on the side surface of the second semiconductor base layer 2 facing away from the first semiconductor base layer 1, and the second passivation layer 6 between the second conductive element 4 and the fourth surface is removed during the thinning process on the side surface of the second semiconductor base layer 2 facing away from the first semiconductor base layer 1.
With continued reference to fig. 8, the method for preparing the interconnection structure further includes: providing a temporary carrier 100; bonding the first semiconductor base layer 1 and the temporary carrier 100 before the thinning treatment of the side surface of the second semiconductor base layer 2 facing away from the first semiconductor base layer 1 after the first rewiring layer 7 is formed on the side surface of the first conductive element 3 facing away from the second conductive element 4; referring to fig. 9, after the second re-wiring layer 8 is formed on the side surface of the second conductive member 4 facing away from the first conductive member 3, the temporary carrier plate 100 is peeled off from the first semiconductor base layer 1.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the invention.

Claims (9)

1. A method of fabricating an interconnect structure, comprising:
providing a first semiconductor base layer and a second semiconductor base layer;
forming a first groove in a first semiconductor base layer with partial thickness;
forming a first conductive element in the first groove;
forming a second groove in a second semiconductor base layer with partial thickness;
forming a second conductive element in the second groove;
bonding the first and second conductive members together while bonding the first and second semiconductor substrates together;
thinning one side surface of the first semiconductor base layer, which faces away from the second semiconductor base layer, until the first conductive piece is exposed;
and thinning a side surface of the second semiconductor base layer, which faces away from the first semiconductor base layer, until the second conductive piece is exposed.
2. The method of manufacturing an interconnect structure of claim 1, wherein the first semiconductor substrate has opposing first and second sides; the second semiconductor base layer has opposite third and fourth sides; before bonding the first semiconductor base layer and the second semiconductor base layer together, the first groove extends from the first face into a part of the first semiconductor base layer, and the second groove extends from the third face into a part of the second semiconductor base layer;
the preparation method of the interconnection structure further comprises the following steps: forming a first passivation layer on the inner wall surface of the first groove and the first face around the first groove before forming the first conductive member; forming a second passivation layer on the inner wall surface of the second groove and a third face around the second groove before forming the second conductive member;
bonding the first semiconductor base layer and the second semiconductor base layer together by bonding the first passivation layer and the second passivation layer;
in the process of thinning the surface of one side of the first semiconductor base layer, which is away from the second semiconductor base layer, a first passivation layer between the first conductive piece and the second surface is removed;
and removing the second passivation layer between the second conductive element and the fourth surface in the thinning process of the side surface of the second semiconductor base layer, which is away from the first semiconductor base layer.
3. The method for manufacturing an interconnection structure according to claim 1, wherein after the thinning treatment of the side surface of the first semiconductor base layer facing away from the second semiconductor base layer and before the thinning treatment of the side surface of the second semiconductor base layer facing away from the first semiconductor base layer, a first rewiring layer is formed on the side surface of the first conductive member facing away from the second conductive member; and after the thinning treatment of the side surface of the second semiconductor base layer, which is away from the first semiconductor base layer, forming a second redistribution layer on the side surface of the second conductive piece, which is away from the first conductive piece.
4. The method for manufacturing an interconnection structure according to claim 3, further comprising: providing a temporary carrier plate; bonding the first semiconductor base layer and the temporary carrier plate before thinning the side surface of the second semiconductor base layer, which is away from the first semiconductor base layer, after forming a first rewiring layer on the side surface of the first conductive element, which is away from the second conductive element; and after a second rewiring layer is formed on the surface of one side, away from the first conductive piece, of the second conductive piece, the temporary carrier plate is peeled off from the first semiconductor base layer.
5. The method of manufacturing an interconnect structure according to claim 1, wherein a ratio of a depth to a width of the first groove is 5:1 to 10:1.
6. the method of manufacturing an interconnect structure of claim 5, wherein the first grooves have a depth of 20 microns to 200 microns; the width of the first groove is 2-50 microns.
7. The method of manufacturing an interconnect structure according to claim 1, wherein the ratio of the depth to the width of the second groove is 5:1 to 10:1.
8. the method of manufacturing an interconnect structure of claim 7, wherein the depth of the second recess is 20 microns to 200 microns; the width of the second groove is 2-50 microns.
9. The method of manufacturing an interconnect structure of claim 2, wherein the first passivation layer has a thickness of 0.1 to 5 microns; the thickness of the second passivation layer is 0.1-5 microns.
CN202211258134.4A 2022-10-14 2022-10-14 Preparation method of interconnection structure Pending CN116130410A (en)

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CN202211258134.4A CN116130410A (en) 2022-10-14 2022-10-14 Preparation method of interconnection structure

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CN116130410A true CN116130410A (en) 2023-05-16

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