CN111799188B - Thinning wafer packaging technology utilizing TSV and TGV - Google Patents
Thinning wafer packaging technology utilizing TSV and TGV Download PDFInfo
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- CN111799188B CN111799188B CN202010694662.9A CN202010694662A CN111799188B CN 111799188 B CN111799188 B CN 111799188B CN 202010694662 A CN202010694662 A CN 202010694662A CN 111799188 B CN111799188 B CN 111799188B
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- 238000012536 packaging technology Methods 0.000 title description 4
- 238000004891 communication Methods 0.000 claims abstract description 58
- 239000010949 copper Substances 0.000 claims abstract description 55
- 239000011521 glass Substances 0.000 claims abstract description 36
- 229910052802 copper Inorganic materials 0.000 claims abstract description 29
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 24
- 238000009713 electroplating Methods 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 claims abstract description 11
- 230000010354 integration Effects 0.000 claims abstract description 10
- 238000012858 packaging process Methods 0.000 claims abstract description 7
- 238000003475 lamination Methods 0.000 claims abstract description 6
- 238000005516 engineering process Methods 0.000 claims description 22
- 239000000126 substance Substances 0.000 claims description 17
- 238000007747 plating Methods 0.000 claims description 15
- 208000014903 transposition of the great arteries Diseases 0.000 claims description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 238000005498 polishing Methods 0.000 claims description 5
- 238000007772 electroless plating Methods 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 241000724291 Tobacco streak virus Species 0.000 claims 11
- 229910052759 nickel Inorganic materials 0.000 claims 6
- 229910052737 gold Inorganic materials 0.000 claims 2
- 239000010410 layer Substances 0.000 description 14
- 238000010586 diagram Methods 0.000 description 11
- 238000000465 moulding Methods 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000000463 material Substances 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
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- 238000009413 insulation Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
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- 239000012634 fragment Substances 0.000 description 1
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- 238000007521 mechanical polishing technique Methods 0.000 description 1
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- 239000003960 organic solvent Substances 0.000 description 1
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- 230000002093 peripheral effect Effects 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
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- 238000011160 research Methods 0.000 description 1
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
Abstract
The invention discloses a thinning wafer packaging process utilizing TSV and TGV, which comprises the following steps: s1, bonding a glass carrier plate by a wafer, and manufacturing TSV communication holes on the back surface; s2, electroplating to form a Ni/Pd/Cu seed layer on the TSV communication holes; s3, filling Cu into the TSV communication holes; s4, making a wafer copper pillar bump; s5, electroplating a Ni/Pd/Au metal lamination; s6, manufacturing a TGV communication hole on the back surface of the glass carrier plate; s7, electroplating to form a Ni/Pd/Cu seed layer in the TGV communication holes, and S8, filling Cu into the TGV communication holes and forming copper pillar bumps; s9, forming RDL on the back surface of the glass carrier plate; s10, etching to remove redundant Ni/Pd/Cu seed layers; s11, electroplating a Ni/Pd/Au metal lamination on the surface of the copper pillar bump of the glass carrier plate; s12, connecting the communication holes of the TSV and the TGV with the Clip or the Board respectively to complete the 3D architecture. The invention does not need the TSV/TGV flat hole filling electroplating of Cu CMP working procedure, the front and the back of the invention respectively complete the connection of the TSV and the TGV communication holes to manufacture double-sided wiring connection, and the Clip or the Board can be welded up and down to complete the 3D architecture with high integration and low delay conduction.
Description
Technical Field
The invention relates to the field of wafer processing, in particular to a thinning wafer packaging process utilizing TSV and TGV.
Background
With the rise of communication electronics, there is an increasing demand for miniaturized and high-sensitivity modules or systems, and the demand for signal quality is also increasing. High-density integrated technologies, such as System-in-Package (SiP), have been rapidly developed, but miniaturized integrated packages of mixed-signal multi-chip systems have become one of the technical difficulties in the field. In addition to technologies such as three-dimensional chip stacking (Stacked Die package), package stacking (Package on Package, POP), and the like, new materials and new technologies are applied to package miniaturization, such as flexible substrates, through silicon via (Through Silicon Via, TSV) interposer technologies, and glass via (Through Glass Via, TGV) interposer technologies, which are one of hot research directions for vertical 3D interconnection.
The through silicon via (Through Silicon Via, TSV) technology is a high-density packaging technology, and is being considered as a fourth generation packaging technology, as it gradually replaces the more mature wire bonding technology in the prior art. The TSV technology realizes vertical electrical interconnection of through-silicon vias by filling conductive substances such as copper, tungsten, polysilicon, and the like. The through silicon via technology can reduce interconnection length, signal delay, capacitance/inductance, low power consumption and high-speed communication between chips, increase broadband and realize miniaturization of device integration through vertical interconnection.
The glass material and the ceramic material have no free moving charges, have excellent dielectric property, have a thermal expansion coefficient close to that of silicon, and the glass through hole (Through Glass Via, TGV) technology of replacing the silicon material with glass can avoid the problem of poor TSV insulation, so that the method is an ideal three-dimensional integration solution. The Glass Via (TGV) technology is considered as a key technology for the next generation of three-dimensional integration, and the core of the technology is a deep hole forming process. In addition, the TGV technology does not need to manufacture an insulating layer, and reduces the process complexity and the processing cost. TGV and related technology have wide application prospect in optical communication, radio frequency, microwave, micro-electromechanical system, micro-fluidic device and three-dimensional integration fields.
Conventional ECP techniques fill the through-silicon vias (TSVs) or TGVs, and then CMP chemical mechanical polishing techniques are used to remove the metal layer from the outer surface of the via after filling the metal through-silicon vias (TSVs) to planarize the via filling, but in ultra-thin wafer or glass carrier structures, CMP is used to limit the thickness of the substrate, which can cause stress non-uniformity and chipping or mechanical damage if too thin.
Disclosure of Invention
In order to solve the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a process for packaging a thinned wafer by using TSVs and TGVs, which uses electroless plating for contact and barrier layers, and provides a seed layer for electroplating copper later, which can fill the through holes of the TSVs or TGVs by electrode plating, which can form RDLs or raised Post and PAD by yellow light patterns, which can remove the photoresist before packaging wires are connected, and which can form perfect fusion bonding to external wires by coating of electroless Ni/Pd/Au metal stacks.
The aim of the invention can be achieved by the following technical scheme:
a thinned wafer packaging process utilizing TSV and TGV, comprising the steps of:
s1, bonding a glass carrier plate on the front surface of a wafer, finishing back surface thinning, and manufacturing TSV communication holes on the back surface of the wafer through a yellow light process or a Laser perforation combined etching technology;
s2, chemically plating a Ni/Pd/Cu seed layer on the side wall and the bottom of the TSV communication hole;
s3, filling Cu into the TSV communication holes by using electrode electroplating, and polishing the back surface of the wafer by Chemical Mechanical Planarization (CMP) to finish the TSV communication hole filling;
s4, coating photoresist on the back surface of the wafer, and making a wafer copper Pillar bump Cu Pillar at the position of the back surface of the wafer corresponding to the TSV communication hole through an ECP process;
s5, performing chemical plating on the surface of the wafer copper Pillar bump Cu Piclar to form a Ni/Pd/Au Metal Stack, and completing TSV through hole communication;
s6, manufacturing a TGV communication hole on the back surface of the glass carrier plate through a yellow light process or a Laser perforation combined etching technology;
s7, forming a Ni/Pd/Cu Seed layer on the surface of the glass carrier plate and the side wall and the bottom of the TGV communication hole by using chemical plating,
s8, coating photoresist on the surface of the glass carrier plate, and filling Cu into the TGV communication holes by using electrode electroplating to form copper Pillar bumps Cu Pillar;
s9, forming a RDL circuit pattern on the back surface of the glass carrier plate through a yellow light process;
s10, removing the photoresist, and etching to remove the Ni/Pd/Cu Seed layer outside the Cu Picllar coverage area of the copper Pillar bump on the back of the glass carrier plate;
s11, performing electroless chemical plating on the surface of the copper Pillar bump Cu Piclar of the glass carrier plate to form Ni/Pd/Au metal lamination coverage, and completing TGV through hole communication;
and S12, after the manufacture of the communication hole connecting lines of the TSV and the TGV is completed, the communication hole connecting lines of the TSV and the TGV are respectively welded with a Clip or a Board, and the 3D framework with high integration and low delay conduction is completed.
Preferably, the TSV via in step S1 is connected to a metal layer of copper or aluminum on the front surface of the wafer, which has been completed with sidewall insulation Sidewall Passivation, and electroless plating may be performed.
Preferably, the TGV communication holes are connected to the wafer front PAD in the step S6.
Preferably, the Ni/Pd/Cu Seed layer thickness is less than 1um.
The invention has the beneficial effects that:
1. the invention does not need the TSV/TGV flat hole filling electroplating of Cu CMP (chemical mechanical polishing) process, overcomes the problem that the thickness of a substrate is limited by adopting CMP, and if the substrate is too thin, fragments or mechanical damage can be caused by uneven stress.
2. The invention can respectively complete the connection of the TSV and the TGV through holes on the front and the back, can be welded with the Clip or the Board up and down, can complete a 3D framework with high integration and low delay conduction, can connect the upper and the lower (front and the back) different components, can increase the integration degree and reduce the speed delay caused by the connection of the lead.
Drawings
The invention is further described below with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a TSV and TGV combined package structure according to the present invention;
FIG. 2 is an enlarged schematic view of the invention at position A of FIG. 1;
FIG. 3 is an enlarged schematic view of the present invention at position B of FIG. 1;
FIG. 4 is a schematic diagram of the molding structure of step S1 of the present invention;
FIG. 5 is a schematic diagram of the molding structure of step S2 of the present invention;
FIG. 6 is a schematic diagram of the molding structure of step S3 of the present invention;
FIG. 7 is a schematic diagram of the molding structure of step S4 of the present invention;
FIG. 8 is a schematic diagram of the molding structure of step S5 of the present invention;
FIG. 9 is a schematic diagram of the molding structure of step S6 of the present invention;
FIG. 10 is a schematic diagram of the molding structure of step S7 of the present invention;
FIG. 11 is a schematic diagram of the molding structure of step S8 of the present invention;
FIG. 12 is a schematic diagram of the molding structure of step S10 of the present invention;
fig. 13 is a schematic diagram of the molding structure of step S11 of the present invention.
In the figure:
1-thinning wafer, 2-glass carrier plate, 3-adhesive layer, 4-TSV communication hole, 5-Ni/Pd/Cu Seed layer, 6-filling Cu, 7-copper Pillar bump Cu Picler, 8-Ni/Pd/Au Metal laminated Metal Stack,9-TGV communication hole.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be understood that the terms "open," "upper," "lower," "thickness," "top," "middle," "length," "inner," "peripheral," and the like indicate orientation or positional relationships, merely for convenience in describing the present invention and to simplify the description, and do not indicate or imply that the components or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention.
Example 1
A thinned wafer packaging process utilizing TSVs, comprising the steps of:
s1, RDL wiring is conducted on the front side of a wafer through a yellow light process, then the front side of the wafer is bonded with a glass carrier plate, back side thinning is completed, and TSV communication holes are manufactured on the back side of the wafer through the yellow light process or a Laser perforation combined etching technology;
s2, chemically plating a Ni/Pd/Cu seed layer on the side wall and the bottom of the TSV communication hole;
s3, filling Cu into the TSV communication holes by using electrode electroplating, and polishing the back surface of the wafer through Chemical Mechanical Planarization (CMP), so as to finish the TSV communication hole filling;
s4, coating photoresist on the back surface of the wafer, and making a wafer copper Pillar bump Cu Pillar at the position of the back surface of the wafer corresponding to the TSV communication hole through an ECP process;
s5, performing chemical plating on the surface of the wafer copper Pillar bump Cu Piclar to form a Ni/Pd/Au Metal Stack, and completing TSV through hole communication;
s6, after the TSV through holes are communicated, packaging bonding or RDL wiring is carried out, and then the TSV through holes are communicated to other chips or PCBs by using a Solder ball Solder Bump;
s7, fixing the thinned wafer on a cutting film frame, performing de-bonding in a Laser/UV/thermal mode, and then turning over to remove the glass carrier plate;
s8, removing the adhesive agent from the thinned wafer by using an organic solvent on the dicing film frame, and then performing dicing and subsequent packaging engineering.
Example 2
A thinned wafer packaging process utilizing TSV and TGV, comprising the steps of:
s1, RDL wiring is conducted on the front side of a wafer through a yellow light process, then the front side of the wafer is bonded with a glass carrier plate, back side thinning is completed, and TSV communication holes are manufactured on the back side of the wafer through the yellow light process or a Laser perforation combined etching technology;
s2, chemically plating a Ni/Pd/Cu seed layer on the side wall and the bottom of the TSV communication hole;
s3, filling Cu into the TSV communication holes by using electrode electroplating, and polishing the back surface of the wafer through Chemical Mechanical Planarization (CMP), so as to finish the TSV communication hole filling;
s4, coating photoresist on the back surface of the wafer, and making a wafer copper Pillar bump Cu Pillar at the position of the back surface of the wafer corresponding to the TSV communication hole through an ECP process;
s5, performing chemical plating on the surface of the wafer copper Pillar bump Cu Piclar to form a Ni/Pd/Au Metal Stack, and completing TSV through hole communication;
s6, manufacturing a TGV communication hole on the back surface of the glass carrier plate through a yellow light process or a Laser perforation combined etching technology;
s7, forming a Ni/Pd/Cu Seed layer on the surface of the glass carrier plate and the side wall and the bottom of the TGV communication hole by using chemical plating,
s8, coating photoresist on the surface of the glass carrier plate, and filling Cu into the TGV communication holes by using electrode electroplating to form copper Pillar bumps Cu Pillar;
s9, forming a RDL circuit pattern on the back surface of the glass carrier plate through a yellow light process;
s10, removing the photoresist, and etching to remove the Ni/Pd/Cu Seed layer outside the Cu Picllar coverage area of the copper Pillar bump on the back of the glass carrier plate;
s11, performing electroless chemical plating on the surface of the copper Pillar bump Cu Piclar of the glass carrier plate to form Ni/Pd/Au metal lamination coverage, and completing TGV through hole communication;
and S12, after the manufacture of the communication hole connecting lines of the TSV and the TGV is completed, the communication hole connecting lines of the TSV and the TGV are respectively welded with a Clip or a Board, and the 3D framework with high integration and low delay conduction is completed.
In the description of the present specification, the descriptions of the terms "one embodiment," "example," "specific example," and the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing has shown and described the basic principles, principal features and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the present invention, and various changes and modifications may be made without departing from the spirit and scope of the invention, which is defined in the appended claims.
Claims (2)
1. A thinned wafer packaging process utilizing TSVs and TGVs, comprising the steps of:
s1, RDL wiring is conducted on the front side of a wafer through a yellow light process, then the front side of the wafer is bonded with a glass carrier plate, back side thinning is completed, and TSV communication holes are manufactured on the back side of the wafer through the yellow light process or a Laser perforation combined etching technology;
s2, chemically plating Ni, pd and Cu seed layers on the side walls and the bottoms of the TSV communication holes;
s3, filling Cu into the TSV communication holes by using electrode electroplating, and polishing the back surface of the wafer through Chemical Mechanical Planarization (CMP), so as to finish the TSV communication hole filling;
s4, coating photoresist on the back surface of the wafer, and making a wafer copper pillar bump on the back surface of the wafer at a position corresponding to the TSV communication hole through an ECP process;
s5, carrying out chemical plating on the surface of the wafer copper pillar bump to form a Ni, pd and Au metal lamination, and completing TSV through hole communication;
s6, manufacturing a TGV communication hole on the back surface of the glass carrier plate through a yellow light process or a Laser perforation combined etching technology;
s7, forming Ni, pd and Cu seed layers on the surface of the glass carrier and the side wall and the bottom of the TGV communication hole by using chemical plating,
s8, coating photoresist on the surface of the glass carrier plate, and filling Cu into the TGV communication holes by using electrode electroplating to form copper pillar bumps;
s9, forming a RDL circuit pattern on the back surface of the glass carrier plate through a yellow light process;
s10, removing the photoresist, and etching to remove the Ni, pd and Cu seed layers outside the copper pillar bump coverage area on the back of the glass carrier plate;
s11, electroless plating is carried out on the surface of the copper pillar bump of the glass carrier plate to form Ni, pd and Au metal lamination coverage, and TGV through hole communication is completed;
s12, after the manufacture of the communication hole connecting lines of the TSV and the TGV is completed, the communication hole connecting lines of the TSV and the TGV are welded with clips or boards respectively, and a 3D framework with high integration and low delay conduction is completed;
in the step S1, the TSV communication hole is connected to a metal layer of copper or aluminum on the front surface of the wafer, and the metal layer is insulated on the side wall and can be subjected to chemical plating;
the TGV communication holes are connected to the wafer front PAD in the step S6.
2. The thinned wafer packaging process utilizing TSV and TGV of claim 1 wherein the Ni, pd and Cu seed layers are less than 1um thick.
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| CN112687618A (en) * | 2020-12-23 | 2021-04-20 | 绍兴同芯成集成电路有限公司 | Wafer packaging method and wafer packaging assembly |
| CN116454020B (en) * | 2023-03-22 | 2024-02-09 | 苏州森丸电子技术有限公司 | Buried high-flatness TGV interconnection process and TGV interconnection structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102270603A (en) * | 2011-08-11 | 2011-12-07 | 北京大学 | Manufacturing method of silicon through hole interconnect structure |
| CN103474394A (en) * | 2013-09-11 | 2013-12-25 | 华进半导体封装先导技术研发中心有限公司 | TSV process method without metal CMP |
| CN103700621A (en) * | 2013-12-27 | 2014-04-02 | 华进半导体封装先导技术研发中心有限公司 | Method for etching vertical glass through holes with high depth-to-width ratios |
| CN104867892A (en) * | 2014-02-20 | 2015-08-26 | 阿尔特拉公司 | Silicon-glass hybrid interposer circuitry |
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| JP2014236102A (en) * | 2013-05-31 | 2014-12-15 | 凸版印刷株式会社 | Wiring board with through electrode, manufacturing method of the same, and semiconductor device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102270603A (en) * | 2011-08-11 | 2011-12-07 | 北京大学 | Manufacturing method of silicon through hole interconnect structure |
| CN103474394A (en) * | 2013-09-11 | 2013-12-25 | 华进半导体封装先导技术研发中心有限公司 | TSV process method without metal CMP |
| CN103700621A (en) * | 2013-12-27 | 2014-04-02 | 华进半导体封装先导技术研发中心有限公司 | Method for etching vertical glass through holes with high depth-to-width ratios |
| CN104867892A (en) * | 2014-02-20 | 2015-08-26 | 阿尔特拉公司 | Silicon-glass hybrid interposer circuitry |
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