CN116072707A - Planar SiC MOSFET containing rare earth gate dielectric layer and manufacturing method thereof - Google Patents
Planar SiC MOSFET containing rare earth gate dielectric layer and manufacturing method thereof Download PDFInfo
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- 229910052761 rare earth metal Inorganic materials 0.000 title claims abstract description 62
- 150000002910 rare earth metals Chemical class 0.000 title claims abstract description 62
- 238000004519 manufacturing process Methods 0.000 title abstract description 6
- 238000000034 method Methods 0.000 claims abstract description 41
- 229910052751 metal Inorganic materials 0.000 claims abstract description 37
- 239000002184 metal Substances 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 29
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 26
- 238000000151 deposition Methods 0.000 claims description 15
- 238000005468 ion implantation Methods 0.000 claims description 14
- 238000000231 atomic layer deposition Methods 0.000 claims description 11
- 238000005566 electron beam evaporation Methods 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 10
- 238000002161 passivation Methods 0.000 claims description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 230000003247 decreasing effect Effects 0.000 claims description 5
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 238000001704 evaporation Methods 0.000 claims description 3
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- 230000005684 electric field Effects 0.000 abstract description 20
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 40
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- 230000003071 parasitic effect Effects 0.000 description 4
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- 238000005240 physical vapour deposition Methods 0.000 description 4
- 150000001768 cations Chemical class 0.000 description 3
- 239000002131 composite material Substances 0.000 description 3
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- 230000001105 regulatory effect Effects 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
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- 238000010894 electron beam technology Methods 0.000 description 1
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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Abstract
The invention discloses a planar SiC MOSFET containing a rare earth gate dielectric layer and a manufacturing method thereof. Wherein, the structure includes: a metal layer, a substrate; the buffer area is arranged at the upper part of the substrate and comprises a plurality of buffer layers; the epitaxial layer is arranged at the upper part of the buffer area; the P well regions are arranged on two sides of the upper part of the epitaxial layer, and JFET regions are formed in the middle of the P well regions; the upper part of the P well region is provided with a super junction region; and a gate oxide layer region and the like which are in contact with the JFET region, the P-well region and the superjunction region are arranged at the upper part of the JFET region. The invention combines the method of the multi-buffer layer, the P+/N+ super junction structure and the gate oxide layer region structure; the peak electric field is transferred by utilizing the structure of the multiple buffer layers, so that the capacity of the device for bearing cosmic rays is improved, the influence of Krik effect of the device on the N+ source region, the P well region and the N-BJT device structure is eliminated, and the effect of improving the radiation resistance of the device is further achieved; the super junction structure of P+/N+ at the lower section of the source electrode is utilized to effectively reduce the contact resistance, reduce the loss of the device and regulate and control the electric field distribution condition of the device.
Description
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to a planar SiC MOSFET containing a rare earth gate dielectric layer and a manufacturing method thereof.
Background
MOSFETs are a type of switching device that can control large currents and voltages with small voltages, and this feature is widely used in analog circuits and digital circuits. After the grid voltage of the device reaches the threshold voltage, holes at the P well region position form a corresponding N channel under the action of reverse voltage, and the source electrode and the drain electrode are connected to form a conducting state.
Due to the nature of the material itself, si devices perform poorly in some extreme environments (e.g., high temperature, high pressure, high power, and high radiation), failing to meet the needs of the relevant application. The third generation semiconductor material silicon carbide (SiC) overcomes the defects of small band gap, low critical breakdown field strength, low thermal conductivity and the like of Si materials by the excellent physical characteristics, and becomes an ideal material for replacing Si. Silicon carbide (SiC) has a wide band gap, a high critical electric field, and a high thermal conductivity, and is the most promising material for next-generation power device applications.
At present, the cell size of the SiC MOSFET device is reduced along with the continuous reduction of the size of the power device, and the thickness of the gate oxide layer of the device is also reduced along with the continuous reduction of the size of the power device. When the thickness of the gate oxide is reduced to some extent, tunneling may occur in the SiC MOSFET device at the gate location, and in order to maintain the stability of the device gate, a high dielectric constant (high K) oxide layer is typically introduced in the prior art as the gate oxide of the device, with the most common high K oxide comprising Al 2 O 3 ，HfO 2 ，TiO 2 Etc. Due to the fact that in Al 2 O 3 /SiO 2 The dipole layer at the interface will have unavoidable effect on threshold voltage, when the gate oxide layer of the SiC MOSFET device is Al 2 O 3 /SiO 2 At this time, the threshold voltage of the SiC MOSFET device will fluctuate significantly. Therefore, how to improve the stability of the threshold voltage of the SiC MOSFET device is a technical problem to be overcome. Secondly, the prior SiC MOSFET device has higher peak field intensity and higher current density, and the characteristics lead the device to beIs susceptible to cosmic radiation inducers. Specifically, when the ray particles penetrate the device, a large number of electron hole pairs are generated by collision between the particles and the crystal lattice, and the phenomenon that a peak electric field is transferred to an epitaxial layer and a drift layer occurs in the device under the conditions of high temperature, high pressure and high current. The collection of a large number of holes and electrons will cause the peak electric field, temperature, etc. of the device to further rise, and at the same time, more electron-hole pairs are excited, so that the device burns out. How to reduce the shift of the peak electric field under the condition of large current is a technical difficulty to be overcome. In addition, the contact performance between the source metal layer and the n+ source region of the SiC MOSFET device is relatively poor. Therefore, how to improve the source contact performance of the device is also a technical problem to be solved.
Disclosure of Invention
In view of the above, the present invention is directed to a planar SiC MOSFET including a rare-earth gate dielectric layer and a method for manufacturing the same, a method for combining a Multi-buffer layer (P+/N+ super junction structure and a gate oxide layer region structure; the structure of the multi-buffer layer is utilized to further transfer the peak electric field, so that the capacity of the device for bearing cosmic rays is improved, the influence of Krik effect of the device on the N+ source region, the P well region and the N-BJT device structure is eliminated, and the effect of improving the radiation resistance of the device is further achieved; the super junction structure of P+/N+ at the lower section of the source electrode is utilized to effectively reduce the contact resistance, reduce the loss of the device and regulate and control the electric field distribution condition of the device.
According to one aspect of the invention, there is provided a planar SiC MOSFET including a rare earth-containing gate dielectric layer, comprising a buffer region disposed on an upper portion of a substrate, comprising a plurality of buffer layers; the epitaxial layer is arranged at the upper part of the buffer area; the P well regions are arranged on two sides of the upper part of the epitaxial layer, and JFET regions are formed in the middle of the P well regions; the upper part of the P well region is provided with a super junction region; the upper part of the JFET region is provided with a gate oxide layer region which is in contact with the JFET region, the P-well region and the superjunction region; the gate oxide layer region comprises a plurality of rare earth gate oxide layers; the upper part of the gate oxide layer area is sequentially provided with a gate metal layer, a passivation layer covering the gate oxide layer area and the gate metal layer; and the upper part of the super junction region is covered with a source metal layer.
According to another aspect of the present invention, there is provided a method for manufacturing a planar SiC MOSFET having a rare earth gate dielectric layer, the method comprising: step 101, evaporating the back of an N-type SiC substrate by adopting an electron beam evaporation mode to obtain a drain metal layer 1, and then obtaining ohmic contact by utilizing a rapid annealing process; step 102, epitaxially obtaining a buffer region of N-type SiC on the top of the SiC substrate; step 103, epitaxially obtaining an epitaxial layer of N-type SiC at the upper part of the buffer zone; 104, preparing a corresponding P well region and a super junction region on the epitaxial layer by utilizing an ion implantation mode to form a corresponding JFET region; step 105, depositing the required rare earth gate oxide regions on the upper parts of the JFET region, the P well region and the super junction region; step 106, depositing a corresponding SiC MOSFET grid on the rare earth grid oxide region by utilizing a photoetching and electron beam evaporation mode; step 107, depositing corresponding source metal layers on the upper parts of the P+ source region and part of the N+ source region by utilizing a photoetching and electron beam evaporation mode; and 108, depositing a passivation layer between the source metal layer and the gate metal layer by using a photoetching and MOCVD growth mode.
It can be found that the invention combines the Multi-buffer layer, the P+/N+ super junction structure and the three rare earth gate dielectric layers (Al 2 O 3 /Gd 2 O 3 /SiO 2 ) A method of construction; the structure of the multi-buffer layer is utilized to further transfer the peak electric field, so that the capacity of the device for bearing cosmic rays is improved, the influence of Krik effect of the device on the N+ source region, the P well region and the N-BJT device structure is eliminated, and the effect of improving the radiation resistance of the device is further achieved; the super junction structure of P+/N+ at the lower section of the source electrode is utilized to effectively reduce the contact resistance, reduce the loss of the device and regulate and control the electric field distribution condition of the device. With a three-layer rare earth oxide composite structure (Al 2 O 3 /Gd 2 O 3 /SiO 2 ) Gd is used as a gate dielectric layer 2 O 3 The attraction of Gd cations to oxygen atoms can effectively reduce the Al content of the high-k gate dielectric layer 2 O 3 /SiO 2 The resulting dipole layer affects the threshold voltage while maintaining the high dielectric constant state of the device gate oxide. Between source and drainAnd the structural design of the multi-layer buffer layer. The structure of the multi-layer buffer layer can be used for effectively dispersing the distribution condition of peak electric fields of the source electrode and the drain electrode under the breakdown condition, so that the capacity of the device for bearing cosmic rays is improved, the influence of Krik effect of a parasitic BJT device structure formed by an N+ well region and an N-is eliminated, and the effect of improving the radiation resistance of the device is further achieved. A p+/n+ structure is used at the location where it contacts the source metal layer. The P+/N+ super junction structure can effectively reduce the source electrode contact resistance of the device, simultaneously effectively reduce the working temperature of the device in the working process, simultaneously further reduce the size of the device and improve the integration of the device. The gate oxide layer adopts Al 2 O 3 /Gd 2 O 3 /SiO 2 Is a structural design of the device. By rare earth oxide Gd 2 O 3 For Al 2 O 3 /SiO 2 Attraction of dipoles (oxygen vacancies) at interface locations to cause Al 2 O 3 /SiO 2 The dipole concentration at the interface is obviously reduced, and the fluctuation of the threshold voltage of the device is effectively restrained.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of a preferred embodiment of the present invention;
FIG. 2 is a schematic diagram of a buffer structure in a preferred embodiment of the present invention, step 1;
FIG. 3 is a schematic diagram of a buffer structure process step 2.1 in a preferred embodiment of the present invention;
FIG. 4 is a schematic diagram of a buffer structure process step 2.2 in a preferred embodiment of the present invention;
FIG. 5 is a schematic diagram of a buffer structure process step 2.3 in a preferred embodiment of the present invention;
FIG. 6 is a schematic diagram of a P+/N+ superjunction process step 4.1 in a preferred embodiment of the present invention;
FIG. 7 is a schematic diagram of a P+/N+ superjunction process step 4.2 in a preferred embodiment of the present invention;
FIG. 8 is a schematic diagram of a P+/N+ superjunction process step 4.3 in a preferred embodiment of the present invention;
FIG. 9 is a schematic diagram of a gate oxide structure process step 5.1 in a preferred embodiment of the present invention;
FIG. 10 is a schematic diagram of a gate oxide structure process step 5.2 in a preferred embodiment of the present invention;
FIG. 11 is a schematic diagram of a gate oxide structure process step 5.3 in a preferred embodiment of the present invention;
FIG. 12 is a schematic diagram of a gate oxide structure process step 5.4 in a preferred embodiment of the present invention;
fig. 13 is a schematic diagram of a source, gate, passivation layer process step 7 in a preferred embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is specifically noted that the following examples are only for illustrating the present invention, but do not limit the scope of the present invention. Likewise, the following examples are only some, but not all, of the examples of the present invention, and all other examples, which a person of ordinary skill in the art would obtain without making any inventive effort, are within the scope of the present invention.
The invention provides a planar SiC MOSFET containing a rare earth gate dielectric layer, and a method for combining a multi-buffer layer, a P+/N+ super junction structure and a three-layer rare earth gate dielectric layer structure; the structure of the multi-buffer layer is utilized to further transfer the peak electric field, so that the capacity of the device for bearing cosmic rays is improved, the influence of Krik effect of the device in an N+ well region and an N-BJT device structure is eliminated, and the effect of improving the radiation resistance of the device is further achieved; the super junction structure of P+/N+ at the lower section of the source electrode is utilized to effectively reduce the contact resistance, reduce the loss of the device and regulate and control the electric field distribution condition of the device.
The structure comprises a buffer area arranged on the upper part of a substrate and a plurality of buffer layers; the epitaxial layer is arranged at the upper part of the buffer area; the P well regions are arranged on two sides of the upper part of the epitaxial layer, and JFET regions are formed in the middle of the P well regions; the upper part of the P well region is provided with a super junction region; the upper part of the JFET region is provided with a gate oxide layer region which is in contact with the JFET region, the P-well region and the superjunction region; the gate oxide layer region comprises a plurality of rare earth gate oxide layers; the upper part of the gate oxide layer area is sequentially provided with a gate metal layer, a passivation layer covering the gate oxide layer area and the gate metal layer; and the upper part of the super junction region is covered with a source metal layer.
As a preferred embodiment, please refer to fig. 1 in particular. The structure in this embodiment includes: a substrate 2; a drain metal layer 1 located at the lower part of the substrate; the buffer areas 3, 4 and 5 are positioned at the upper part of the substrate 2 and are arranged between the substrate 2 and the epitaxial layer 6, and the concentrations of the substrate 2, the buffer areas 3, 4 and 5 and the epitaxial layer 6 are sequentially decreased in a decreasing manner, and the direction is from the substrate 2 to the epitaxial layer 6; an epitaxial layer 6 located on the upper surfaces of the buffer areas 3, 4 and 5; JFET region 7 located at the middle upper part of the epitaxial layer 6 and between adjacent P-well regions 8, the width being 3 μm; the P well region 8 is positioned at the upper part of the epitaxial layer 6, and two sides of the JFET region 7; the upper part of the P well region is provided with a super junction region, and the super junction region comprises a P+ source region 9 and an N+ source region 10; the P+ source region 9 is positioned at the edge position above the P well region 8; an n+ source region 10 located above the P well region 8 and close to the p+ source region 9; gate oxide regions 11, 12, 13 are located at the upper parts of the p+ source region 9, the JFET region 7, and the partial n+ source region 10, the gate oxide regions 11, 12, 13 have three layers, and the first gate oxide layer 11 disposed at the upper parts of the p+ source region 9, the JFET region 7, and the partial n+ source region 10 has a structure of Al 2 O 3 The second gate oxide layer 12 has a structure of Gd 2 O 3 The third gate oxide layer 13 has a structure of SiO 2 The method comprises the steps of carrying out a first treatment on the surface of the A gate metal layer 14 located on top of the gate oxide regions 11, 12, 13; a source metal layer 15 located on top of the p+ source region 9 and part of the n+ source region 10; a passivation layer 16 between the source metal layer 15 and the gate metal layer 14.
In this embodiment, the P-well region has a width of 5-10 μm and a height of 3-4 μm. The super junction region has a width of 2-6 μm and a height of 0.5-3 μm, wherein the P+ source region has a width of 2-3 μm and a height of 0.5-1.5 μm, and the N+ source region has a width of 2-3 μm and a height of 0.5-1.5 μm. Preferably, the P-well region has a width of 7 μm and a height of 3 μm; the width of the P+ source region is 2.5 mu m, the height is 1 mu m, the width of the N+ source region is 2.5 mu m, and the height is 1 mu m; it should be understood that the arrangement is to ensure that the contact resistance can be effectively reduced, the loss of the device is reduced, and the electric field distribution condition of the device is regulated and controlled; the specific size settings may be varied according to different needs.
In this embodiment, the gate oxide region includes a first rare earth gate oxide layer 11, and the height of the first rare earth gate oxide layer 11 is 5-8nm; the gate oxide layer region comprises a second rare earth gate oxide layer 12, and the height of the second rare earth gate oxide layer 12 is 20-25nm; the gate oxide layer region comprises a plurality of third rare earth gate oxide layers 13, and the height of the third rare earth gate oxide layers 13 is 8-12nm. The gate oxide layer region comprises a first rare earth gate oxide layer, a second rare earth gate oxide layer and a third rare earth gate oxide layer, and the rare earth gate oxide layer is made of Al 2 O 3 、Gd 2 O 3 、SiO 2 One or more of the following. Preferably, the gate oxide region includes a first rare earth gate oxide 11, a second rare earth gate oxide 12 and a third rare earth gate oxide 13, which are disposed once, and the material of the first rare earth gate oxide 11 is Al 2 O 3 The material of the second rare earth gate oxide layer 12 is Gd 2 O 3 The third rare earth gate oxide layer 13 is made of SiO 2 . With a three-layer rare earth oxide composite structure (Al 2 O 3 /Gd 2 O 3 /SiO 2 ) Gd is used as a gate dielectric layer 2 O 3 The attraction of Gd cations to oxygen atoms can effectively reduce the Al content of the high-k gate dielectric layer 2 O 3 /SiO 2 The resulting dipole layer affects the threshold voltage while maintaining the high dielectric constant state of the device gate oxide. The gate oxide layer adopts Al 2 O 3 /Gd 2 O 3 /SiO 2 Is a structural design of the device. By rare earth oxide Gd 2 O 3 For Al 2 O 3 /SiO 2 Attraction of dipoles (oxygen vacancies) at interface locations to cause Al 2 O 3 /SiO 2 The dipole concentration at the interface is obviously reduced, and the fluctuation of the threshold voltage of the device is effectively restrained.
In this embodiment, the doping concentrations of the buffer layers decrease in order along the upward direction of the substrate. The purpose of the arrangement is that the distribution condition of peak electric fields of a scattered source electrode and a drain electrode under the breakdown condition can be effectively dispersed by utilizing the structure of the gradient decreasing multilayer buffer layer, the capacity of bearing cosmic rays of the device is improved, the influence of Krik effect of a parasitic BJT device structure formed by an N+ well region and an N-is eliminated, and the effect of improving the radiation resistance of the device is further achieved.
It can be found that the invention combines the Multi-buffer layer, the P+/N+ super junction structure and the three rare earth gate dielectric layers (Al 2 O 3 /Gd 2 O 3 /SiO 2 ) A method of construction; the structure of the multi-buffer layer is utilized to further transfer the peak electric field, so that the capacity of the device for bearing cosmic rays is improved, the influence of Krik effect of the device on the N+ source region, the P well region and the N-BJT device structure is eliminated, and the effect of improving the radiation resistance of the device is further achieved; the super junction structure of P+/N+ at the lower section of the source electrode is utilized to effectively reduce the contact resistance, reduce the loss of the device and regulate and control the electric field distribution condition of the device. With a three-layer rare earth oxide composite structure (Al 2 O 3 /Gd 2 O 3 /SiO 2 ) Gd is used as a gate dielectric layer 2 O 3 The attraction of Gd cations to oxygen atoms can effectively reduce the Al content of the high-k gate dielectric layer 2 O 3 /SiO 2 The resulting dipole layer affects the threshold voltage while maintaining the high dielectric constant state of the device gate oxide. And a structural design of a plurality of buffer layers is adopted between the source electrode and the drain electrode. The structure of the multi-layer buffer layer can be used for effectively dispersing the distribution condition of peak electric fields of the source electrode and the drain electrode under the breakdown condition, so that the capacity of the device for bearing cosmic rays is improved, the influence of Krik effect of a parasitic BJT device structure formed by an N+ well region and an N-is eliminated, and the effect of improving the radiation resistance of the device is further achieved. At the position contacting with the source metal layerThe structure of P+/N+ is adopted. The P+/N+ super junction structure can effectively reduce the source electrode contact resistance of the device, simultaneously effectively reduce the working temperature of the device in the working process, simultaneously further reduce the size of the device and improve the integration of the device. The gate oxide layer adopts Al 2 O 3 /Gd 2 O 3 /SiO 2 Is a structural design of the device. By rare earth oxide Gd 2 O 3 For Al 2 O 3 /SiO 2 Attraction of dipoles (oxygen vacancies) at interface locations to cause Al 2 O 3 /SiO 2 The dipole concentration at the interface is obviously reduced, and the fluctuation of the threshold voltage of the device is effectively restrained.
The invention also provides a method for preparing the planar SiC MOSFET containing the rare earth gate dielectric layer, which comprises the following steps:
step 101, evaporating the back of an N-type SiC substrate by adopting an electron beam evaporation mode to obtain a drain metal layer 1, and then obtaining ohmic contact by utilizing a rapid annealing process;
step 102, epitaxially obtaining a buffer region of N-type SiC on the top of the SiC substrate;
step 103, epitaxially obtaining an epitaxial layer of N-type SiC at the upper part of the buffer zone;
104, preparing a corresponding P well region and a super junction region on the epitaxial layer by utilizing an ion implantation mode to form a corresponding JFET region;
step 105, depositing the required rare earth gate oxide regions on the upper parts of the JFET region, the P well region and the super junction region;
step 106, depositing a corresponding SiC MOSFET grid on the rare earth grid oxide region by utilizing a photoetching and electron beam evaporation mode;
step 107, depositing corresponding source metal layers on the upper parts of the P+ source region and part of the N+ source region by utilizing a photoetching and electron beam evaporation mode;
and 108, depositing a passivation layer between the source metal layer and the gate metal layer by using a photoetching and MOCVD growth mode.
As a preferred embodiment, the specific steps are as follows:
1. referring to fig. 2, an Ni/Au drain metal layer 1 is obtained by vapor deposition on the back of an N-type SiC substrate 2 by electron beam vapor deposition, and then ohmic contact is obtained by a rapid annealing process;
2. referring to FIGS. 3-5, buffer regions 3, 4, 5 of N-type SiC of different concentrations are epitaxially grown on top of a SiC substrate 2, the N-type SiC doping concentrations being 1×10, respectively 17 cm -3 ，1×10 16 cm -3 ，1×10 15 cm -3 ；
3. Referring to FIG. 6, an epitaxial layer 6 of N-type SiC having a doping concentration of 1×10 is epitaxially grown on top of the SiC buffer layer 14 cm -3 ；
4. Referring to fig. 7-8, a corresponding P-well region 8, a p+ source region 9,N + source region 10 are prepared on the N-type SiC epitaxial layer 6 by ion implantation to form a corresponding JFET region 7;
5. referring to FIGS. 9-11, a portion of the N+ source region 10 is deposited on top of the P well region 8, the P+ source region 9 to obtain the desired Al 2 O 3 /Gd 2 O 3 /SiO 2 Rare earth gate oxide layers 11, 12, 13;
6. referring to fig. 12, a corresponding gate metal layer 14 is deposited on the rare earth gate oxide layer by photolithography and electron beam evaporation;
7. referring to fig. 13, a corresponding source metal layer 15 is deposited on the p+ source region and a portion of the n+ source region by photolithography and electron beam evaporation; depositing Si between the source metal layer and the gate metal layer by using a photoetching and MOCVD growth mode 3 N 4 A passivation layer 16.
In this embodiment, the specific process of epitaxially obtaining the buffer regions 3, 4, 5 of N-type SiC with different concentrations on top of the SiC substrate 2 is:
2.1 referring to FIG. 3, an N-type doping concentration of 1×10 is prepared by CVD growth on the upper portion of an N-type SiC substrate 17 cm -3 N-type buffer layer 3 of (a);
2.2 referring to FIG. 4, a layer of N-type SiC buffer is grown by CVD on top ofMode preparation of N-type doping concentration of 1×10 16 cm -3 An N-type buffer layer 4 of (a);
2.3 referring to FIG. 5, an N-type doped layer having a concentration of 1×10 is formed on the N-type SiC buffer layer by CVD 15 cm -3 N-type buffer layer 5 of (a).
In this embodiment, step 4, the specific process of obtaining the p+/n+ super junction structure by ion implantation is as follows:
4.1 referring to FIG. 6, a width of 7 μm, a depth of 3 μm and a concentration of 1×10 are formed on the upper portion of the N-type epitaxial layer 6 and on both sides of the JFET region 7 by aluminum ion implantation 16 cm -3 P-well region 8 of (a);
4.2 referring to FIG. 7, a width of 2.5 μm, a depth of 1 μm, and a concentration of 1×10 are prepared at the upper edge of the P-well region 8 by using an oxide layer mask and aluminum ion implantation 18 cm -3 P+ source region of (a);
4.3 referring to FIG. 8, a width of 2.5 μm is prepared at a position above the P well region 8 and near the P+ source region 9 by using an oxide layer mask and nitrogen ion implantation to obtain a depth of 1 μm and a concentration of 1×10 18 cm -3 N+ source region 10 of (a).
In this embodiment, step 5, the specific process of obtaining the corresponding three rare earth gate oxide layers 11, 12, 13 by using PVD (magnetron sputtering) and ALD (atomic layer deposition) growth methods is as follows:
5.1 referring to FIG. 9, the P-well region, JFET region 7, and partial N+ source region 10 are formed by ALD (atomic layer deposition) to deposit Al with a thickness of 5-8nm 2 O 3 A first rare earth gate oxide layer 11;
5.2 referring to FIG. 10, the PVD (magnetron sputtering) method is used to deposit the metal oxide on the Al 2 O 3 Gd with thickness of 20-25nm is deposited on 2 O 3 Wherein the growth conditions are that the vacuum degree of the equipment growth is controlled to be 1 multiplied by 10 -4 Pa, growth pressure is 2.5Pa, ar: O 2 The flow rate ratio of (2) is 30sccm:5sccm, the growth power is 50-70W; the second rare earth gate oxide layer 12 obtained;
5.3 referring to FIG. 11, the ALD (atomic layer deposition) method is used inGd 2 O 3 Deposition of SiO with thickness of 10nm 2 A third rare earth gate oxide layer 13 of (c).
The preferred embodiment is to obtain different concentrations of SiC buffer layers between the substrate and the epitaxial layer by CVD, obtain P+/N+ super junction by aluminum ion implantation and nitrogen ion implantation at the upper part of the epitaxial layer, two sides of the JFET region and above the P-well region, and deposit rare earth oxide layer (Al) by ALD (atomic layer deposition) and PVD (magnetron sputtering) at the upper parts of the P-well region, JFET region and part of N+ source region 2 O 3 /Gd 2 O 3 /SiO 2 ) Is a structure of (a). The distribution condition of an electric field between the source electrode and the drain electrode can be effectively regulated by utilizing the SiC buffer layers with different concentrations, so that the adverse effect of cosmic rays on the device is reduced; the P+/N+ super junction is obtained at the upper part of the epitaxial layer, at the two sides of the JFET region and above the P well region in a way of aluminum ion implantation and nitrogen ion implantation at the position close to the P+ source region, so that the contact characteristic between the source electrode and the epitaxial layer is improved, and meanwhile, the working resistance and the working loss of the device are reduced; adopting ALD (atomic layer deposition) and PVD (magnetron sputtering) two common coating processes to obtain corresponding three-layer rare earth gate oxide (Al) 2 O 3 /Gd 2 O 3 /SiO 2 ) The dipole layer at the interface position of the gate oxide layer is regulated, so that the stability of the threshold voltage of the device is improved under the condition that the breakdown voltage of the device is kept unchanged.
It can be seen that, in the above scheme,
(1) And a structural design of a plurality of buffer layers is adopted between the source electrode and the drain electrode. The distribution condition of peak electric fields of the source electrode and the drain electrode under the breakdown condition can be effectively dispersed by utilizing the structure of the multi-layer buffer layer, so that the capacity of the device for bearing cosmic rays is improved, the influence of Krik effect of a parasitic BJT device structure formed by N+ and P-well and N-is eliminated, and the effect of improving the radiation resistance of the device is further achieved;
(2) A p+/n+ structure is used at the location where it contacts the source metal layer. The P+/N+ super junction structure can effectively reduce the source electrode contact resistance of the device, effectively reduce the working temperature of the device in the working process, further reduce the size of the device and improve the integration of the device;
(3) The gate oxide layer adopts Al 2 O 3 /Gd 2 O 3 /SiO 2 Is a structural design of the device. By rare earth oxide Gd 2 O 3 For Al 2 O 3 /SiO 2 Attraction of dipoles (oxygen vacancies) at interface locations to cause Al 2 O 3 /SiO 2 The dipole concentration at the interface is obviously reduced, and the fluctuation of the threshold voltage of the device is effectively restrained.
The foregoing description is only a partial embodiment of the present invention, and is not intended to limit the scope of the present invention, and all equivalent devices or equivalent processes using the descriptions and the drawings of the present invention or directly or indirectly applied to other related technical fields are included in the scope of the present invention.
Claims (10)
1. A planar SiC MOSFET having a rare earth gate dielectric layer, comprising: a metal layer, a substrate; characterized by further comprising:
the buffer area is arranged at the upper part of the substrate and comprises a plurality of buffer layers; the epitaxial layer is arranged at the upper part of the buffer area; the P well regions are arranged on two sides of the upper part of the epitaxial layer, and JFET regions are formed in the middle of the P well regions; the upper part of the P well region is provided with a super junction region; the upper part of the JFET region is provided with a gate oxide layer region which is in contact with the JFET region, the P-well region and the superjunction region; the gate oxide layer region comprises a plurality of rare earth gate oxide layers; the upper part of the gate oxide layer area is sequentially provided with a gate metal layer, a passivation layer covering the gate oxide layer area and the gate metal layer; and the upper part of the super junction region is covered with a source metal layer.
2. The planar SiC MOSFET of claim 1 wherein the P-well region has a width of 5-10 μm and a height of 3-4 μm.
3. A planar SiC MOSFET having a rare earth gate dielectric according to claim 1 or 2, wherein said superjunction region has a width of 2-6 μm and a height of 0.5-3 μm.
4. A planar SiC MOSFET comprising a rare earth gate dielectric layer as defined in claim 1,
the gate oxide layer region comprises a plurality of first rare earth gate oxide layers, and the heights of the first rare earth gate oxide layers are 5-8nm;
and/or the number of the groups of groups,
the gate oxide layer region comprises a plurality of second rare earth gate oxide layers, and the height of the second rare earth gate oxide layers is 20-25nm;
and/or the number of the groups of groups,
the gate oxide layer region comprises a plurality of third rare earth gate oxide layers, and the height of each third rare earth gate oxide layer is 8-12nm.
5. A planar SiC MOSFET comprising a rare earth gate dielectric layer as defined in claim 4,
the gate oxide layer region comprises a first rare earth gate oxide layer, a second rare earth gate oxide layer and a third rare earth gate oxide layer which are sequentially arranged from bottom to top, and the rare earth gate oxide layer is made of Al 2 O 3 、Gd 2 O 3 、SiO 2 One or more of the following.
6. A planar SiC MOSFET comprising a rare earth gate dielectric layer as defined in claim 1,
the doping concentration of the buffer layers is gradually decreased along the upward direction of the substrate.
7. A method for preparing a planar SiC MOSFET containing a rare earth gate dielectric layer, wherein the method is used for preparing a planar SiC MOSFET containing a rare earth gate dielectric layer according to any one of claims 1 to 6; the method comprises the following steps:
step 101, evaporating the back of an N-type SiC substrate by adopting an electron beam evaporation mode to obtain a drain metal layer 1, and then obtaining ohmic contact by utilizing a rapid annealing process;
step 102, epitaxially obtaining a buffer region of N-type SiC on the top of the SiC substrate;
step 103, epitaxially obtaining an epitaxial layer of N-type SiC at the upper part of the buffer zone;
104, preparing a corresponding P well region and a super junction region on the epitaxial layer by utilizing an ion implantation mode to form a corresponding JFET region;
step 105, depositing the required rare earth gate oxide regions on the upper parts of the JFET region, the P well region and the super junction region;
step 106, depositing a corresponding SiC MOSFET grid on the rare earth grid oxide region by utilizing a photoetching and electron beam evaporation mode;
step 107, depositing corresponding source metal layers on the upper parts of the P+ source region and part of the N+ source region by utilizing a photoetching and electron beam evaporation mode;
and 108, depositing a passivation layer between the source metal layer and the gate metal layer by using a photoetching and MOCVD growth mode.
8. The method for fabricating a planar SiC MOSFET including a rare earth gate dielectric of claim 7, wherein step 102 further comprises fabricating a plurality of N-type buffer layers of successively decreasing doping concentration by CVD growth on top of the N-type SiC substrate.
9. The method of claim 7, wherein the step 104 further comprises preparing a p+ source region in the super junction region above the P well region by means of oxide layer mask and aluminum ion implantation; and preparing an N+ source region in the super junction region at one side of the P well region far away from the edge position by using an oxide layer mask and nitrogen ion implantation mode.
10. The method of claim 7, wherein the step 105 further comprises depositing a gate oxide layer region on top of the JFET region, the P-well region, and the superjunction region by atomic layer deposition and/or magnetron sputtering.
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Inventor after: Yang Weifeng Inventor after: Wang Xinwei Inventor after: Ye Xiaofeng Inventor after: Long Mingtao Inventor before: Yang Weifeng Inventor before: Wang Xinwei Inventor before: Ye Xiaofeng Inventor before: Long Mingtao |