CN116417520B - Gallium oxide field effect transistor and preparation method thereof - Google Patents
Gallium oxide field effect transistor and preparation method thereof Download PDFInfo
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- CN116417520B CN116417520B CN202310640409.9A CN202310640409A CN116417520B CN 116417520 B CN116417520 B CN 116417520B CN 202310640409 A CN202310640409 A CN 202310640409A CN 116417520 B CN116417520 B CN 116417520B
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- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 title claims abstract description 96
- 229910001195 gallium oxide Inorganic materials 0.000 title claims abstract description 95
- 238000002360 preparation method Methods 0.000 title abstract description 10
- 238000002353 field-effect transistor method Methods 0.000 title description 2
- 239000010410 layer Substances 0.000 claims abstract description 346
- 239000000463 material Substances 0.000 claims abstract description 100
- 230000005669 field effect Effects 0.000 claims abstract description 65
- 239000011229 interlayer Substances 0.000 claims abstract description 60
- 230000007704 transition Effects 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 238000000151 deposition Methods 0.000 claims description 49
- 229910052751 metal Inorganic materials 0.000 claims description 46
- 239000002184 metal Substances 0.000 claims description 46
- 238000004519 manufacturing process Methods 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 22
- 238000000059 patterning Methods 0.000 claims description 13
- 238000005496 tempering Methods 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 10
- 230000001681 protective effect Effects 0.000 claims description 7
- 230000000903 blocking effect Effects 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 6
- 230000005684 electric field Effects 0.000 abstract description 22
- 239000003989 dielectric material Substances 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 19
- 230000008021 deposition Effects 0.000 description 7
- 229910002601 GaN Inorganic materials 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 229910052749 magnesium Inorganic materials 0.000 description 4
- 239000011777 magnesium Substances 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 239000002131 composite material Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 2
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 2
- 229910001260 Pt alloy Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910001069 Ti alloy Inorganic materials 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 241001354791 Baliga Species 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 150000004820 halides Chemical class 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
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- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention provides a gallium oxide field effect transistor and a preparation method thereof, belonging to the technical field of semiconductor devices. The gallium oxide field effect transistor comprises a drain electrode, a gallium oxide substrate, a voltage-resistant layer, a p base layer and a conducting layer which are sequentially arranged. The active area of the gallium oxide field effect transistor is provided with a plurality of first grooves, the bottom of at least one first groove is provided with a high-resistance layer, the inside of the first groove is provided with a gate dielectric layer and a gate electrode, and the surface of the gate electrode is provided with a first interlayer dielectric; a first p-type material layer is arranged in the first groove without the high-resistance layer. The transition region is provided with a second recess having a second p-type material layer deposited therein. The termination region is provided with a plurality of third recesses having a third p-type material layer deposited therein. The conductive layer of the active area and the surface of the first interlayer medium are provided with a source electrode. The gallium oxide field effect transistor can reduce the electric field on the surface of a semiconductor device, reduce the dependence on the thickness of a gate dielectric material, and has the characteristics of high voltage-withstanding efficiency and small occupied area.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a gallium oxide field effect transistor and a preparation method thereof.
Background
In a wide bandgap semiconductor material, gallium oxide (Ga 2 O 3 ) Has a forbidden band width of 4.8eV, an ideal breakdown field strength of 8MV/cm, and a bar Li Ga figure of merit (BFOM, baliga's configuration-of-merit) of up to 3400. Ga 2 O 3 Is about 4 times that of GaN and 10 times that of SiC. Thus, ga is given the same withstand voltage 2 O 3 The power device has lower on-resistance and lower power consumption than a GaN device or a SiC device, and can greatly reduce the electric energy loss when the device works.
However, gallium oxide lacks an effective P-type semiconductor, so that it cannot be made into a metal-oxide semiconductor field effect transistor (MOSFET) of a conventional structure like SiC, gaN, and can be made into a metal-insulator semiconductor field effect transistor (MISFET) or a Junction Field Effect Transistor (JFET) device in which the drain, source and drift regions are all N-type conductive. The gallium oxide MISFET and JFET devices have work function differences between gate metal, polysilicon, P-type semiconductor and gallium oxide epitaxial layers, so that depletion layers appear on conductive channels to influence the working characteristics of the devices. The planar gallium oxide MISFET device is only partially depleted and not fully depleted in its conductive path at a gate voltage of 0V and is only a depletion type device at forward bias. When the device is in reverse bias, the gate electrode can shield part of the electric field, but because the gate electrode is on the gallium oxide epitaxial surface, the depletion region is not expanded enough, the electric field shielding capability is limited, the electric field of the metal-semiconductor interface is still strong, more and more electrons are generated from the source electrode to the drain electrode along with the increase of reverse voltage, and larger reverse leakage current occurs, so that the reliability of the device is deteriorated. On the other hand, when the device works as a flywheel diode at a third quadrant, smaller Schottky barrier height and low conduction voltage drop are needed, and the power consumption of the device is reduced. Although the planar MISFET has the advantage of operating in the third quadrant, it is not practical because of the large reverse leakage. There is a need to further develop devices that are junction enhancement and reverse leakage less and that are capable of integrating schottky diodes.
To reduce the electric field at the metal-semiconductor interface, an enhanced semiconductor device was prepared, which is known in the art (Li, w., et al, "Single and multi-fin normal-off Ga 2 O 3 vertical transistors with a breakdown voltage over 2.6.6 kV in "2019 IEEE International Electron Devices Meeting (IEDM) IEEE, 2019") grooves are formed in the surface by etching the gallium oxide epitaxial layer, and then SiO is deposited into the grooves 2 And Al 2 O 3 And forming a gate dielectric of the MISFET device by using the insulating dielectric, and manufacturing an Enhanced MISFET (EMISFET). In contrast to planar MISFET devices, EMISFET devices have normally-off characteristics because the metal gate or polysilicon gate can fully deplete the conductive channel. In addition, the gate electrode has a certain depth, so that the electric field of the reverse bias part can be effectively shielded, the surface electric field is reduced to a certain extent, and the leakage current is reduced; and the device can operate in the third quadrant.
Due to the nature of gallium oxide materials, if a large depth of gate dielectric deposition is to be achieved, it cannot be achieved by thermal oxidation, and it is necessary to form deep trenches in the gallium oxide material, and then form the deposition of gate dielectric on the surfaces of the deep trenches. However, the depth of the deep trench is larger, so that the thickness of the gate dielectric layer in the deep trench is uneven, and the uniformity of the threshold voltage of the device is affected. Although the EMISFET device can effectively reduce the surface electric field during reverse bias, due to the limited depth of the groove, the peak electric field is located closer to the surface, and a part of electric field lines still pass through the grid electrode to reach the source electrode, so that the electric field of the metal-semiconductor interface is still strong, and larger leakage current can be generated by the device, thereby affecting the reliability of the device. More importantly, the thickness of the gate dielectric material which is usually selected for preparing the enhanced device is very thin, when the peak value of the electric field is transferred from the surface to the internal groove, the gate dielectric can only bear very small voltage, and the device is more likely to break down at the gate dielectric, so that the breakdown voltage and the forward conduction characteristic of the EMISFET device are influenced by the thickness of the gate dielectric, and the advantage of high breakdown field strength of gallium oxide cannot be fully exerted. On the other hand, in order to manufacture an enhancement device, it is necessary to set the pitch of two adjacent trenches to about 0.35 μm, ensuring that the conduction channel is fully depleted at a gate voltage of 0V. To realize small line width and continue to make lithography and etching on the small line width, an expensive electron beam lithography machine needs to replace a common i-line lithography machine to complete the exposure process, which results in increased production cost, reduced productivity, and no utilization of mass production. Meanwhile, in the prior art, the terminal structure is single, and withstand voltage can be realized only through the field limiting ring and the high-resistance layer.
Therefore, new technical solutions are needed to further reduce the electric field at the device surface and reduce the dependence on the gate dielectric material thickness. Meanwhile, the manufacturing difficulty of the device is reduced, so that the device can be manufactured by adopting a more traditional scheme. Finally, the terminal structure of the gallium oxide device is required to have the characteristics of high voltage-resistant efficiency and small occupied area, and lays a foundation for manufacturing the gallium oxide field effect transistor device with high voltage resistance and high reliability.
Disclosure of Invention
In order to achieve the above object, the present invention provides a gallium oxide field effect transistor. The gallium oxide field effect transistor can reduce the electric field on the surface of the semiconductor device and reduce the dependence on the thickness of the gate dielectric material; and has the characteristics of high pressure-resistant efficiency and small occupied area.
Specifically, in order to achieve the above purpose, the present invention adopts the following technical scheme:
a gallium oxide field effect transistor comprises a drain electrode, a gallium oxide substrate, a voltage-resistant layer, a p base layer and a conductive layer which are sequentially arranged; the voltage-resistant layer, the p base layer and the conducting layer form an epitaxial layer with a sandwich structure; the epitaxial layer comprises an active region, a transition region and a terminal region, wherein the transition region is positioned between the active region and the terminal region; the active region is provided with a plurality of first grooves, and the bottom end of the interior of at least one first groove is provided with a high-resistance layer; a gate dielectric layer is arranged on the inner edge wall of the first groove provided with the high-resistance layer, a gate electrode is arranged in the gate dielectric layer, and a first interlayer dielectric is arranged on the upper surface of the gate electrode; a first p-type material layer is arranged on the inner edge wall of the first groove without the high-resistance layer; the transition region is provided with a second groove, and a second p-type material layer is arranged along the inner wall of the second groove; a plurality of third grooves are formed in the terminal end at intervals, and a third p-type material layer is arranged in each third groove along the wall; and a source electrode is arranged on the surface of the conducting layer of the active region and the surface of the first interlayer medium, and two ends of the source electrode are respectively connected with the first p-type material layer and the second p-type material layer.
In a preferred embodiment, a first metal layer is provided on the surface of the first p-type material layer, and a second metal layer is provided on the surface of the second p-type material layer.
In a preferred embodiment, the first groove provided with the first metal layer is filled with a second interlayer medium inside; and third interlayer media are arranged in the second grooves, in each third groove and on the surface of the conductive layer of the terminal area.
In a preferred embodiment, the bottom end of the interior of the second recess is provided with a high-resistance layer; or/and the bottom end of the inner part of at least one third groove is provided with a high-resistance layer.
In a preferred embodiment, the depth of the first recess in the active region, in which the gate dielectric layer is disposed, is less than the depth of the first recess in which the first p-type material layer is disposed, and less than the depth of the second recess.
In a preferred embodiment, the depth of the third recess is greater than or equal to the thickness of the conductive layer.
In a preferred embodiment, the termination region comprises at least one N + A blocking ring.
The invention also provides a preparation method of the gallium oxide field effect transistor, which comprises the following steps:
sequentially growing a pressure-resistant layer, a p base layer and a conductive layer on a gallium oxide substrate to form an epitaxial layer with a sandwich structure, etching the surface of the epitaxial layer, forming a plurality of first grooves in an active region, forming a second groove in a transition region, and forming a plurality of third grooves in a terminal region;
injecting a protective element into the bottom end of the inside of at least one first groove and tempering to form a high-resistance layer; the protective element is nitrogen element or magnesium element;
depositing a drain metal layer on one side of the gallium oxide substrate far away from the pressure-resistant layer, and tempering to obtain a drain;
depositing a gate dielectric layer in the first groove provided with the high-resistance layer, and then depositing a conductive material to manufacture a gate electrode; depositing a first interlayer medium on the upper surface of the gate electrode;
depositing and patterning p-type materials in the first groove, the second groove and each third groove which are not provided with the high-resistance layer to respectively obtain a first p-type material layer, a second p-type material layer and a third p-type material layer;
and depositing a source electrode metal layer on the surface of the conducting layer of the active region and the surface of the first interlayer medium, and respectively connecting the source electrode metal layer with the first p-type material layer and the second p-type material layer to obtain a source electrode.
In a preferred embodiment, the method for manufacturing a gallium oxide field effect transistor further comprises the steps of: and depositing a first metal layer on the surface of the first p-type material layer, and depositing a second metal layer on the surface of the second p-type material layer.
In a further preferred embodiment, the method for manufacturing a gallium oxide field effect transistor further comprises the steps of: depositing a second interlayer medium in the first groove in which the first metal layer is deposited, and respectively depositing a third interlayer medium in the second groove, in each third groove and on the surface of the conductive layer of the terminal area; the source metal layer extends to the surfaces of the second interlayer dielectric and the third interlayer dielectric.
In a preferred embodiment, the thickness of the pressure-resistant layer is 5-10 μm.
In a preferred embodiment, the material used for the pressure-resistant layer is gallium oxide, silicon carbide, gallium nitride or diamond.
In a particularly preferred embodiment of the invention, the preparation method comprises the following steps:
s1, a voltage-resistant layer, a p base layer and a conductive layer are sequentially grown on a gallium oxide substrate; the voltage-resistant layer, the p base layer and the conducting layer form an epitaxial layer with a sandwich structure; the epitaxial layer comprises an active region, a transition region and a terminal region, wherein the transition region is positioned between the active region and the terminal region;
s2, etching the surface of the epitaxial layer, forming a plurality of first grooves in an active region, forming a second groove in a transition region, and forming a plurality of third grooves in a terminal region;
s3, injecting a protective element into the bottom end of the inside of at least one first groove and tempering to form a high-resistance layer;
s4, depositing a drain metal layer on one side of the gallium oxide substrate far away from the pressure-resistant layer, and tempering to obtain a drain;
s5, depositing a gate dielectric layer on the surface of the high-resistance layer and on the inner wall of the first groove provided with the high-resistance layer, and patterning the gate dielectric layer;
s6, depositing a conductive material in the gate dielectric layer and patterning the conductive material to obtain a gate electrode;
s7, depositing and patterning a p-type material along the wall inside the first groove without the gate electrode to obtain a first p-type material layer; depositing and patterning a p-type material along the wall inside the second groove to obtain a second p-type material layer; depositing and patterning a p-type material along the wall inside the third groove to obtain a third p-type material layer;
s8, respectively depositing a first metal layer and a second metal layer on the surfaces of the first p-type material layer and the second p-type material layer;
s9, depositing a first interlayer medium on the upper surface of the gate electrode; depositing a second interlayer medium in the first groove which is not provided with the gate electrode; respectively depositing a third interlayer medium in the second grooves, in each third groove and on the surface of the conductive layer of the terminal area, so that the third interlayer medium of the transition area and the third interlayer medium of the terminal area are connected into a whole; patterning the first interlayer medium, the second interlayer medium and the third interlayer medium respectively;
and S10, depositing a source metal layer on the surface of the conductive layer of the active region and the surface of the first interlayer medium, patterning and tempering, wherein the source metal layer extends to the surfaces of the second interlayer medium and the third interlayer medium, and obtaining a source electrode. In a further preferred embodiment, step S3 further comprises injecting a protective element at the bottom end of the interior of the second recess and tempering to form a high-resistance layer.
In a further preferred embodiment, step S3 further comprises injecting a protective element at the bottom end of the interior of at least one of said third grooves and tempering to form a high-resistance layer.
In a further preferred embodiment, step S3 further comprises forming a photolithographic window between any two non-adjacent third recesses of the termination region or at the end of the termination region where the third recesses are not provided, and then implanting and activating silicon element by an ion implanter to form N + A blocking ring.
Compared with the prior art, the invention has the following beneficial effects:
in the invention, an epitaxial layer of a sandwich structure grown on a gallium oxide substrate is used as a device processing base, and the epitaxial layer of the sandwich structure consists of a pressure-resistant layer, a p base layer (pbase layer) and a conductive layer. The voltage-resistant layer and the conductive layer are both N-type semiconductors, the doping concentration of the conductive layer is far higher than that of the voltage-resistant layer, and the p-base layer is formed by doping Mg and N elements into the epitaxial layer together as impurities in the epitaxial growth process, and has the property of weak p-type semiconductors. And etching epitaxial layers in the active region and the terminal region respectively to form a plurality of first grooves and a plurality of third grooves, wherein the first grooves of the active region form a trench MOSFET, and a high-resistance layer formed by injecting a protective element (N or Mg) and a heterojunction formed by depositing a first p-type material layer protect the bottom of the first grooves from a reverse electric field, and simultaneously reduce the reverse current of a source electrode and a drain electrode. The third groove of the terminal region and the p base layer form a composite terminal structure, and when the third p type material layer in the third groove is connected with the p base layer, the field limiting ring terminal formed by the third p type material layer plays a role in voltage resistance by depositing the third p type material layer in the third groove and patterning the third p type material layer in the third groove; when the third p-type material layer in the third groove is not connected with the p-type material layer, the p-type material layer is firstly subjected to high voltage to generate a depletion layer, when the p-type material layer is depleted by the high voltage, depletion of the conducting layer occurs, and after the conducting layer is also depleted, a strong electric field is formed on the surface of the device, so that the p-type material layer is required to be added to serve as a stop layer (namely the third p-type material layer) of the electric field, the electric field is concentrated on the p-type material, and the electric field on the surface of the device is reduced. When the grid voltage is 0V, the device has normal-off performance, the space between the first grooves can be increased due to the shielding effect of the high-resistance layer and the heterojunction in the active area, and the photoetching of the first groove pattern can be completed by using a conventional photoetching machine, so that the gallium oxide field effect transistor with high voltage resistance and small area can be manufactured finally. Therefore, the structure of the gallium oxide field effect transistor provided by the invention can not only improve the voltage withstanding efficiency of the device, but also reduce the chip area.
Drawings
Fig. 1 is a schematic structural diagram of a gallium oxide field effect transistor in embodiment 1;
fig. 2 is a schematic diagram of an epitaxial layer of a sandwich structure prepared in the first step of the preparation method of a gallium oxide field effect transistor in example 2;
fig. 3 is a schematic diagram showing the structure obtained by the second step of the method for manufacturing a gallium oxide field effect transistor in example 2;
fig. 4 is a schematic diagram showing the structure obtained by the third step of the method for manufacturing a gallium oxide field effect transistor in example 2;
fig. 5 is a schematic diagram of a structure obtained by the fourth step of the method for manufacturing a gallium oxide field effect transistor in example 2;
fig. 6 is a schematic diagram of a structure obtained by the fifth step of the manufacturing method of the gallium oxide field effect transistor in example 2;
fig. 7 is a schematic diagram showing a structure obtained by the sixth step of the manufacturing method of the gallium oxide field effect transistor in example 2;
fig. 8 is a schematic diagram of a structure obtained by a seventh step of the method for manufacturing a gallium oxide field effect transistor in example 2;
fig. 9 is a schematic diagram of a structure obtained by the eighth step of the method for manufacturing a gallium oxide field effect transistor in example 2;
fig. 10 is a schematic diagram of a structure obtained by a ninth step of the manufacturing method of a gallium oxide field effect transistor in example 2;
fig. 11 is a schematic structural diagram of a gallium oxide field effect transistor prepared in the tenth step of the preparation method of a gallium oxide field effect transistor in example 2;
fig. 12 is a schematic structural diagram of a gallium oxide field effect transistor in embodiment 3;
fig. 13 is a schematic structural diagram of a gallium oxide field effect transistor in embodiment 4;
fig. 14 is a schematic structural diagram of a gallium oxide field effect transistor in embodiment 5;
fig. 15 is a schematic structural diagram of a gallium oxide field effect transistor in example 6;
fig. 16 is a schematic structural diagram of a gallium oxide field effect transistor in example 7;
fig. 17 is a schematic structural diagram of a gallium oxide field effect transistor in example 8;
fig. 18 is a schematic structural diagram of a gallium oxide field effect transistor in embodiment 9.
In the figure: 1. a gallium oxide substrate; 2. a pressure-resistant layer; 3. a p base layer; 4. a conductive layer; 5. a high-resistance layer; 6. a drain electrode; 7. a gate dielectric layer; 8. a gate electrode; 91. a first p-type material layer; 92. a second p-type material layer; 93. a third p-type material layer; 101. a first metal layer; 102. a second metal layer; 111. a first interlayer medium; 112. a second interlayer medium; 113. a third interlayer medium; 12. a source electrode; 13. n (N) + A blocking ring; A. an active region; B. a transition zone; C. a termination region.
Detailed Description
The following description sets forth a clear and complete description of the present invention, in connection with embodiments, so that those skilled in the art will fully understand the present invention. It will be apparent that the described embodiments are only some, but not all, of the preferred embodiments of the present invention. Any equivalent alterations or substitutions for the following embodiments without any inventive effort by those of ordinary skill in the art are intended to be within the scope of the present invention.
The methods not described in detail in the examples below are all conventional methods well known to those skilled in the art. For example, etching the epitaxial layer using an ICP etcher with BCl 3 The method of etching by gas adopts a magnetron sputtering method for p-type material deposition, a PECVD (plasma enhanced chemical vapor deposition) method for interlayer dielectric deposition, an electron beam evaporation method for metal layer deposition of a source electrode and a drain electrode, and an LPCVD (low pressure chemical vapor deposition) method for gate electrode deposition.
The terms "first," "second," "third," and the like in this disclosure are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implying a number of technical features being indicated.
Example 1
As shown in fig. 1, fig. 1 is a schematic structural diagram of a gallium oxide field effect transistor according to the present embodiment. The gallium oxide field effect transistor comprises a drain electrode 6, a gallium oxide substrate 1, a voltage-resistant layer 2, a p base layer 3 and a conductive layer 4 which are sequentially arranged; the voltage-resistant layer 2, the p base layer 3 and the conducting layer 4 form an epitaxial layer with a sandwich structure. The epitaxial layer comprises an active region A, a transition region B and a terminal region C, wherein the transition region B is positioned between the active region A and the terminal region C. The active area A is provided with a plurality of first grooves at intervals, and the bottom end of the inside of at least one first groove is provided with a high-resistance layer 5. The inner edge wall of the first groove which is not provided with the high-resistance layer 5 is provided with a first p-type material layer 91; a gate dielectric layer 7 is arranged along the inner wall of the first groove provided with the high-resistance layer 5, a gate electrode 8 is arranged in the gate dielectric layer 7, and a first interlayer dielectric 111 is arranged on the upper surface of the gate electrode 8. The transition region B is provided with a second recess in which a second p-type material layer 92 is provided along the wall. The terminal area C is provided with a plurality of third grooves at intervals, and a third p-type material layer 93 is arranged in each third groove along the wall. A source electrode 12 is disposed on the surface of the conductive layer 4 of the active region a and the surface of the first interlayer dielectric 111, and two ends of the source electrode 12 are respectively connected to the first p-type material layer 91 and the second p-type material layer 92.
The first recess in the active region a forms a trench MOSFET and has a heterojunction formed by deposition of the high-resistance layer 5 and the first p-type material layer 91 to protect the bottom of the first recess from the reverse electric field while reducing the source and drain reverse current. The third groove of the termination region C and the p base layer 3 form a composite termination structure, and the third p type material layer 93 is deposited and patterned in the third groove of the termination region C, so that when the third p type material layer 93 in the third groove is connected with the p base layer 3, the field limiting ring terminal formed by the third p type material layer 93 plays a role in voltage resistance, and is connected with the p base layer 3, so that the electric field which is concentrated at the edge of the original field limiting ring is dispersed through the p base layer 3, thereby avoiding the concentration of the electric field at a certain place, and integrally increasing the voltage resistance of the device. The composite terminal structure can achieve the purposes of improving the voltage-withstanding efficiency of the device and reducing the area of the chip.
The preparation method of the gallium oxide field effect transistor in fig. 1 comprises the following steps:
(1) And a pressure-resistant layer 2, a p base layer 3 and a conductive layer 4 are sequentially grown on the gallium oxide substrate 1 to form an epitaxial layer with a sandwich structure. The epitaxial layer comprises an active region A, a transition region B and a terminal region C, wherein the transition region B is positioned between the active region A and the terminal region C. And etching the surface of the epitaxial layer, forming a plurality of first grooves in the active region, forming a second groove in the transition region, and forming a plurality of third grooves in the terminal region. The material of the pressure-resistant layer 2 is gallium nitride, and the thickness is 5 mu m.
(2) Injecting magnesium element into the bottom end of the inner part of one of the first grooves and tempering to form a high-resistance layer 5; depositing a gate dielectric (e.g. Al) on the surface of the high-resistance layer 5 and on the inner walls of the first recess 2 O 3 ) Obtaining a gate dielectric layer 7; thenDeposition of a conductive material, such as polysilicon, continues inside the first recess, resulting in a gate electrode 8. Depositing a first interlayer dielectric (e.g. SiO) on the surface of the gate electrode 8 2 ) 111, the first interlayer dielectric 111 completely covers the gate electrode 8 and the gate dielectric layer 7 in the first groove, and two ends of the first interlayer dielectric 111 extend to the surface of the conductive layer 4 around the first groove respectively.
(3) A drain metal layer (e.g. Ti/Au alloy layer) is deposited on the side of the gallium oxide substrate 1 remote from the voltage-resistant layer 2, and tempered to obtain a drain electrode 6.
(4) A p-type material (e.g., niO) is deposited and patterned in the first recess, in the second recess, and in each of the third recesses where the high-resistance layer 5 is not disposed, resulting in a first p-type material layer 91, a second p-type material layer 92, and a third p-type material layer 93, respectively.
(5) A source metal layer (e.g., a Ti/Al/Pt alloy layer) is deposited on the surface of the conductive layer 4 of the active region a and the surface of the first interlayer dielectric 111, and the source metal layer is connected to the first p-type material layer 91 and the second p-type material layer 92, respectively, to obtain a source electrode 12. Thus, the complete gallium oxide field effect transistor of fig. 1 was prepared.
Example 2
As shown in fig. 11, the present embodiment provides a gallium oxide field effect transistor, which includes a drain electrode 6, a gallium oxide substrate 1, a voltage-resistant layer 2, a p base layer 3, and a conductive layer 4, which are sequentially arranged; the voltage-resistant layer 2, the p base layer 3 and the conducting layer 4 form an epitaxial layer with a sandwich structure. The epitaxial layer comprises an active region A, a transition region B and a terminal region C, wherein the transition region B is positioned between the active region A and the terminal region C. The active area A is provided with a plurality of first grooves, the transition area B is provided with a second groove, and the terminal area C is provided with a plurality of third grooves. The bottom end of the inside of at least one first groove is provided with a high-resistance layer 5, and a gate dielectric layer 7 is arranged along the wall inside the first groove provided with the high-resistance layer 5; a gate electrode 8 is filled in the gate dielectric layer 7; a first interlayer dielectric 111 is deposited on the upper surface of the gate electrode 8, and the first interlayer dielectric 111 extends to the periphery of the first recess provided with the high-resistance layer 5 to be in contact with the conductive layer 4. A first p-type material layer 91 is disposed at the bottom and on the side wall in the first groove where the gate electrode 8 is not disposed, a first metal layer 101 is disposed on the surface of the first p-type material layer 91, and a second interlayer dielectric 112 is filled in the first metal layer 101. The bottom and the side wall in the second groove are both provided with a second p-type material layer 92, and a second metal layer 102 is arranged on the surface of the second p-type material layer 92. A third layer 93 of p-type material is provided along the inner walls of each of said third recesses. A third interlayer dielectric 113 is deposited in the second grooves, in each third groove, on the surface of the conductive layer of the termination region C, and is integrated therewith. The surface of the conductive layer 4 of the active region a and the surface of the first interlayer dielectric 111 are provided with a source 12, and the source 12 extends to both sides to the surfaces of the second interlayer dielectric 112 and the third interlayer dielectric 113, respectively.
As shown in fig. 2 to 11, the preparation method of the gallium oxide field effect transistor comprises the following steps:
s1, a voltage-resistant layer 2, a p base layer 3 and a conductive layer 4 are sequentially grown on a gallium oxide substrate 1, and the voltage-resistant layer 2, the p base layer 3 and the conductive layer 4 form an epitaxial layer with a sandwich structure (figure 2). The pressure-resistant layer 2 is a gallium oxide layer grown by an HPVE (halide vapor phase epitaxy) method and has a thickness of 10 μm.
S2, etching the surface of the epitaxial layer, forming a plurality of first grooves in the active area A, forming a second groove in the transition area B, and forming a plurality of third grooves in the terminal area C (figure 3).
And S3, injecting nitrogen element into the bottom end of the inner part of one of the first grooves and tempering to form a high-resistance layer 5 (figure 4). The high-resistance layer 5 serves as a protective layer at the bottom of the first groove.
And S4, depositing a drain metal layer (such as a Ti/Au alloy layer) on one side of the gallium oxide substrate 1 far away from the pressure-resistant layer 2 and tempering to enable the drain metal layer to form ohmic contact with the gallium oxide substrate 1, so as to obtain a drain electrode 6 (figure 5).
S5, depositing Al on the surface of the high-resistance layer 5 and the inner wall of the first groove deposited with the high-resistance layer 5 by adopting an Atomic Layer Deposition (ALD) method 2 O 3 The layers are patterned to obtain a gate dielectric layer 7 (fig. 6).
S6, a conductive material (polysilicon) is deposited and patterned in the gate dielectric layer 7 (fig. 7) as a gate electrode 8.
And S7, depositing and patterning p-type material NiO along the wall in the first groove, the second groove and the third groove which are not provided with the gate electrode by adopting a magnetron sputtering method to form a first p-type material layer 91, a second p-type material layer 92 and a third p-type material layer 93 (figure 8) respectively. The depth of the third recess extends from the conductive layer 4 all the way to the voltage withstanding layer 2, penetrating the p-base layer in the middle, so that the first p-type material layer 91, the second p-type material layer 92 and the third p-type material layer 93 all form a heterojunction with the gallium oxide of the voltage withstanding layer 2, the first p-type material layer 91 in the active region a is connected to the p-base layer 3, while the third p-type material layer 93 in the termination region C is also connected to the p-base layer 3.
And S8, depositing metal Ni on the inner edge walls of the first p-type material layer 91 and the second p-type material layer 92 respectively to obtain a first metal layer 101 and a second metal layer 102 (figure 9), enabling the first metal layer 101 to form ohmic contact with the first p-type material layer 91, and enabling the second metal layer 102 to form ohmic contact with the second p-type material layer 92.
S9, depositing a first interlayer dielectric 111 on the upper surface of the gate electrode 8; depositing a second interlayer dielectric 112 inside the first recess where the gate electrode 8 is not provided; a third interlayer dielectric 113 is deposited inside the second grooves, inside each of the third grooves and on the surface of the conductive layer 4 of the termination region C, respectively, so that the third interlayer dielectric 113 of the transition region B and the termination region C are integrated (fig. 10). And respectively patterning the first interlayer medium, the second interlayer medium and the third interlayer medium.
S10, depositing a source metal layer (such as a Ti/Al/Pt alloy layer) on the surface of the conductive layer 4 of the active region A and the surface of the first interlayer dielectric 111, patterning, and tempering to enable the source metal layer to form ohmic contact with the conductive layer 4, wherein the source metal layer extends to the surfaces of the second interlayer dielectric 112 and the third interlayer dielectric 113 towards two sides respectively, so as to obtain the source 12. Thus, a complete gallium oxide field effect transistor was prepared (fig. 11).
Example 3
As shown in fig. 12, this embodiment provides a gallium oxide field effect transistor, whose structure is different from that of embodiment 2 in that: the bottom of the second groove is also provided with a high-resistance layer 5.
The method of manufacturing a gallium oxide field effect transistor in this example is the same as that of example 2.
Example 4
As shown in fig. 13, the present embodiment provides a gallium oxide field effect transistor, whose structure is different from that of embodiment 2 in that: the bottom end of the interior of the second recess is also deposited with a high-resistance layer 5, and the bottom end of the interior of at least one of the third recesses is also deposited with a high-resistance layer 5.
The method of manufacturing a gallium oxide field effect transistor in this example is the same as that of example 2.
Example 5
As shown in fig. 14, the present embodiment provides a gallium oxide field effect transistor, whose structure is different from that of embodiment 2 in that: the bottom ends of the interiors of the plurality of third grooves are deposited with a high-resistance layer 5.
The method of manufacturing a gallium oxide field effect transistor in this example is the same as that of example 2.
Example 6
As shown in fig. 15, the present embodiment provides a gallium oxide field effect transistor, whose structure is different from that of embodiment 2 in that: the depth of the first recess provided with the gate electrode 8 in the active region a is smaller than the depth of the first recess (provided with the first p-type material layer 91) not provided with the gate electrode, while also being smaller than the depth of the second recess; the bottom ends of the interiors of the plurality of third grooves are deposited with a high-resistance layer 5.
The method of manufacturing a gallium oxide field effect transistor in this example is the same as that of example 2.
Example 7
As shown in fig. 16, the present embodiment provides a gallium oxide field effect transistor, whose structure is different from that of embodiment 2 in that: the depth of the third recess in the termination region C is equal to the thickness of the conductive layer 4 so that the third p-type material layer 93 is just connected to the p-base layer 3.
The method of manufacturing a gallium oxide field effect transistor in this example is the same as that of example 2.
Example 8
As shown in fig. 17, this embodiment provides a gallium oxide field effect transistor, whose structure is different from that of embodiment 2 in that: the depth of the third recess in the termination region C is smaller than the thickness of the conductive layer 4 so that the third p-type material layer 93 is not connected to the p-base layer 3.
The method of manufacturing a gallium oxide field effect transistor in this example is the same as that of example 2.
Example 9
As shown in fig. 18, this embodiment provides a gallium oxide field effect transistor, whose structure is different from that of embodiment 2 in that: at least one N is also arranged in the terminal area C + A blocking ring 13.
The method for manufacturing a gallium oxide field effect transistor in this embodiment is substantially the same as embodiment 2, except that step S3 further includes the steps of:
forming a photoetching window between any two non-adjacent third grooves of the terminal area C or at the tail part of the terminal area C, which is not provided with the third grooves, by adopting a photoetching process, and then implanting silicon element by an ion implanter, wherein the implantation concentration is 1 multiplied by 10 19 cm -3 Activating at 1200+ -50deg.C for 30 min to form N + A blocking ring 13. Is provided with N + In the region of the blocker ring 13, the third recess has a depth greater than that of the non-N recess + The depth of the third groove in the region of the blocker ring 13 is small.
The foregoing description is only of the preferred embodiments of the invention and is not intended to limit the scope of the invention. Various modifications and alterations of this invention will occur to those skilled in the art. Any and all such simple and equivalent variations and modifications are intended to be included within the scope of this invention.
Claims (10)
1. The gallium oxide field effect transistor is characterized by comprising a drain electrode, a gallium oxide substrate, a voltage-resistant layer, a p base layer and a conductive layer which are sequentially arranged; the voltage-resistant layer, the p base layer and the conducting layer form an epitaxial layer with a sandwich structure; the epitaxial layer comprises an active region, a transition region and a terminal region, wherein the transition region is positioned between the active region and the terminal region; the active region is provided with a plurality of first grooves, and the bottom end of the interior of at least one first groove is provided with a high-resistance layer; a gate dielectric layer is arranged on the inner edge wall of the first groove provided with the high-resistance layer, a gate electrode is arranged in the gate dielectric layer, and a first interlayer dielectric is arranged on the upper surface of the gate electrode; a first p-type material layer is arranged on the inner edge wall of the first groove without the high-resistance layer; the transition region is provided with a second groove, and a second p-type material layer is arranged along the inner wall of the second groove; a plurality of third grooves are formed in the terminal end at intervals, and a third p-type material layer is arranged in each third groove along the wall; a source electrode is arranged on the surface of the conducting layer of the active region and the surface of the first interlayer medium, and two ends of the source electrode are respectively connected with the first p-type material layer and the second p-type material layer; the voltage-resistant layer and the conductive layer are both N-type semiconductor layers.
2. Gallium oxide field effect transistor according to claim 1, wherein a first metal layer is provided on the surface of the first p-type material layer and a second metal layer is provided on the surface of the second p-type material layer.
3. Gallium oxide field effect transistor according to claim 2, wherein the first recess provided with the first metal layer is filled with a second interlayer dielectric inside; and third interlayer media are arranged in the second grooves, in each third groove and on the surface of the conductive layer of the terminal area.
4. The gallium oxide field effect transistor according to claim 1, wherein a bottom end of an interior of the second groove is provided with a high-resistance layer; or/and the bottom end of the inner part of at least one third groove is provided with a high-resistance layer.
5. The gallium oxide field effect transistor of claim 1, wherein a depth of the first recess in the active region in which the gate dielectric layer is disposed is less than a depth of the first recess in which the first p-type material layer is disposed and less than a depth of the second recess.
6. The gallium oxide field effect transistor of claim 1, wherein the depth of the third recess is greater than or equal to the thickness of the conductive layer.
7. The gallium oxide field effect transistor of claim 1, wherein the termination region comprises at least one N + A blocking ring.
8. The method for manufacturing a gallium oxide field effect transistor according to any one of claims 1 to 7, comprising the steps of:
sequentially growing a pressure-resistant layer, a p base layer and a conductive layer on a gallium oxide substrate to form an epitaxial layer with a sandwich structure, etching the surface of the epitaxial layer, forming a plurality of first grooves in an active region, forming a second groove in a transition region, and forming a plurality of third grooves in a terminal region;
injecting a protective element into the bottom end of the inside of at least one first groove and tempering to form a high-resistance layer;
depositing a drain metal layer on one side of the gallium oxide substrate far away from the pressure-resistant layer, and tempering to obtain a drain;
depositing a gate dielectric layer in the first groove provided with the high-resistance layer, and then depositing a conductive material to manufacture a gate electrode; depositing a first interlayer medium on the upper surface of the gate electrode;
depositing and patterning p-type materials in the first groove, the second groove and each third groove which are not provided with the high-resistance layer to respectively obtain a first p-type material layer, a second p-type material layer and a third p-type material layer;
and depositing a source electrode metal layer on the surface of the conducting layer of the active region and the surface of the first interlayer medium, and respectively connecting the source electrode metal layer with the first p-type material layer and the second p-type material layer to obtain a source electrode.
9. The method of preparing as claimed in claim 8, further comprising the steps of: and depositing a first metal layer on the surface of the first p-type material layer, and depositing a second metal layer on the surface of the second p-type material layer.
10. The method of manufacturing according to claim 9, further comprising the step of: depositing a second interlayer medium in the first groove in which the first metal layer is deposited, and respectively depositing a third interlayer medium in the second groove, in each third groove and on the surface of the conductive layer of the terminal area; the source metal layer extends to the surfaces of the second interlayer dielectric and the third interlayer dielectric.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107293599A (en) * | 2017-07-19 | 2017-10-24 | 中国科学院微电子研究所 | Silicon carbide power device terminal and preparation method thereof |
| CN110120425A (en) * | 2019-05-22 | 2019-08-13 | 西安电子科技大学 | The high-voltage MOSFET device and production method of vertical-type |
| WO2019191465A1 (en) * | 2018-03-28 | 2019-10-03 | Cornell University | VERTICAL GALLIUM OXIDE (Ga2O3) POWER FETS |
| CN113257922A (en) * | 2021-05-13 | 2021-08-13 | 电子科技大学 | Multi-channel enhanced gallium oxide junction field effect transistor |
| CN114743881A (en) * | 2022-04-28 | 2022-07-12 | 中国电子科技集团公司第十三研究所 | Gallium oxide vertical field effect transistor preparation method and field effect transistor |
| CN116053297A (en) * | 2023-01-10 | 2023-05-02 | 湖北九峰山实验室 | Multistage groove enhanced power device and preparation method thereof |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101932576B1 (en) * | 2010-09-13 | 2018-12-26 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and method for manufacturing the same |
| JP6284140B2 (en) * | 2013-06-17 | 2018-02-28 | 株式会社タムラ製作所 | Ga2O3 semiconductor device |
| US9214539B2 (en) * | 2013-09-03 | 2015-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gallium nitride transistor with a hybrid aluminum oxide layer as a gate dielectric |
| TWI701715B (en) * | 2017-06-06 | 2020-08-11 | 黃知澍 | N-face III/nitride epitaxy structure and its active device and its integration of polarity inversion manufacturing method |
| CN111223782B (en) * | 2019-11-26 | 2020-10-20 | 中国科学院上海微***与信息技术研究所 | Gallium oxide semiconductor structure, vertical gallium oxide-based power device and preparation method |
| JP2023000187A (en) * | 2021-06-17 | 2023-01-04 | 株式会社デンソー | Semiconductor device and method for manufacturing the same |
-
2023
- 2023-06-01 CN CN202310640409.9A patent/CN116417520B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107293599A (en) * | 2017-07-19 | 2017-10-24 | 中国科学院微电子研究所 | Silicon carbide power device terminal and preparation method thereof |
| WO2019191465A1 (en) * | 2018-03-28 | 2019-10-03 | Cornell University | VERTICAL GALLIUM OXIDE (Ga2O3) POWER FETS |
| CN110120425A (en) * | 2019-05-22 | 2019-08-13 | 西安电子科技大学 | The high-voltage MOSFET device and production method of vertical-type |
| CN113257922A (en) * | 2021-05-13 | 2021-08-13 | 电子科技大学 | Multi-channel enhanced gallium oxide junction field effect transistor |
| CN114743881A (en) * | 2022-04-28 | 2022-07-12 | 中国电子科技集团公司第十三研究所 | Gallium oxide vertical field effect transistor preparation method and field effect transistor |
| CN116053297A (en) * | 2023-01-10 | 2023-05-02 | 湖北九峰山实验室 | Multistage groove enhanced power device and preparation method thereof |
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