CN116314259A - Super-junction SiC MOSFET containing rare earth gate dielectric layer and manufacturing method thereof - Google Patents
Super-junction SiC MOSFET containing rare earth gate dielectric layer and manufacturing method thereof Download PDFInfo
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- 229910052761 rare earth metal Inorganic materials 0.000 title claims abstract description 65
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- 239000002184 metal Substances 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 38
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- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000005468 ion implantation Methods 0.000 claims description 23
- 238000000151 deposition Methods 0.000 claims description 14
- 238000001259 photo etching Methods 0.000 claims description 13
- 238000005566 electron beam evaporation Methods 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 9
- 238000002161 passivation Methods 0.000 claims description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 7
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 5
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 4
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- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 239000002253 acid Substances 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims 4
- 150000002576 ketones Chemical class 0.000 claims 1
- 238000010276 construction Methods 0.000 abstract description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 35
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- 238000010586 diagram Methods 0.000 description 13
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- 238000009826 distribution Methods 0.000 description 7
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- 230000001105 regulatory effect Effects 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 230000005684 electric field Effects 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 238000001755 magnetron sputter deposition Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 150000001768 cations Chemical class 0.000 description 3
- 239000002131 composite material Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
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- 239000012535 impurity Substances 0.000 description 2
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- 125000004430 oxygen atom Chemical group O* 0.000 description 2
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- 239000011248 coating agent Substances 0.000 description 1
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Abstract
The invention discloses a super-junction SiC MOSFET containing a rare earth gate dielectric layer and a manufacturing method thereof. Wherein, the structure includes: a metal layer, a substrate; the P-pilar region is arranged at the upper part of the substrate and comprises a plurality of P-pilar arranged at intervals; the epitaxial layer is arranged at the upper part and the interval of the P-pilar region; the P well regions are arranged on two sides of the upper part of the epitaxial layer, and JFET regions are formed in the middle of the P well regions; a P+ source region is arranged at the edge position of one side, far away from the JFET region, of the upper part of the P well region, and an N+ source region is arranged on one side, close to the JFET region; the upper part of the JFET region is provided with a gate oxide layer region which is in contact with the JFET region, the P well region and the N+ source region; the gate oxide region comprises a plurality of rare earth gate oxide layers and the like. The invention combines a drift region vertical P/N super junction (Supe)r junction), P+/N+ super junction structure and three rare earth gate dielectric layers (Al 2 O 3 /Gd 2 O 3 /SiO 2 ) A method of construction; the P+/N+ super junction structure at the lower section of the source electrode and the vertical P/N super junction structure at the lower end of the drift region are utilized to effectively reduce the source electrode contact resistance and the device drift region resistance, and reduce the on resistance and the device loss of the device.
Description
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to a super-junction SiC MOSFET containing a rare-earth gate dielectric layer and a manufacturing method thereof.
Background
MOSFETs are a type of switching device that can control large currents and voltages with small voltages, and this feature is widely used in analog circuits and digital circuits. After the grid voltage of the device reaches the threshold voltage, holes at the P well region position form a corresponding N channel under the action of reverse voltage, and the source electrode and the drain electrode are connected to form a conducting state.
Due to the nature of the material itself, si devices perform poorly in some extreme environments (e.g., high temperature, high pressure, high power, and high radiation), failing to meet the needs of the relevant application. The third generation semiconductor material silicon carbide (SiC) overcomes the defects of small band gap, low critical breakdown field strength, low thermal conductivity and the like of Si materials by the excellent physical characteristics, and becomes an ideal material for replacing Si. Silicon carbide (SiC) has a wide band gap, a high critical electric field, and a high thermal conductivity, and is the most promising material for next-generation power device applications.
At present, the cell size of the SiC MOSFET device is reduced along with the continuous reduction of the size of the power device, and the thickness of the gate oxide layer of the device is also reduced along with the continuous reduction of the size of the power device. When the thickness of the gate oxide is reduced to some extent, tunneling may occur in the SiC MOSFET device at the gate location, and in order to maintain the stability of the device gate, a high dielectric constant (high K) oxide layer is typically introduced in the prior art as the gate oxide of the device, with the most common high K oxide comprising Al 2 O 3 ，HfO 2 ，TiO 2 Etc. Due to the fact that in Al 2 O 3 /SiO 2 The dipole layer at the interface will have unavoidable effect on threshold voltage, when the gate oxide layer of the SiC MOSFET device is Al 2 O 3 /SiO 2 At this time, the threshold voltage of the SiC MOSFET device will fluctuate significantly. Therefore, how to improve the stability of the threshold voltage of the SiC MOSFET device is a technical problem to be overcome. Second, siC MOSFET deviceThe impurity concentration of the drift layer is low, and the resistance value of the drift layer is relatively large; the depletion layer of the SiC MOSFET device is in a horizontal state, and the resistance value of the drift layer is further improved. How to reduce the resistance of the drift layer and reduce the dynamic loss is a technical difficulty to be overcome. In addition, the contact performance between the source metal layer and the n+ source region of the SiC MOSFET device is relatively poor. Therefore, how to improve the source contact performance of the device is also a technical problem to be solved.
Disclosure of Invention
Accordingly, the present invention is directed to a Super junction SiC MOSFET with a rare earth gate dielectric layer and a method for fabricating the same, which combines a drift region vertical P/N Super junction (Super junction), a P+/N+ Super junction structure and three rare earth gate dielectric layers (Al 2 O 3 /Gd 2 O 3 /SiO 2 ) A method of construction; the P+/N+ super junction structure at the lower section of the source electrode and the vertical P/N super junction structure at the lower end of the drift region are utilized to effectively reduce the source electrode contact resistance and the resistance of the drift region of the device, reduce the on resistance and the loss of the device and regulate and control the electric field distribution condition of the device; with a three-layer rare earth oxide composite structure (Al 2 O 3 /Gd 2 O 3 /SiO 2 ) Gd is used as a gate dielectric layer 2 O 3 The attraction of Gd cations to oxygen atoms can effectively reduce the Al content of the high-k gate dielectric layer 2 O 3 /SiO 2 The resulting dipole layer affects the threshold voltage while maintaining the high dielectric constant state of the device gate oxide.
According to one aspect of the present invention, there is provided a superjunction SiC MOSFET including a rare earth gate dielectric layer, comprising: a metal layer, a substrate; the P-pilar region is arranged at the upper part of the substrate and comprises a plurality of P-pilar arranged at intervals; the epitaxial layer is arranged at the upper part and the interval of the P-pilar region; the P well regions are arranged on two sides of the upper part of the epitaxial layer, and JFET regions are formed in the middle of the P well regions; a P+ source region is arranged at the edge position of one side, far away from the JFET region, of the upper part of the P well region, and an N+ source region is arranged on one side, close to the JFET region; the upper part of the JFET region is provided with a gate oxide layer region which is in contact with the JFET region, the P well region and the N+ source region; the gate oxide layer region comprises a plurality of rare earth gate oxide layers; the upper part of the gate oxide layer area is sequentially provided with a gate metal layer, a passivation layer covering the gate oxide layer area and the gate metal layer; and source metal layers are covered on the upper parts of the P+ source region and the N+ source region.
According to another aspect of the present invention, there is provided a method for manufacturing a super junction SiC MOSFET including a rare earth gate dielectric layer, the method comprising: step 101, evaporating a metal layer on the back of an N-type SiC substrate by adopting an electron beam evaporation mode, and obtaining ohmic contact by utilizing a rapid annealing process; step 102, carrying out epitaxy on the upper part of an N-type SiC substrate to obtain an N-type first epitaxial layer; step 103, setting P-pilers at equal intervals on the top of the SiC substrate by utilizing ion implantation and a photoetching mask to form a P-piler region; 104, epitaxially obtaining a second epitaxial layer of N-type SiC on the upper part of the P-pilar region; step 105, preparing a corresponding P well region, a P+ source region and an N+ source region on the epitaxial layer by utilizing an ion implantation mode to form a corresponding JFET region; step 106, depositing the upper parts of the JFET region, the P well region and the N+ source region to obtain the rare earth gate oxide region; step 107, depositing the gate metal layer on the rare earth gate oxide region by utilizing a photoetching and electron beam evaporation mode; step 108, depositing corresponding source metal layers on the upper parts of the P+ source region and part of the N+ source region by utilizing a photoetching and electron beam evaporation mode; and 109, depositing a passivation layer between the source metal layer and the gate metal layer by using a photoetching and MOCVD growth mode.
It can be found that the invention combines the drift region vertical PN Super junction (Super junction), the P+/N+ Super junction structure and three rare earth gate dielectric layers (Al 2 O 3 /Gd 2 O 3 /SiO 2 ) A method of construction; the P+/N+ super junction structure at the lower section of the source electrode and the vertical P/N super junction structure at the lower end of the drift region are utilized to effectively reduce the source electrode contact resistance and the resistance of the drift region of the device, reduce the on resistance and the loss of the device and regulate and control the electric field distribution condition of the device; with a three-layer rare earth oxide composite structure (Al 2 O 3 /Gd 2 O 3 /SiO 2 ) Gd is used as a gate dielectric layer 2 O 3 Attraction of Gd, a cation of (C) to oxygen atomsCan effectively reduce the Al of the high-k gate dielectric layer 2 O 3 /SiO 2 The resulting dipole layer affects the threshold voltage while maintaining the high dielectric constant state of the device gate oxide.
It can be seen that, in the above scheme,
(1) And a vertical P/N super junction structure at the lower ends of the JFET region and the drift region. The distribution condition of the JFET region and the drift region depletion layer can be effectively regulated and controlled by utilizing the vertical P/N super junction structure, the on-resistance of the device in the drift region is reduced, the power consumption and junction temperature of the device are further reduced, and the stability of the device is improved;
(2) A p+/n+ structure is used at the location where it contacts the source metal layer. The P+/N+ super junction structure can effectively reduce the source electrode contact resistance of the device, effectively reduce the junction temperature of the device, further reduce the size of the device and improve the integration of the device;
(3) By rare earth oxide Gd 2 O 3 For Al 2 O 3 /SiO 2 Attraction of dipoles (oxygen vacancies) at interface locations to cause Al 2 O 3 /SiO 2 The dipole concentration at the interface is obviously reduced, and the fluctuation of the threshold voltage of the device is effectively restrained.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of a preferred embodiment of the present invention;
FIG. 2 is a schematic diagram of a vertical P/N superjunction structure process step 3.1 in accordance with a preferred embodiment of the present invention;
FIG. 3 is a schematic diagram of a vertical P/N superjunction structure process step 3.2 in accordance with a preferred embodiment of the present invention;
FIG. 4 is a schematic diagram of a vertical P/N superjunction structure process step 3.3 in accordance with a preferred embodiment of the present invention;
FIG. 5 is a schematic diagram of a vertical P/N superjunction structure process step 3.4 in accordance with a preferred embodiment of the present invention;
FIG. 6 is a schematic diagram of a vertical P/N superjunction structure process step 3.5 in accordance with a preferred embodiment of the present invention;
FIG. 7 is a schematic diagram of a P+/N+ superjunction process step 5.1 in a preferred embodiment of the present invention;
FIG. 8 is a schematic diagram of a P+/N+ superjunction process step 5.2 in a preferred embodiment of the present invention;
FIG. 9 is a schematic diagram of a P+/N+ superjunction process step 5.3 in a preferred embodiment of the present invention;
FIG. 10 is a schematic diagram of a gate oxide structure process step 6.1 in a preferred embodiment of the present invention;
FIG. 11 is a schematic diagram of a gate oxide structure process step 6.2 in a preferred embodiment of the present invention;
FIG. 12 is a schematic diagram of a gate oxide structure process step 6.3 in a preferred embodiment of the present invention;
FIG. 13 is a schematic diagram of a gate metal layer process step 5.3 in a preferred embodiment of the present invention;
fig. 14 is a schematic view of the process steps of source, gate and passivation layers in a preferred embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is specifically noted that the following examples are only for illustrating the present invention, but do not limit the scope of the present invention. Likewise, the following examples are only some, but not all, of the examples of the present invention, and all other examples, which a person of ordinary skill in the art would obtain without making any inventive effort, are within the scope of the present invention.
The invention provides a Super junction SiC MOSFET containing a rare earth gate dielectric layer, which combines a drift region vertical PN Super junction (Super junction), a P+/N+ Super junction structure and three rare earth gate dielectric layers (Al) 2 O 3 /Gd 2 O 3 /SiO 2 ) A method of construction; by using the P+/N+ super junction structure of the lower section of the source electrode and the vertical P/N super junction structure of the lower end of the drift regionThe source contact resistance and the device drift region resistance are effectively reduced, the on-resistance and the device loss of the device are reduced, and the electric field distribution condition of the device is regulated and controlled.
The structure comprises a P-pilar region arranged on the upper part of a substrate, and a plurality of P-pilar regions arranged at intervals; the epitaxial layer is arranged at the upper part and the interval of the P-pilar region; the P well regions are arranged on two sides of the upper part of the epitaxial layer, and JFET regions are formed in the middle of the P well regions; a P+ source region is arranged at the edge position of one side, far away from the JFET region, of the upper part of the P well region, and an N+ source region is arranged on one side, close to the JFET region; the upper part of the JFET region is provided with a gate oxide layer region which is in contact with the JFET region, the P well region and the N+ source region; the gate oxide layer region comprises a plurality of rare earth gate oxide layers; the upper part of the gate oxide layer area is sequentially provided with a gate metal layer, a passivation layer covering the gate oxide layer area and the gate metal layer; and source metal layers are covered on the upper parts of the P+ source region and the N+ source region.
As a preferred embodiment, please refer to fig. 1 in particular. The structure in this embodiment includes: a substrate 2; a drain metal layer 1 located at the lower part of the substrate 2; a P-pilar region 3 located on the upper part of the substrate 2, and interposed between the substrate 2 and the epitaxial layer 4; an epitaxial layer 4 is positioned on the upper surface of the P-pilar region 3; the JFET region 5 is positioned at the middle upper part of the epitaxial layer 4 and is arranged between the adjacent P-well regions 6, and the width of the JFET region is 3 mu m; a P well region 6 which is positioned at the upper part of the epitaxial layer 4, two sides of the JFET region 5 and has a width of 7.5 mu m; the P+ source region 7 is positioned at the edge position above the P well region 6; an n+ source region 8 located above the P well region 6 and close to the p+ source region 7; gate oxide regions 9, 10, 11 are located on the upper portions of the P-well region 6, JFET region 5, and part of the n+ source region 8, the gate oxide regions 9, 10, 11 having a structure of (Al 2 O 3 /Gd 2 O 3 /SiO 2 ) The structure of the first gate oxide layer 9 at the upper parts of the P well region 6, the JFET region 5 and part of the N+ source region 8 is Al 2 O 3 The second gate oxide layer 10 has the structure of Gd 2 O 3 The third gate oxide layer 11 has a structure of SiO 2 The method comprises the steps of carrying out a first treatment on the surface of the A gate metal layer 12 located on top of the gate oxide regions 9, 10, 11; a source metal 13 located at the upper portions of the p+ source region 7 and the partial n+ source region 8; si (Si) 3 N 4 A passivation layer 14 positioned on theBetween the source metal layer 13 and the gate metal layer 12.
In this embodiment, the P-pilar regions are disposed at equal intervals, the P-pilar 3 is disposed at intervals of 0.1-0.9 μm from left to right, the P-pilar 3 is disposed at a depth of 0.5-1.5 μm, and the P-pilar regions are disposed at a width of 0.1-0.9 μm, and the P-pilar regions have a cross-sectional shape of one or more of square, rectangle, and circle. Preferably, the P-pilar regions are arranged at equal intervals, the interval of the P-pilar regions from left to right is 0.5 mu m, the depth is 1 mu m, the width is 0.1-0.9 mu m, and the cross section shape is rectangular; it should be understood that the arrangement is to ensure that the contact resistance can be effectively reduced, the loss of the device is reduced, and the electric field distribution condition of the device is regulated and controlled; the specific size settings may be varied according to different needs.
In this embodiment, the gate oxide region includes a first rare earth gate oxide layer 11, and the height of the first rare earth gate oxide layer 11 is 5-8nm; the gate oxide layer region comprises a second rare earth gate oxide layer 12, and the height of the second rare earth gate oxide layer 12 is 20-25nm; the gate oxide layer region comprises a plurality of third rare earth gate oxide layers 13, and the height of the third rare earth gate oxide layers 13 is 8-12nm. The gate oxide layer region comprises a first rare earth gate oxide layer, a second rare earth gate oxide layer and a third rare earth gate oxide layer, and the rare earth gate oxide layer is made of Al 2 O 3 、Gd 2 O 3 、SiO 2 One or more of the following. Preferably, the gate oxide region includes a first rare earth gate oxide 11, a second rare earth gate oxide 12 and a third rare earth gate oxide 13, which are disposed once, and the material of the first rare earth gate oxide 11 is Al 2 O 3 The material of the second rare earth gate oxide layer 12 is Gd 2 O 3 The third rare earth gate oxide layer 13 is made of SiO 2 . With a three-layer rare earth oxide composite structure (Al 2 O 3 /Gd 2 O 3 /SiO 2 ) Gd is used as a gate dielectric layer 2 O 3 The attraction of Gd cations to oxygen atoms can effectively reduce the Al content of the high-k gate dielectric layer 2 O 3 /SiO 2 The resulting dipole layer affects the threshold voltage while maintaining the high dielectric constant state of the device gate oxide. Grid electrodeThe polar oxide layer adopts Al 2 O 3 /Gd 2 O 3 /SiO 2 Is a structural design of the device. By rare earth oxide Gd 2 O 3 For Al 2 O 3 /SiO 2 Attraction of dipoles (oxygen vacancies) at interface locations to cause Al 2 O 3 /SiO 2 The dipole concentration at the interface is obviously reduced, and the fluctuation of the threshold voltage of the device is effectively restrained.
It can be seen that, in the above scheme,
(1) And a vertical P/N super junction structure at the lower ends of the JFET region and the drift region. The distribution condition of the JFET region and the drift region depletion layer can be effectively regulated and controlled by utilizing the vertical P/N super junction structure, the on-resistance of the device in the drift region is reduced, the power consumption and junction temperature of the device are further reduced, and the stability of the device is improved;
(2) A p+/n+ structure is used at the location where it contacts the source metal layer. The P+/N+ super junction structure can effectively reduce the source electrode contact resistance of the device, effectively reduce the junction temperature of the device, further reduce the size of the device and improve the integration of the device;
(3) The gate oxide layer adopts Al 2 O 3 /Gd 2 O 3 /SiO 2 Is a structural design of the device. By rare earth oxide Gd 2 O 3 For Al 2 O 3 /SiO 2 Attraction of dipoles (oxygen vacancies) at interface locations to cause Al 2 O 3 /SiO 2 The dipole concentration at the interface is obviously reduced, and the fluctuation of the threshold voltage of the device is effectively restrained.
The invention also provides a method for preparing the super junction SiC MOSFET containing the rare earth gate dielectric layer, which comprises the following steps:
step 101, evaporating the back of an N-type SiC substrate by adopting an electron beam evaporation mode to obtain a drain metal layer, and then obtaining ohmic contact by utilizing a rapid annealing process;
step 102, carrying out epitaxy on the upper part of an N-type SiC substrate to obtain an N-type first epitaxial layer;
step 103, setting P-pilers at equal intervals on the top of the SiC substrate by utilizing ion implantation and a photoetching mask to form a P-piler region;
104, epitaxially obtaining a second epitaxial layer of N-type SiC on the upper part of the P-pilar region;
step 105, preparing a corresponding P well region, a P+ source region and an N+ source region on the epitaxial layer by utilizing an ion implantation mode to form a corresponding JFET region;
step 106, depositing the upper parts of the JFET region, the P well region and the N+ source region to obtain the rare earth gate oxide region;
step 107, depositing the gate metal layer on the rare earth gate oxide region by utilizing a photoetching and electron beam evaporation mode;
step 108, depositing corresponding source metal layers on the upper parts of the P+ source region and part of the N+ source region by utilizing a photoetching and electron beam evaporation mode;
and 109, depositing a passivation layer between the source metal layer and the gate metal layer by using a photoetching and MOCVD growth mode.
As a preferred embodiment, the specific steps are as follows:
1. evaporating the back of the N-type SiC substrate 2 by adopting an electron beam evaporation mode to obtain a Ni/Au drain electrode metal layer 1, and then obtaining ohmic contact by utilizing a rapid annealing process;
2. referring to FIG. 2, an epitaxial layer 4 is epitaxially formed on an upper portion of an N-type SiC substrate 2, the doping concentration of the N-type SiC being 1×10 15 cm -3 ；
3. Referring to FIGS. 2-6, P-pilar regions 3 of the same pitch are prepared on top of a SiC substrate 2 by ion implantation and photolithographic masking, the P-type SiC doping concentrations being respectively 1×10 15 cm -3 ；
4. Referring to fig. 7, the epitaxial layer 4 is re-epitaxially grown on the upper portion of the P-pilar region 3 to obtain an N-type SiC epitaxial layer 4;
5. referring to fig. 8-9, corresponding P-well regions 6, p+ source regions 7, n+ source regions 8 are prepared on the N-type SiC epitaxial layer 4 by means of ion implantation to form corresponding JFET regions 5;
6. referring to FIGS. 10-12, in the P-well region 6, JFET region 5, and portion of N+ source region 8Upper deposition to obtain the desired Al 2 O 3 /Gd 2 O 3 /SiO 2 Gate oxide regions 9, 10, 11;
7. referring to fig. 13, a corresponding gate metal layer 12 is deposited on the gate oxide regions 9, 10, 11 by photolithography and electron beam evaporation;
8. referring to fig. 14, a corresponding source metal layer 13 is deposited on the p+ source region 7 and a portion of the n+ source region 8 by photolithography and electron beam evaporation; si is deposited between the source metal layer 13 and the gate metal layer 12 by using the photoetching and MOCVD growth modes 3 N 4 A passivation layer 14.
In this embodiment, in the step 3, the specific process of preparing the P-pilar regions 3 with the same pitch on top of the SiC substrate by using the manner of ion implantation and photolithographic masking is as follows:
3.1 referring to fig. 2, the upper part of the epitaxial layer 4 is subjected to a photolithography process to obtain the shape required by P-pilar 3;
3.2 referring to FIG. 3, siO with thickness of 300-500nm is grown by MOCVD directly above the N-type SiC epitaxial layer 4 and the photoresist 301 2 Is a mask layer 302;
3.3 referring to fig. 4, the photoresist 301 is cleaned by acetone and ethanol to obtain an ion implanted mask layer 302;
3.4 referring to FIG. 5, a corresponding 1×10 is obtained by aluminum ion implantation directly above the N-type SiC drift layer 4 and the photoresist 301 15 cm -3 P-pilar region 3 of (a);
3.5 referring to FIG. 6, the device is SiO-doped with 1% HF acid solution 2 Is cleaned of the mask layer 302.
The purpose of this arrangement is a vertical P/N superjunction structure of the JFET region and the lower end of the drift region. The distribution of the JFET region and the drift region depletion layer can be effectively regulated and controlled by utilizing the vertical P/N super junction structure, the on-resistance of the device in the drift region is reduced, the power consumption and junction temperature of the device are further reduced, and the stability of the device is improved.
In this embodiment, step 5, the specific process of forming the corresponding JFET region 5 by preparing the corresponding P well region 6, p+ source region 7, n+ source region 8 on the N-type SiC epitaxial layer 4 by using an ion implantation method is as follows:
5.1 referring to FIG. 7, a JFET region 5 having a width of 7 μm, a depth of 3 μm, and a concentration of 1×10 is formed on the upper portion of the N-type epitaxial layer by aluminum ion implantation 16 cm -3 P-well region 6 of (a);
5.2 referring to FIG. 8, a width of 2.5 μm, a depth of 1 μm, and a concentration of 1×10 are prepared at the upper edge of the P-well region 6 by using an oxide layer mask and aluminum ion implantation 18 cm -3 P+ source region 7 of (a);
5.3 referring to FIG. 9, a width of 2.5 μm is prepared at a position above the P well region 6 and near the P+ source region 7 by using an oxide layer mask and nitrogen ion implantation to obtain a depth of 1 μm and a concentration of 1×10 18 cm -3 N+ source region 8 of (a).
The purpose of this is to adopt a p+/n+ structure at the location of contact with the source metal layer. The P+/N+ super junction structure can effectively reduce the source electrode contact resistance of the device, effectively reduce the junction temperature of the device, further reduce the size of the device and improve the integration of the device.
In this embodiment, step 6, a specific process of obtaining the corresponding three-layer rare earth gate oxide structure by using PVD (magnetron sputtering) and ALD (atomic layer deposition) growth methods is as follows:
6.1 referring to FIG. 10, the P-well region 6, JFET region 5, and part of the N+ source region 8 are deposited with Al having a thickness of 5-8nm by ALD (atomic layer deposition) 2 O 3 A first rare earth gate oxide layer 11;
6.2 referring to FIG. 11, the method of PVD (magnetron sputtering) is used for forming a coating on Al 2 O 3 Gd with thickness of 20-25nm is deposited on 2 O 3 Wherein the growth conditions are that the vacuum degree of the equipment growth is controlled to be 1 multiplied by 10 -4 Pa, growth pressure is 2.5Pa, ar: O 2 The flow rate ratio of (2) is 30sccm:5sccm, the growth power is 50-70W, and the second rare earth gate oxide layer 12 is obtained;
6.3 referring to FIG. 12, ALD (atomic layer deposition)) In the mode of Gd 2 O 3 Deposition of SiO with thickness of 10nm 2 A third rare earth gate oxide layer 13; .
The purpose of this arrangement is that the gate oxide layer is made of Al 2 O 3 /Gd 2 O 3 /SiO 2 Is a structural design of the device. By rare earth oxide Gd 2 O 3 For Al 2 O 3 /SiO 2 Attraction of dipoles (oxygen vacancies) at interface locations to cause Al 2 O 3 /SiO 2 The dipole concentration at the interface is obviously reduced, and the fluctuation of the threshold voltage of the device is effectively restrained.
The preferred embodiment is a vertical P/N super junction structure comprising a JFET region and a drift region at the lower end, wherein a P+/N+ super junction is obtained by aluminum ion implantation and nitrogen ion implantation at the upper part of an epitaxial layer, two sides of the JFET region and above a P well region, and a rare earth oxide layer (Al) is obtained by ALD (atomic layer deposition) and PVD (magnetron sputtering) at the upper parts of the P well region, the JFET region and a part of the N+ source region 2 O 3 /Gd 2 O 3 /SiO 2 ) Is a structure of (a). The vertical P/N super junction structure is utilized, so that the impurity concentration of the drift layer can be effectively improved, and the resistance and conduction loss of the drift layer of the device are reduced; the P+/N+ super junction is obtained at the upper part of the epitaxial layer, at the two sides of the JFET region and above the P well region in a way of aluminum ion implantation and nitrogen ion implantation at the position close to the P+ source region, so that the contact characteristic between the source electrode and the epitaxial layer is improved, and meanwhile, the working resistance and the working loss of the device are reduced; adopting ALD (atomic layer deposition) and PVD (magnetron sputtering) two common coating processes to obtain corresponding three-layer rare earth gate oxide (Al) 2 O 3 /Gd 2 O 3 /SiO 2 ) The dipole layer at the interface position of the gate oxide layer is regulated, so that the stability of the threshold voltage of the device is improved under the condition that the breakdown voltage of the device is kept unchanged.
The foregoing description is only a partial embodiment of the present invention, and is not intended to limit the scope of the present invention, and all equivalent devices or equivalent processes using the descriptions and the drawings of the present invention or directly or indirectly applied to other related technical fields are included in the scope of the present invention.
Claims (10)
1. A superjunction SiC MOSFET having a rare earth gate oxide layer, comprising: a metal layer, a substrate; characterized by further comprising:
the P-pilar region is arranged at the upper part of the substrate and comprises a plurality of P-pilar arranged at intervals; the epitaxial layer is arranged at the upper part and the interval of the P-pilar region; the P well regions are arranged on two sides of the upper part of the epitaxial layer, and JFET regions are formed in the middle of the P well regions; a P+ source region is arranged at the edge position of one side, far away from the JFET region, of the upper part of the P well region, and an N+ source region is arranged on one side, close to the JFET region; the upper part of the JFET region is provided with a gate oxide layer region which is in contact with the JFET region, the P well region and the N+ source region; the gate oxide layer region comprises a plurality of rare earth gate oxide layers; the upper part of the gate oxide layer area is sequentially provided with a gate metal layer, a passivation layer covering the gate oxide layer area and the gate metal layer; and source metal layers are covered on the upper parts of the P+ source region and the N+ source region.
2. A super junction SiC MOSFET having a rare earth gate oxide according to claim 1, characterized in that said plurality of P-pilers are arranged at equal intervals and have an interval of 0.1-0.9 μm.
3. A superjunction SiC MOSFET having a rare earth gate oxide according to claim 1 or 2, wherein said P-pilar has a depth of 0.5-1.5 μm and a width of 0.1-0.9 μm.
4. A super junction SiC MOSFET comprising a rare earth gate oxide layer as defined in claim 1,
the gate oxide layer region comprises a plurality of first rare earth gate oxide layers, and the heights of the first rare earth gate oxide layers are 5-8nm;
and/or the number of the groups of groups,
the gate oxide layer region comprises a plurality of second rare earth gate oxide layers, and the height of the second rare earth gate oxide layers is 20-25nm;
and/or the number of the groups of groups,
the gate oxide layer region comprises a plurality of third rare earth gate oxide layers, and the height of each third rare earth gate oxide layer is 8-12nm.
5. A super junction SiC MOSFET comprising a rare earth gate oxide layer as defined in claim 4,
the gate oxide layer region comprises a first rare earth gate oxide layer, a second rare earth gate oxide layer and a third rare earth gate oxide layer which are sequentially arranged from bottom to top, and the rare earth gate oxide layer is made of Al 2 O 3 、Gd 2 O 3 、SiO 2 One or more of the following.
6. A super junction SiC MOSFET comprising a rare earth gate oxide layer as defined in claim 1,
the cross section of the P-pilar is one or more of square, rectangle and round.
7. A method for preparing a super junction SiC MOSFET containing a rare earth gate oxide layer, characterized by being used for preparing a super junction SiC MOSFET containing a rare earth gate oxide layer according to any one of claims 1 to 6; the method comprises the following steps:
step 101, evaporating the back of an N-type SiC substrate by adopting an electron beam evaporation mode to obtain a drain metal layer, and then obtaining ohmic contact by utilizing a rapid annealing process;
step 102, carrying out epitaxy on the upper part of an N-type SiC substrate to obtain an N-type first epitaxial layer;
step 103, setting P-pilers at equal intervals on the top of the SiC substrate by utilizing ion implantation and a photoetching mask to form a P-piler region;
104, epitaxially obtaining a second epitaxial layer of N-type SiC on the upper part of the P-pilar region;
step 105, preparing a corresponding P well region, a P+ source region and an N+ source region on the epitaxial layer by utilizing an ion implantation mode to form a corresponding JFET region;
step 106, depositing the upper parts of the JFET region, the P well region and the N+ source region to obtain the rare earth gate oxide region;
step 107, depositing the gate metal layer on the rare earth gate oxide region by utilizing a photoetching and electron beam evaporation mode;
step 108, depositing corresponding source metal layers on the upper parts of the P+ source region and part of the N+ source region by utilizing a photoetching and electron beam evaporation mode;
and 109, depositing a passivation layer between the source metal layer and the gate metal layer by using a photoetching and MOCVD growth mode.
8. The method for fabricating a super junction SiC MOSFET including a rare earth gate oxide of claim 7, wherein step 103 further includes obtaining a desired shape of P-pilar on top of the N-type SiC epitaxial layer by photolithography; siO with thickness of 300-500nm is grown right above the N-type SiC epitaxial layer and the photoresist by MOCVD 2 Is a mask layer of the mask layer; performing related cleaning on the photoresist by using acetone and ethanol to obtain an ion implanted mask layer; forming a P-pilar region by aluminum ion implantation right above the N-type SiC epitaxial layer and the photoresist; device SiO using 1% HF acid solution 2 And cleaning the mask layer of the mask layer.
9. The method of fabricating a super junction SiC MOSFET including a rare earth gate oxide of claim 7, wherein step 105 further includes, using aluminum ion implantation to fabricate P-well regions on both sides of the JFET on the upper portion of the N-type epitaxial layer;
preparing a P+ source region at the edge position of one side of the upper part of the P well region far away from the JFET region by using an oxide layer mask and an aluminum ion implantation mode; and preparing an N+ source region at one side of the upper part of the P well region, which is close to the JFET region, by using an oxide layer mask and nitrogen ion implantation mode.
10. The method for fabricating a super junction SiC MOSFET with a rare earth gate oxide layer as defined in claim 7, wherein said step 103 further comprises obtaining a desired shape of P-pilar on the upper portion of the N-type SiC drift layer by photolithography, and growing SiO with a thickness of 300-500nm by MOCVD 2 Is a mask layer of the mask layer; by using the CCarrying out related cleaning on the photoresist by ketone and ethanol to obtain an ion implanted mask layer; the corresponding 1×10 is obtained by aluminum ion implantation directly above the N-type SiC drift layer and the photoresist 15 cm -3 P-pilar region of (a); device SiO using 1% HF acid solution 2 And cleaning the mask layer of the mask layer.
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Inventor after: Yang Weifeng Inventor after: Wang Xinwei Inventor after: Ye Xiaofeng Inventor after: Long Mingtao Inventor before: Yang Weifeng Inventor before: Wang Xinwei Inventor before: Ye Xiaofeng Inventor before: Long Mingtao |