CN117118395A - Digital downsampling filter for Sigma Delta ADC - Google Patents

Abstract

The invention discloses a digital downsampling filter for a Sigma Delta ADC, which belongs to the field of integrated circuit design, wherein the designed digital downsampling filter is a three-stage cascade downsampling digital filter, downsampling is 128 times, and the digital downsampling filter is formed by cascading filters F1, F2 and F3. The filter F1 is formed by cascading 5 single-stage 5-order CIC filters, wherein the downsampling multiple of each single-stage CIC filter is 2, so that the downsampling multiple of F1 is 32; the filter F2 is a low-pass FIR filter, and comprises 33 time delay units, 2 downsampling modules, 34 coefficient modules and 34 adder modules, wherein the downsampling multiple is 2; the filter F3 is a half-band filter, and the structure of the filter is composed of 18 time delay units, 2 downsampling modules, 18 coefficient modules and 17 adders, wherein the downsampling multiple is 2. The digital downsampling filter can filter out high-frequency noise, and reduces the frequency of the signal to the near Nyquist frequency through extraction, so that the required multi-bit digital signal is finally output.

Description

Digital downsampling filter for Sigma Delta ADC

Technical Field

The invention relates to the technical field of integrated circuit design, in particular to a digital downsampling filter for a Sigma Delta ADC.

Background

Integrated circuits may be classified into analog integrated circuits and digital integrated circuits according to the type of signal being processed. In general, a signal whose amplitude and frequency are continuously changed with time is called an analog signal, and a signal whose amplitude and frequency are discrete is called a digital signal. Compared with analog signals, the integrated circuit for processing digital signals has the advantages of high integration level, high data processing speed, good redundancy for the fluctuation of semiconductor technology and the like. Considering that signals in nature are all analog signals, analog-to-digital converters for converting analog signals into digital signals and then processing the digital signals have been developed, and play an important role.

Currently, many types of analog-to-digital converters have emerged, such as Sigma Delta ADC, SAR ADC, pipeline ADC, etc. Among them, the Sigma Delta ADC occupies a large part of the market of analog-to-digital converters. Because the Sigma Delta ADC adopts the technologies of over-sampling, noise shaping and the like, the Sigma Delta ADC can realize higher resolution and lower power consumption under the condition of low speed requirement, and has wide application in the fields of instruments, meters, audio signal processing and the like.

Typically, a Sigma Delta ADC includes two modules, a Sigma Delta modulator and a digital downsampling filter. The modulator module is to oversample and quantize the input signal, noise shaping the noise in the passband such that the in-band quantization noise is reduced and the signal-to-noise distortion ratio is increased. Due to the oversampling technique, the output rate frequency of the modulator is very high and is not suitable for subsequent processing. And a low pass filter is required to process the noise as the quantization noise is moved out of band. Conventional analog filters are not suitable for operation in such multi-rate systems, so digital downsampling filters are the optimal choice.

The current digital downsampling filter technology is basically realized by three-stage cascading of a CIC filter, an FIR half-band filter and an IIR filter. The conventional recursive CIC filter is slow, the half-band filter cannot compensate the passband attenuation well, and the IIR filter introduces nonlinear phase problems. With the development of the market, sigma Delta ADC puts higher demands on the digital filter.

CN106921367B, a digital decimation filter of sigma delta ADC, comprises a digital decimation filter for reducing the sampling frequency and filtering out-of-band quantization noise; the digital decimation filter comprises a CIC filter, an HF filter and an IIR filter which are sequentially connected. Compared with the traditional digital decimation filter, the invention meets the requirements of various downsampling rates by using smaller hardware cost, adopts a three-section structure, designs a new structure of the digital decimation filter according to indexes, and realizes the data precision of 16 bits. On the premise of meeting the requirements of linear phase and stability, an IIR filter is used, so that the hardware cost is further reduced.

In this patent, the CIC filter adopts a conventional recursive structure, is slow, introduces longer bytes, and the passband roll-off problem introduced for the CIC filter has not been considered. The invention adopts a three-section structure as well, but the CIC filter adopts a non-recursive structure, has higher speed and smaller area, and can occupy less hardware resources. And the spectral characteristics of the arcsine filter are utilized to compensate the passband of the CIC filter, so that the signal integrity is ensured. Finally, since the digital downsampling filter of the present invention is a Sigma Delta modulator for audio, with higher stability and linear phase requirements, the third stage filter should still use a FIR filter.

Disclosure of Invention

The present invention is directed to solving the above problems of the prior art. A digital downsampling filter for a Sigma Delta ADC is presented. The technical scheme of the invention is as follows:

a digital downsampling filter for a Sigma Delta ADC, comprising: the method comprises the steps of adopting a first-stage filter F1, a second-stage filter F2 and a third-stage filter F3 which are cascaded in three stages, wherein a data input end is connected with an input end of the first-stage filter F1; the output end of the first-stage filter F1 is connected with the input end of the second-stage filter F2; the output end of the second-stage filter F2 is connected with the output end of the third-stage filter F3; the output end of the third-stage filter F3 is used as the output end of the digital downsampling filter; the digital downsampling filter is used for reducing the output rate of the Sigma Delta modulator, filtering out-of-band quantization noise on the premise of not influencing signals, and the first-stage filter F1 is a non-recursive CIC filter and is used for completing 32 times of downsampling; the second-stage filter F2 is an arcsine filter and is used for completing 2 times of downsampling, compensating passband ripple and increasing stop band attenuation; the third stage filter F3 is a half-band filter for performing 2-fold downsampling and narrowing the filter transition band.

Further, the first stage filter F1 includes: the first fifth-order CIC filter, the second fifth-order CIC filter, the third fifth-order CIC filter, the fourth fifth-order CIC filter and the fifth-order CIC filter are connected with each other, the input of the first fifth-order CIC filter is used as the input of the first-stage filter F1, and the output of the fifth-order CIC filter is used as the output of the first-stage filter F1.

Further, the five-order CIC filter includes five delay modules D1 ₁ -D1 ₅ Two downsampling modules M1 ₁ -M1 ₂ Three coefficient modules A1 ₁ -A1 ₃ Two addition modules A1 ₁ -A1 ₂ An input of the first stage filter F1 is connected with a first delay module D1 ₁ Is input to a first downsampling module M1 ₁ Is input to a first delay module D1 ₁ The output of (a) is connected with a second downsampling module M1 ₂ Is input to a second downsampling module M1 ₂ The output of (a) is connected with a third delay module D1 ₃ Input of (a) and third coefficient module A1 ₃ Is input to a first downsampling module M1 ₁ The output of (a) is connected with the second delay module D1 ₂ Is input to a second delay module D1 ₂ The output of (a) is connected with a fourth delay module D1 ₄ Input of a fourth delay block D1 ₄ The output of (2) is connected with the first coefficient moduleBlock A1 ₁ Is input to a third delay module D1 ₃ The output of (a) is connected with a fifth delay module D1 ₅ Is input to a first addition module S1 ₁ Is connected to the second delay module D1 ₂ Output of (D) and third delay module D1 ₃ The output of (1), a first addition module S1 ₁ The output of (a) is connected with a second coefficient module A1 ₂ Finally, a second adder module S1 ₂ Is connected with the first coefficient module A1 ₁ Output of (D) and first delay block D1 ₁ Output of (a), second coefficient module A1 ₂ Output of (D) and fifth delay block D1 ₅ Output of (a), third coefficient module A1 ₃ An output of (2); second adder module S1 ₂ As an output of a five-order CIC filter.

Further, the second stage filter F2 is a low-pass arcsine filter, and includes: the second-stage downsampling module, the second-stage delay module, the second-stage filter coefficient module and the second-stage filter addition module, wherein the input of the second-stage downsampling module is used as the input of the second-stage filter F2, and the first output is connected with the second-stage delay module D2 _1,1 And second-stage filter coefficient module A2 _1,1 The second output is connected with the second-stage delay module D2 _2,1 And second-stage filter coefficient module A2 _2,1 Second-stage delay module D2 _1,1 The output of (a) is connected with the second-stage delay module D2 _1,2 And second-stage filter coefficient module A2 _1,2 Second-stage filter addition module S2 _1,2 Is connected with the second-stage filter adding module S2 _1,1 The output of (a) and the second-stage filter coefficient module A2 _1,2 An output of (2); the second-stage filter adding module S2 _2,17 The output of (2) is connected with a second-stage filter adding module S2 _1,1 Is input to the computer; the second-stage filter adding module S2 _1,17 As the output of the second stage filter F2; the input ends of the second-stage filter adding modules are positive input ends.

Further, the second stage downsampling module includes a first decimating module M2 ₁ A second extraction module M2 ₂ First delay module D2 ₁ Second, secondThe input of the stage filter F2 is connected with the first decimation module M2 ₁ And a first delay module D2 ₁ Is input to a first delay module D2 ₁ The output of (2) is connected with the second extraction module M2 ₂ Is input to the first decimating module M2 ₁ As the first output of the second stage downsampling module, the second decimation module M2 ₂ As a second output of the second stage downsampling module.

Further, the third stage filter F3 is a low-pass half-band filter, and includes: the third-stage downsampling module, the third-stage delay module and the third-stage filter coefficient module; the input of the third-stage downsampling module is used as the input of a third-stage filter F3, and the first output is connected with a third-stage delay module D3 _1,1 Input of (a) and third stage filter coefficient module A3 _1,1 The second output is connected with the delay module D3 of the third-stage filter _2,1 Is input to the computer; third-stage delay module D3 _1,1 The output of (a) is connected with the second-stage delay module D3 _1,2 And third stage filter coefficient module A3 _1,2 Is input to a third stage filter addition module S3 _1,2 Is connected to the third stage filter adder S2 _1,1 Output of (a) and third stage filter coefficient module A3 _1,2 An output of (2); the third-stage filter delay module D3 _2,1 The output of (a) is connected with a third-stage filter coefficient module A3 _2,1 Is input to the third stage filter coefficient module A3 _2,1 The output of (2) is connected with a third-stage filter adding module S3 _1,1 Is input to the computer; the second-stage filter adding module S3 _1,38 As an output of the third stage FIR filter; the input ends of the third-stage filter adding modules are positive input ends.

Further, the third stage downsampling module includes a first decimating module M3 ₁ A second extraction module M3 ₂ First delay module D3 ₁ The method comprises the steps of carrying out a first treatment on the surface of the The input of the third stage filter F3 is connected with the first extraction module M3 ₁ And a first delay module D3 ₁ Is input to a first delay module D3 ₁ The output of (a) is connected with the second extraction module M3 ₂ Is input to the first decimating module M3 ₁ As a second step downThe first output of the sampling module, the second decimation module M3 ₂ As a second output of the second stage downsampling module.

The first stage filter F1 adopts a CIC filter, and the transfer function is as follows:

where Z represents the result of Z-transforming the CIC filter impulse response, since in the digital signal processing field Z-transforming is required to obtain a discrete signal.

The invention has the advantages and beneficial effects as follows:

compared with the traditional digital downsampling filter structure or more structures adopted in recent years, the invention adopts a three-stage cascade structure, uses a non-recursive CIC filter, specifically compensates passband attenuation, uses an FIR half-band filter in the third stage, and obtains a narrower transition band in frequency spectrum. Due to the adoption of the structure, the invention realizes lower time delay and lower hardware consumption, and has excellent transition band and passband performances while meeting the linear phase.

The second filter F2 of the present invention can compensate for the passband attenuation introduced by the first filter F1, and the third filter F3 provides an excellent transition band spectrum.

In recent years, a recursive filter is mostly adopted as a CIC filter in the digital downsampling filter, and the invention can achieve the effect of higher speed by using the recursive CIC filter. Meanwhile, the problems of instability and big byte data caused by recursion are skillfully avoided, and the hardware consumption is reduced. Meanwhile, the influences of different orders of the half-band filter on the transition band and the stop band are compromised, and the optimal order is used for achieving the best filtering effect.

Drawings

FIG. 1 is a schematic diagram of a digital downsampling filter for a Sigma Delta ADC according to a preferred embodiment of the present invention;

FIG. 2 is a schematic diagram of a single-stage five-order double downsampling CIC filter according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a second stage FIR filter according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a third stage FIR filter according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a conventional indirectly implemented CIC filter for comparison with an embodiment of the present invention;

FIG. 6 is a schematic diagram of the amplitude-frequency response of a first stage CIC filter according to an embodiment of the invention;

FIG. 7 is a schematic diagram of the amplitude-frequency response of a second stage FIR filter according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of the amplitude-frequency response of a third stage FIR filter according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of an amplitude-frequency response of a cascaded first stage CIC filter and a cascaded second stage FIR filter according to an embodiment of the present invention;

FIG. 10 is a graph showing the amplitude-frequency response of a digital downsampling filter according to an embodiment of the invention;

FIG. 11 (a) is a schematic diagram of an FFT performed on the modulator output according to an embodiment of the present invention;

FIG. 11 (b) is a schematic diagram of an FFT performed on the output of a digital down-sampling filter according to an embodiment of the present invention;

fig. 12 is a schematic diagram of output waveforms of each stage of the digital down-sampling filter according to the embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and specifically described below with reference to the drawings in the embodiments of the present invention. The described embodiments are only a few embodiments of the present invention.

The technical scheme for solving the technical problems is as follows:

the embodiment of the invention provides a digital downsampling filter which is applied to a Sigma Delta ADC and comprises a first-stage filter F1, a second-stage filter F2 and a third-stage filter F3 which are sequentially connected. Wherein the data input end of the digital downsampling filter is connected with a first-stage filter F1; the output end of the first-stage filter F1 is connected with the input end of the second-stage filter F2; the output end of the second-stage filter F2 is connected with the output end of the third-stage filter F3; the output end of the third stage filter F3 is used as the output end of the digital downsampling filter. The digital downsampling filter can be used to reduce the output rate of the Sigma Delta modulator and filter out-of-band quantization noise without affecting the signal.

Further, the transfer function that needs to be satisfied by the first stage filter F1 is:

i.e. the downsampling factor is 32 times and the order is five. It can be seen that the transfer function can be implemented by a CIC filter with five-order double downsampling multiple, so that the first-stage CIC filter is formed by cascading five-order double downsampling CIC filters. Wherein the single stage CIC filter transfer function is:

the transfer function illustrates that the resulting single stage CIC filter structure is non-recursive.

The first stage filter F1 includes: a first fifth-order CIC filter, a second fifth-order CIC filter, a third fifth-order CIC filter, a fourth fifth-order CIC filter, and a fifth-order CIC filter, wherein the CIC filters are connected with each other. The input of the first fifth-order CIC filter is taken as the input of the first-stage filter F1, and the output of the fifth-order CIC filter is taken as the output of the first-stage filter F1.

Further, the five-order CIC filter includes five delay modules D1, two downsampling modules M1, three coefficient modules A1, and two adding modules S1. An input of the first stage filter F1 is connected with a first delay module D1 ₁ Is input to a first downsampling module M1 ₁ Is input to the computer. First delay module D1 ₁ The output of (a) is connected with a second downsampling module M1 ₂ Is input to the computer. Second descending miningSample module M1 ₂ The output of (a) is connected with a third delay module D1 ₃ Input of (a) and third coefficient module A1 ₃ Is input to the computer. First downsampling module M1 ₁ The output of (a) is connected with the second delay module D1 ₂ Is input to the computer. Second delay module D1 ₂ The output of (a) is connected with a fourth delay module D1 ₄ Input of a fourth delay block D1 ₄ The output of (a) is connected with a first coefficient module A1 ₁ Is input to the computer. Third delay module D1 ₃ The output of (a) is connected with a fifth delay module D1 ₅ Is input to the computer. First addition module S1 ₁ Is connected to the second delay module D1 ₂ Output of (D) and third delay module D1 ₃ The output of (1), a first addition module S1 ₁ The output of (a) is connected with a second coefficient module A1 ₂ Is input to the computer. Finally, a second adder module S1 ₂ Is connected with the first coefficient module A1 ₁ Output of (D) and first delay block D1 ₁ Output of (a), second coefficient module A1 ₂ Output of (D) and fifth delay block D1 ₅ Output of (a), third coefficient module A1 ₃ Is provided. Second adder module S1 ₂ As an output of a five-order CIC filter.

The second stage filter F2 is a low-pass arcsine filter, and includes: the system comprises a second-stage downsampling module, a second-stage delay module, a second-stage filter coefficient module and a second-stage filter addition module. The input of the second-stage downsampling module is used as the input of a second-stage filter F2, and the first output is connected with a second-stage delay module D2 _1,1 And second-stage filter coefficient module A2 _1,1 The second output is connected with the second-stage delay module D2 _2,1 And second-stage filter coefficient module A2 _2,1 . Second-stage delay module D2 _1,1 The output of (a) is connected with the second-stage delay module D2 _1,2 And second-stage filter coefficient module A2 _1,2 Second-stage filter addition module S2 _1,2 Is connected with the second-stage filter adding module S2 _1,1 The output of (a) and the second-stage filter coefficient module A2 _1,2 Is provided. Because of the specificity of the FIR filter structure, the remaining connections can be derived as described above, and therefore will not be described in detail here. In particular, the firstTwo-stage filter addition module S2 _2,17 The output of (2) is connected with a second-stage filter adding module S2 _1,1 Is input to the computer. The second-stage filter adding module S2 _1,17 As the output of the second stage filter F2. The input ends of the second-stage filter adding modules are positive input ends.

Further, the second stage downsampling module includes a first decimating module M2 ₁ A second extraction module M2 ₂ First delay module D2 ₁ . The input of the second stage filter F2 is connected with the first extraction module M2 ₁ And a first delay module D2 ₁ Is input to a first delay module D2 ₁ The output of (2) is connected with the second extraction module M2 ₂ Is input to the first decimating module M2 ₁ As the first output of the second stage downsampling module, the second decimation module M2 ₂ As a second output of the second stage downsampling module.

The third stage filter F3 is a low-pass half-band filter, and includes: the third-stage downsampling module, the third-stage delay module and the third-stage filter coefficient module. The input of the third-stage downsampling module is used as the input of a third-stage filter F3, and the first output is connected with a third-stage delay module D3 _1,1 Input of (a) and third stage filter coefficient module A3 _1,1 The second output is connected with the delay module D3 of the third-stage filter _2,1 Is input to the computer. Third-stage delay module D3 _1,1 The output of (a) is connected with the second-stage delay module D3 _1,2 And third stage filter coefficient module A3 _1,2 Is input to a third stage filter addition module S3 _1,2 Is connected to the third stage filter adder S2 _1,1 Output of (a) and third stage filter coefficient module A3 _1,2 Is provided. Because of the specificity of the FIR filter structure, the remaining connections can be derived as described above, and therefore will not be described in detail here. In particular, the third stage filter delay module D3 _2,1 The output of (a) is connected with a third-stage filter coefficient module A3 _2,1 Is input to the third stage filter coefficient module A3 _2,1 The output of (2) is connected with a third-stage filter adding module S3 _1,1 Is input to the computer. The second-stage filter adds the modulusBlock S3 _1,38 As an output of the third stage FIR filter. The input ends of the third-stage filter adding modules are positive input ends.

Further, the third stage downsampling module includes a first decimating module M3 ₁ A second extraction module M3 ₂ First delay module D3 ₁ . The input of the third stage filter F3 is connected with the first extraction module M3 ₁ And a first delay module D3 ₁ Is input to a first delay module D3 ₁ The output of (a) is connected with the second extraction module M3 ₂ Is input to the first decimating module M3 ₁ As the first output of the second stage downsampling module, the second decimation module M3 ₂ As a second output of the second stage downsampling module.

Through the above technical solution, the second stage filter F2 can compensate the passband attenuation problem introduced by the first stage filter F1, and the third stage filter F3 provides an excellent transition band spectrum. More specific functions will be described in detail in the detailed description section that follows.

It should be noted that, the Sigma Delta ADC designed below refers to a Sigma Delta analog-to-digital converter including a Sigma Delta modulator and a digital downsampling filter, and the embodiment of the present invention mainly designs the digital downsampling filter.

The structure of a conventional five-order CIC filter that indirectly implements recursion is shown in fig. 5, and its transfer function is:

wherein D is a decimation factor, M is the delay number of the delay module, and 5 represents the CIC order. The recursive CIC filter has the advantages of no need of a multiplier, easiness in hardware implementation and the like. However, recursive CIC filters increase word length and introduce speed limitations.

Therefore, the invention adopts a non-recursion CIC filter, does not need an integral module, has output only associated with input and no feedback loop compared with a recursion structure, has higher stability, and is more suitable for audio and other applications.

Fig. 2 is a schematic diagram of a single-stage five-order two-fold downsampling CIC filter in a non-recursive CIC filter according to an embodiment of the invention. The transfer function of the CIC filter is:

H(Z)＝1+z ^-1 (5+10z ^-2 +z ^-4 )+z ^-2 (10+5z ^-2 )

after cascading, the five-stage five-order CIC filter can achieve the function of the five-stage thirty-two times downsampling CIC filter. The present invention contemplates providing a solution to the speed limitation problem of digital downsampling filters by non-recursively structured CIC filters, optimizing the operating frequency.

As previously described, CIC filters introduce passband attenuation problems. In order to effectively reduce passband attenuation, a cascaded compensation filter approach is required. For the compensation filter, the amplitude-frequency characteristic of the compensation filter has obvious reciprocal relation with the amplitude-frequency characteristic of the CIC filter, and the amplitude-frequency characteristic of the CIC filter of the fifth-order thirty-two times downsampling meets the following conditionThe amplitude-frequency characteristic curve of the FIR filter provided by the invention needs to be satisfied

Fig. 3 shows a low-pass arcsine FIR filter according to an embodiment of the present invention, where the FIR filter can be designed using the equiripple method with fdatool in MATLAB. In the fdatool single-rate mode, the low-pass arcsine filter only performs passband attenuation compensation; in the fdatool multirate mode, the FIR compensation filter can compensate for passband attenuation and can also perform downsampling operations on the signal. The arcsine low-pass filter structure has the advantages that the stop band attenuation is good, and a down-sampling function can be added, so that the down-sampling number of the front-stage CIC filter is effectively reduced. However, if the transition band width is reduced and the passband compensation effect is better, the order of the arcsine filter needs to be increased, and the total amount of the filter coefficients increases due to the increase of the order, so that more hardware resources are required for storing and operating the filter coefficients.

Fig. 4 shows a low-pass half-band FIR filter according to an embodiment of the present invention, which can implement the function of reducing the width of the transition band described above. The half-band filter is a special linear phase low-pass filter, the passband characteristic of which is flat and symmetrical about 1/2 Nyquist sampling rate, and the transition band is convenient to control. And meanwhile, half of the filter coefficients are 0, so that less hardware resources are consumed. The digital filter of the type can reduce the area and the power consumption of the whole chip, is not only commonly used in a digital downsampling filter of a Sigma Delta ADC, but also has wide application in other digital signal processing fields.

In the structure of the three-stage cascade digital downsampling filter, selecting the order of the second-stage FIR filter and the third-stage FIR filter is a very critical problem, and can influence the filtering effect and subsequent hardware resource consumption. When the order of the second-stage FIR low-pass arcsine filter is too low, the stop band and transition band performance of the whole digital downsampling filter can be affected; when the order is too high, the performance change with the increase of the order is no longer obvious and takes up too much resources. The transition band can be narrowed by a third stage FIR low pass half band filter and provides good stop band attenuation, but as the half band filter order increases, the stop band attenuation increases but the transition band instead widens. The order for the third stage FIR filter should also be chosen to be a compromise between the actual model and the application.

The present invention therefore proposes a digital decimation filter for a Sigma Delta ADC. Fig. 1 is a schematic diagram of a digital downsampling filter according to an embodiment of the invention, which is applied to a Sigma Delta ADC and includes a first stage filter F1, a second stage filter F2, and a third stage filter F3. The embodiment of the invention is suitable for a Sigma Delta ADC applied to the audio frequency field, and the application principle of the digital downsampling filter of the embodiment of the invention is described in detail below by way of example.

Specifically, the first-stage filter F1 includes five single-stage five-order double downsampling CIC filters, the second-stage filter F2 is a thirty-second-order low-pass arcsine filter, and the third-stage filter F3 is a seventy-fourth-order low-pass half-band filter. The data input end of the digital downsampling filter is connected with a first-stage filter F1; the output end of the first-stage filter F1 is connected with the input end of the second-stage filter F2; the output end of the second-stage filter F2 is connected with the input end of the third-stage filter F3; the output end of the third stage filter F3 is used as the output end of the digital downsampling filter. Through the first stage filter F1, less resources are consumed, 32 times of downsampling is performed on the output signal of the modulator, but the stopband attenuation is smaller, the transition band is wider, and the passband ripple is larger. The second stage filter F2 is able to compensate for the passband roll-off problem of the filter F1 and provide excellent stopband attenuation and achieve double downsampling. The third stage filter F3 is capable of controlling the transition band, achieving a narrower transition band and providing excellent stop band attenuation, and achieving double down-sampling. The digital downsampling filter provided by the embodiment of the invention can filter out-of-band noise and realize 128 times downsampling.

Further, in this embodiment, the first stage filter F1 has an order of 5 and a stage number of 5; fpass1 of the second-stage filter F2 is 20kHz, and Fston 1 is 38.24kHz; apass1 of the second-stage filter F2 is 1.079dB, and Astop1 is-80 dB; fpass2 of the third-stage filter F3 is 18kHz, and Fston 2 is 22kHz; apass2 of the third stage filter F3 is 0.01dB and Astop2 is-67 dB.

Specifically, the amplitude-frequency response of the first-stage filter F1 is shown in fig. 6, the amplitude-frequency response of the second-stage filter F2 is shown in fig. 7, and the amplitude-frequency response of the third-stage filter F3 is shown in fig. 8. The amplitude-frequency response of the cascade of filters F1 and F2 can be obtained with the aid of software and tools as shown in fig. 9. It can be seen that the low-pass arcsine filter provided by the embodiment of the invention can well compensate the passband roll-off problem introduced by the CIC filter, and achieves a good filtering effect.

As shown in fig. 10, the amplitude-frequency characteristic of the digital downsampling filter provided by the embodiment of the invention may be shown, where Apass of the digital downsampling filter is 0.1dB, and astop is-88 dB. The sampling frequency of the modulator provided by the embodiment of the invention is 5.12MHz, taking a sine wave of 2421.875Hz as an input signal as an example, and obtaining the result shown in fig. 11 (a) after Fast Fourier Transform (FFT) is performed on the output of the modulator. The modulator can reach 106.6dB signal-to-noise and distortion ratio (SNDR) and 17.42bit effective number of bits (ENOB). After passing through the digital down-sampling filter provided by the embodiment of the invention, the output signal is subjected to FFT to obtain the result shown in FIG. 11 (b), namely, SNDR of 107.1dB and ENOB of 17.5bit are achieved.

Further, the outputs of the stages of the digital downsampling filter are shown in fig. 12, and it can be seen that the output code stream of the modulator is restored to a sine wave-like signal by the digital downsampling filter, and the downsampling is completed by 128 times. The 128-time downsampling means that every 128 data are taken and stored, and the rate of the output data of the modulator can be reduced.

In summary, the digital downsampling filter for Sigma Delta ADC provided by the present invention has at least the following advantages:

1) The digital downsampling filter for the Sigma Delta ADC provided by the embodiment of the invention can show smaller passband ripple, narrower transition band, larger stopband attenuation and higher filtering performance.

2) Compared with the traditional recursive CIC filter structure, the embodiment of the invention designs a non-recursive five-stage CIC filter structure corresponding to the problems of speed limitation and hardware consumption, and meanwhile, a feedback loop is deleted, so that the system is more stable.

3) Compared with the traditional three-stage cascade structure, the method has the advantages that the influence of the order changes of the second-stage FIR filter and the third-stage FIR filter on the amplitude-frequency characteristic is analyzed, and the better order is selected.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.

The above examples should be understood as illustrative only and not limiting the scope of the invention. Various changes and modifications to the present invention may be made by one skilled in the art after reading the teachings herein, and such equivalent changes and modifications are intended to fall within the scope of the invention as defined in the appended claims.

Claims (8)

1. A digital downsampling filter for a Sigma Delta ADC, comprising: the method comprises the steps of adopting a first-stage filter F1, a second-stage filter F2 and a third-stage filter F3 which are cascaded in three stages, wherein a data input end is connected with an input end of the first-stage filter F1; the output end of the first-stage filter F1 is connected with the input end of the second-stage filter F2; the output end of the second-stage filter F2 is connected with the output end of the third-stage filter F3; the output end of the third-stage filter F3 is used as the output end of the digital downsampling filter; the digital downsampling filter is used for reducing the output rate of the Sigma Delta modulator, filtering out-of-band quantization noise on the premise of not influencing signals, and the first-stage filter F1 is a non-recursive CIC filter and is used for realizing 32 times downsampling; the second-stage filter F2 is an arcsine filter and is used for realizing 2 times of downsampling, compensating passband ripple and increasing stop band attenuation; the third stage filter F3 is a half-band filter for implementing 2-fold downsampling and narrowing the filter transition band.

2. A digital downsampling filter for a Sigma Delta ADC according to claim 1, wherein said first stage filter F1 comprises: the first fifth-order CIC filter, the second fifth-order CIC filter, the third fifth-order CIC filter, the fourth fifth-order CIC filter and the fifth-order CIC filter are connected with each other, the input of the first fifth-order CIC filter is used as the input of the first-stage filter F1, and the output of the fifth-order CIC filter is used as the output of the first-stage filter F1.

3. The digital downsampling filter for a Sigma Delta ADC of claim 2, wherein said five-order CIC filter includes five delay blocks D1 therein ₁ -D1 ₅ Two downsampling modules M1 ₁ -M1 ₂ Three coefficient modules A1 ₁ -A1 ₃ Two addition modules A1 ₁ -A1 ₂ An input of the first stage filter F1 is connected with a first delay module D1 ₁ Is input to a first downsampling module M1 ₁ Is input to a first delay module D1 ₁ The output of (a) is connected with a second downsampling module M1 ₂ Is input to a second downsampling module M1 ₂ The output of (a) is connected with a third delay module D1 ₃ Input of (a) and third coefficient module A1 ₃ Is input to a first downsampling module M1 ₁ The output of (a) is connected with the second delay module D1 ₂ Is input to a second delay module D1 ₂ The output of (a) is connected with a fourth delay module D1 ₄ Input of a fourth delay block D1 ₄ The output of (a) is connected with a first coefficient module A1 ₁ Is input to a third delay module D1 ₃ The output of (a) is connected with a fifth delay module D1 ₅ Is input to a first addition module S1 ₁ Is connected to the second delay module D1 ₂ Output of (D) and third delay module D1 ₃ The output of (1), a first addition module S1 ₁ The output of (a) is connected with a second coefficient module A1 ₂ Finally, a second adder module S1 ₂ Is connected with the first coefficient module A1 ₁ Output of (D) and first delay block D1 ₁ Output of (a), second coefficient module A1 ₂ Output of (D) and fifth delay block D1 ₅ Output of (a), third coefficient module A1 ₃ An output of (2); second adder module S1 ₂ As an output of a five-order CIC filter.

4. A digital downsampling filter for a Sigma Delta ADC as set forth in claim 1, wherein said second stage filter F2 is a low pass inverseA sine filter comprising: the second-stage downsampling module, the second-stage delay module, the second-stage filter coefficient module and the second-stage filter addition module, wherein the input of the second-stage downsampling module is used as the input of the second-stage filter F2, and the first output is connected with the second-stage delay module D2 _1,1 And second-stage filter coefficient module A2 _1,1 The second output is connected with the second-stage delay module D2 _2,1 And second-stage filter coefficient module A2 _2,1 Second-stage delay module D2 _1,1 The output of (a) is connected with the second-stage delay module D2 _1,2 And second-stage filter coefficient module A2 _1,2 Second-stage filter addition module S2 _1,2 Is connected with the second-stage filter adding module S2 _1,1 The output of (a) and the second-stage filter coefficient module A2 _1,2 An output of (2); the second-stage filter adding module S2 _2,17 The output of (2) is connected with a second-stage filter adding module S2 _1,1 Is input to the computer; the second-stage filter adding module S2 _1,17 As the output of the second stage filter F2; the input ends of the second-stage filter adding modules are positive input ends.

5. The digital downsampling filter for a Sigma Delta ADC of claim 4, wherein said second stage downsampling module comprises a first decimating module M2 ₁ A second extraction module M2 ₂ First delay module D2 ₁ The input of the second stage filter F2 is connected with the first extraction module M2 ₁ And a first delay module D2 ₁ Is input to a first delay module D2 ₁ The output of (2) is connected with the second extraction module M2 ₂ Is input to the first decimating module M2 ₁ As the first output of the second stage downsampling module, the second decimation module M2 ₂ As a second output of the second stage downsampling module.

6. A digital downsampling filter for a Sigma Delta ADC according to claim 1, wherein said third stage filter F3 is a low pass half-band filter comprising: third-stage downsampling moduleThe third-stage delay module and the third-stage filter coefficient module; the input of the third-stage downsampling module is used as the input of a third-stage filter F3, and the first output is connected with a third-stage delay module D3 _1,1 Input of (a) and third stage filter coefficient module A3 _1,1 The second output is connected with the delay module D3 of the third-stage filter _2,1 Is input to the computer; third-stage delay module D3 _1,1 The output of (a) is connected with the second-stage delay module D3 _1,2 And third stage filter coefficient module A3 _1,2 Is input to a third stage filter addition module S3 _1,2 Is connected to the third stage filter adder S2 _1,1 Output of (a) and third stage filter coefficient module A3 _1,2 An output of (2); the third-stage filter delay module D3 _2,1 The output of (a) is connected with a third-stage filter coefficient module A3 _2,1 Is input to the third stage filter coefficient module A3 _2,1 The output of (2) is connected with a third-stage filter adding module S3 _1,1 Is input to the computer; the second-stage filter adding module S3 _1,38 As an output of the third stage FIR filter; the input ends of the third-stage filter adding modules are positive input ends.

7. A digital downsampling filter for a Sigma Delta ADC as recited in claim 1, wherein said third stage downsampling module comprises a first decimating module M3 ₁ A second extraction module M3 ₂ First delay module D3 ₁ The method comprises the steps of carrying out a first treatment on the surface of the The input of the third stage filter F3 is connected with the first extraction module M3 ₁ And a first delay module D3 ₁ Is input to a first delay module D3 ₁ The output of (a) is connected with the second extraction module M3 ₂ Is input to the first decimating module M3 ₁ As the first output of the second stage downsampling module, the second decimation module M3 ₂ As a second output of the second stage downsampling module.

8. A digital down-sampling filter for Sigma Delta ADC as defined in claim 1, wherein said first stage filter F1 employs CIC filters with transfer functions of:

where Z represents the result of Z-transforming the CIC filter impulse response, since in the digital signal processing field Z-transforming is required to obtain a discrete signal.