CN115878522B - Data transmission device and system - Google Patents
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Abstract
The present disclosure relates to a data transmission device and system. The device comprises: the external device comprises a memory bus and a peripheral bus, wherein the memory bus is used for sending read-write requests of a direct memory access controller and a central processing unit to a memory block to the memory block, and the peripheral bus is used for sending read-write requests of the direct memory access controller and the central processing unit to external devices to the external devices. According to the method and the device, the memory bus and the peripheral bus are arranged, the read-write request of the direct memory access controller and the central processing unit to the memory block is sent to the memory block through the memory bus, the read-write request of the direct memory access controller and the central processing unit to the external device is sent to the external device through the peripheral bus, when the access requests to the external device and the memory block are initiated simultaneously, the access requests can reach the target position without mutual interference through the memory bus and the peripheral bus respectively, the probability of collision is reduced, and the overall processing speed of the system is improved.
Description
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to a data transmission device and system.
Background
With the continuous development of computer technology, the amount of data to be processed in a short time is continuously increased, and meanwhile, the requirement of people on data transmission speed is continuously increased. Direct memory access (Direct Memory Access, DMA) is a transfer mechanism for data transfer between an external device and memory, enabling data transfer without going through a central processing unit (Central Processing Unit, CPU). However, in the prior art, only an access request for one of the external device or the memory can be processed at the same time, but the access requests for the external device and the memory cannot be processed at the same time, and if the access requests for the external device and the memory are initiated at the same time, a conflict can be generated, so that the overall processing speed of the system is reduced.
Disclosure of Invention
In order to solve the technical problems, the present disclosure provides a data transmission device and a system.
A first aspect of an embodiment of the present disclosure provides a data transmission apparatus, including:
the external device comprises a memory bus and a peripheral bus, wherein the memory bus is used for sending read-write requests of a direct memory access controller and a central processing unit to a memory block to the memory block, and the peripheral bus is used for sending read-write requests of the direct memory access controller and the central processing unit to external devices to the external devices.
In some embodiments of the present disclosure, the memory bus includes:
the first interface is connected with the direct memory access controller, and the first memory address decoding module is used for decoding a first read-write request of the memory block by the direct memory access controller and extracting the address of the memory block from the decoded first read-write request;
the second memory address decoding module is used for decoding a second read-write request of the memory block from the central processing unit and extracting the address of the memory block from the decoded second read-write request.
In some embodiments of the present disclosure, the memory bus further includes:
and the memory arbitration module is connected with the first memory address decoding module and the second memory address decoding module and is used for arbitrating the received first read-write request and the received second read-write request, and sending the first read-write request and the second read-write request to the memory blocks corresponding to the memory arbitration module according to the priorities of the first read-write request and the second read-write request, wherein the memory arbitration module and the memory blocks are in one-to-one correspondence.
In some embodiments of the disclosure, the memory arbitration module includes:
a first arbitration unit, configured to determine, when a received read-write request is the same as an initiator of a read-write request being processed, a priority of the received read-write request as a highest priority;
and the second arbitration unit is used for determining the priority of the received read-write request based on a polling scheduling algorithm when the received read-write request is different from the initiator of the read-write request which is being processed.
In some embodiments of the present disclosure, the peripheral bus includes:
the first switching bridge is connected with the direct storage access controller and is used for converting the structure of the received third read-write request of the direct storage access controller to the external equipment into a first preset structure;
the first peripheral address decoding module is used for decoding the third read-write request after the structure conversion and extracting the address of the external equipment from the decoded third read-write request;
the second switching bridge is connected with the central processing unit and is used for converting the structure of the received fourth read-write request of the central processing unit to the external equipment into a second preset structure;
and the second external address decoding module is used for decoding the fourth read-write request after the structure conversion and extracting the address of the external equipment from the decoded fourth read-write request.
In some embodiments of the present disclosure, the peripheral bus further comprises:
the peripheral arbitration module is connected with the first peripheral address decoding module and the second peripheral address decoding module and used for arbitrating the received third read-write request and the received fourth read-write request, and sending the third read-write request and the fourth read-write request to external equipment corresponding to the peripheral arbitration module according to the priorities of the third read-write request and the fourth read-write request, wherein the peripheral arbitration module is in one-to-one correspondence with the external equipment;
and the synchronous processing module is connected with the external equipment and is used for carrying out clock synchronous processing on the data returned by the external equipment and sending the data to the direct memory access controller.
In some embodiments of the present disclosure, the synchronization processing module includes:
a matching unit, configured to determine an address of a target channel corresponding to an address of an external device included in data returned by the external device, based on a mapping relationship between the address of the external device and an address of a channel in the direct memory access controller;
and the first sending unit is used for sending the data returned by the external equipment to the direct memory access controller through the target channel according to the address of the target channel.
In some embodiments of the present disclosure, the direct memory access controller includes:
the third interface is connected with the central processing unit and the register is used for storing configuration parameters sent by the central processing unit, and the configuration parameters are used for configuring channels connected with the register;
the channel is used for sending a read-write request to a preset arbitration module and receiving data returned by the preset arbitration module;
the preset arbitration module is used for arbitrating the read-write request sent by the channel and the data returned by the memory bus and the peripheral bus, sending the read-write request to the memory bus or the peripheral bus according to the order of priority from high to low, and sending the data to the channel.
In some embodiments of the present disclosure, the channel comprises:
the inquiring unit is used for inquiring whether a read-write request corresponding to the channel exists or not based on the configuration parameters;
and the second sending unit is used for sending the read-write request to the preset arbitration module when the read-write request corresponding to the channel is inquired.
In some embodiments of the present disclosure, the direct memory access controller further includes:
and the multiplexing module is used for forwarding the received read-write requests sent by the preset arbitration module to the external equipment and the memory block through the peripheral bus and the memory bus, and forwarding a plurality of groups of data returned by the external equipment and the memory block to the preset arbitration module.
A second aspect of the embodiments of the present disclosure provides a data transmission system, including a data transmission device, a direct memory access controller, a central processing unit, a memory block, and an external device;
the central processing unit is connected with the direct memory access controller, the memory bus is connected with the memory block, the direct memory access controller and the central processing unit, and the peripheral bus is connected with the external equipment, the direct memory access controller and the central processing unit.
Compared with the prior art, the technical scheme provided by the embodiment of the disclosure has the following advantages:
in the data transmission device and the data transmission system provided by the embodiment of the disclosure, through setting the memory bus and the peripheral bus, the read-write request of the direct memory access controller and the central processing unit to the memory block is sent to the memory block through the memory bus, the read-write request of the direct memory access controller and the central processing unit to the external device is sent to the external device through the peripheral bus, when the access requests to the external device and the memory block are initiated simultaneously, the access requests can reach the target positions without mutual interference through the memory bus and the peripheral bus respectively, the probability of collision is reduced, and the overall processing speed of the system is improved.
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The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.
In order to more clearly illustrate the embodiments of the present disclosure or the solutions in the prior art, the drawings that are required for the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is a schematic structural diagram of a data transmission device according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a memory bus according to an embodiment of the disclosure;
FIG. 3 is a schematic diagram of a peripheral bus according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a direct memory access controller according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a data transmission system according to an embodiment of the present disclosure.
Detailed Description
In order that the above objects, features and advantages of the present disclosure may be more clearly understood, a further description of aspects of the present disclosure will be provided below. It should be noted that, without conflict, the embodiments of the present disclosure and features in the embodiments may be combined with each other.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced otherwise than as described herein; it will be apparent that the embodiments in the specification are only some, but not all, embodiments of the disclosure.
Fig. 1 is a schematic structural diagram of a data transmission device according to an embodiment of the present disclosure.
As shown in fig. 1, the data transmission device 100 provided in the embodiment of the disclosure includes a memory bus 110 and a peripheral bus 120, where the memory bus 110 is respectively connected to a direct storage access controller 130, a central processing unit 140, and a memory block 150, and the peripheral bus 120 is respectively connected to the direct storage access controller 130, the central processing unit 140, and an external device 160.
In the embodiment of the present disclosure, the memory bus 110 is used to send the read/write request of the direct storage access controller 130 and the central processing unit 140 to the memory block 150, and the peripheral bus 120 is used to send the read/write request of the direct storage access controller 130 and the central processing unit 140 to the external device 160.
A bus in embodiments of the present disclosure may be understood as a common communication backbone that carries the various functional components within the device, a memory bus may be understood as a backbone that communicates between the direct memory access controller and the central processor and the memory block, and a peripheral bus may be understood as a backbone that communicates between the direct memory access controller and the central processor and the external device.
The direct memory access controller (Direct memory access controller, DMAC) in the embodiments of the present disclosure may be understood as a control module when accessing a memory according to a direct memory access rule, and the central processing unit (Central Process Unit, CPU) may be understood as a core component that controls a computer device to automatically complete instruction fetching and instruction task execution, where both the direct memory access controller and the central processing unit may serve as a host to actively initiate a read/write request to a memory block and an external device.
A memory block in the embodiments of the present disclosure may be understood as a common storage area in a memory pool, and multiple memory blocks may exist at the same time. The external device may be understood as an external device capable of performing input and output operations, such as an external memory, a keyboard, and the like.
A read-write request in an embodiment of the present disclosure may be understood as a request for implementing a function of copying data from one address space to another address space.
In the embodiment of the disclosure, the read-write request of the direct memory access controller and the central processing unit to the memory block is sent to the memory block through the memory bus by setting the memory bus and the peripheral bus, the read-write request of the direct memory access controller and the central processing unit to the external device is sent to the external device through the peripheral bus, and when the access requests for the external device and the memory block are simultaneously initiated, the access requests can reach the target position without mutual interference through the memory bus and the peripheral bus respectively, thereby reducing the consumption of arbitration logic, reducing the probability of collision and improving the overall processing speed of the system.
Fig. 2 is a schematic diagram of a memory bus according to an embodiment of the disclosure.
As shown in fig. 2, the memory bus 200 provided in the embodiment of the disclosure includes a first interface 210, a first memory address decoding module 220, a second interface 230, a second memory address decoding module 240, and a memory arbitration module 250, wherein the memory arbitration module 250 includes a first arbitration unit 251 and a second arbitration unit 252, and the memory arbitration modules 250-1 and 250-2 are respectively connected to different memory blocks.
The first interface 210 in the embodiment of the present disclosure is connected to the direct storage access controller, and is configured to receive a first read-write request from the direct storage access controller to the memory block.
The second interface 230 in the embodiment of the present disclosure is connected to the central processing unit, and is configured to receive a second read/write request from the central processing unit to the memory block.
In an exemplary implementation of the disclosed embodiment, the second interface 230 may be connected to the central processor through a CPU memory channel and an advanced high-performance bus (AdvancedHigh Performance Bus, AHB), that is, the second interface 230 is connected to the CPU memory channel, the CPU memory channel is connected to the AHB bus, and the AHB bus is connected to the central processor, where the second interface 230 may receive a second read-write request sent by the central processor through the AHB bus and the CPU memory channel.
In an exemplary implementation manner of the embodiments of the present disclosure, according to different hosts that initiate read-write requests, the memory bus 200 may further set different interfaces, receive read-write requests of different hosts for a memory block, and by way of example, the memory bus may set up 8 interfaces at most.
The first memory address decoding module 220 in the embodiment of the present disclosure is connected to the first interface 210, and is configured to, after receiving a first read-write request sent by the direct memory access controller through the first interface 210, decode the first read-write request, and extract an address of a memory block from the decoded request, so as to facilitate addressing of a corresponding memory block by the extracted address.
The second memory address decoding module 240 in the embodiment of the present disclosure is connected to the second interface 230, and is configured to, after receiving a second read/write request sent by the central processor through the second interface 230, decode the second read/write request, and extract an address of a memory block from the decoded request, so as to facilitate addressing of a corresponding memory block by the extracted address.
The memory arbitration module 250 in the embodiment of the present disclosure is connected to the first memory address decoding module 220, the second memory address decoding module 240, and a memory block, and is configured to arbitrate priorities of the first read/write request and the second read/write request when the direct memory access controller and the central processing unit simultaneously receive the first read/write request and the second read/write request for the same memory block, send the read/write request with the highest priority to the memory block, and wait for the memory block to process and send the next read/write request with the highest priority to the memory block.
The memory arbitration module 250 in the embodiment of the disclosure includes a first arbitration unit 251 and a second arbitration unit 252. The memory arbitration module 250 may adopt a modified polling algorithm, when the received read-write request is a read-write request with repeated access, that is, when the newly received read-write request is the same as the initiator of the read-write request being processed, the first arbitration unit 251 determines the priority of the newly received read-write request as the highest priority, and sends the read-write request with the highest priority to the memory block after the processing of the memory block is completed, and when the received read-write request is not a read-write request with repeated access, that is, when the newly received read-write request is different from the initiator of the read-write request being processed, the second arbitration unit 252 determines the priority of the newly received read-write request based on the polling scheduling algorithm, specifically, after the memory block processes the read-write request, the request initiator corresponding to the processed read-write request may be adjusted to the lowest priority, and the priority of the other initiators is improved, so as to ensure the balanced allocation of processing resources.
In an exemplary implementation of the disclosed embodiments, the memory arbitration module 250 may implement asymmetric reading and writing of memory blocks based on a matrix type non-pair Ji Nacun access algorithm.
According to the embodiment of the disclosure, the first interface and the first memory address decoding module connected with the direct memory access controller, the second interface and the second memory address decoding module connected with the central processing unit and the memory arbitration module comprising the first arbitration unit and the second arbitration unit are arranged, after the addresses of the memory blocks which are accessed in a target manner are obtained through analysis by the first memory address decoding module and the second memory address decoding module, the read-write request is sent to the arbiter corresponding to the memory block, so that access conflict among the read-write requests for different memory blocks is avoided, the overall processing speed of the system is further improved, meanwhile, the read-write requests from the same initiator can be processed at one time, the read-write requests from different initiators can be distributed with processing resources in a balanced manner, and the balance of the integrity of task processing and the time length of waiting for response is realized.
Fig. 3 is a schematic structural diagram of a peripheral bus according to an embodiment of the present disclosure.
As shown in fig. 3, the peripheral bus 300 provided in the embodiment of the present disclosure includes a first bridge 310, a first peripheral address decoding module 320, a second bridge 330, a second peripheral address decoding module 340, a peripheral arbitration module 350, and a synchronization processing module 360. The synchronization processing module 360 includes a matching unit 361 and a first transmitting unit 362, and is connected to the external devices 370-1 and 370-2, and the peripheral arbitration modules 350-1 and 350-2 are connected to the external devices 370-1 and 370-2, respectively.
The first bridge 310 in the embodiment of the present disclosure is connected to the direct storage access controller, and is configured to receive a third read-write request from the direct storage access controller to the external device, and convert the structure of the third read-write request into a first preset structure, so as to facilitate identifying and extracting information from the third read-write request of the first preset structure.
The second switching bridge 330 in the embodiment of the present disclosure is connected to the central processing unit, and is configured to receive a fourth read-write request from the central processing unit to the external device, and convert the structure of the fourth read-write request into a second preset structure, so as to identify and extract information from the fourth read-write request of the second preset structure, where the second preset structure may be the same as the first preset structure, and is a peripheral bus (Advanced Peripheral Bus, APB) structure, or may be different from the first preset structure, and is not limited herein.
In an exemplary implementation manner of the disclosed embodiment, the second bridge 330 may be connected to the central processor through an AHB bus, that is, the second bridge 330 is connected to the AHB bus, and the AHB bus is connected to the central processor, where the second bridge 330 may receive a fourth read/write request sent by the central processor through the AHB bus.
In an exemplary implementation of the disclosed embodiment, the first bridge 310 and the second bridge 330 may use a handshake structure to stably send the third read-write request and the fourth read-write request to the first peripheral address decoding module 320 and the second peripheral address decoding module 340.
In an exemplary implementation of the embodiments of the present disclosure, the peripheral bus 300 may further be configured with different interfaces according to different hosts that initiate the read-write request, so as to receive the read-write request from different hosts to the external device.
The first peripheral address decoding module 320 in the embodiment of the present disclosure is connected to the first bridge 310, and is configured to decode the third read-write request after receiving the structure conversion sent by the first bridge 310, and extract the address of the external device from the decoded third read-write request, so as to facilitate the subsequent addressing of the corresponding external device by the extracted address.
The second external address decoding module 340 in the embodiment of the present disclosure is connected to the second transit bridge 330, and is configured to decode the fourth read-write request after receiving the structure conversion sent by the second transit bridge 330, and extract the address of the external device from the decoded fourth read-write request, so as to facilitate the subsequent addressing of the corresponding external device by the extracted address.
The peripheral arbitration module 350 in the embodiment of the present disclosure is connected to the first peripheral address decoding module 320, the second peripheral address decoding module 340 and one external device 370, and is configured to, when receiving a third read-write request and a fourth read-write request of the same external device 370 from the direct memory access controller and the central processing unit at the same time, arbitrate priorities of the third read-write request and the fourth read-write request, send a read-write request with the highest priority to the external device 370, and wait for the external device 370 to process and send a next read-write request with the highest priority to the external device 370.
In one exemplary implementation of the disclosed embodiments, the peripheral arbitration module 350 may set the fourth read-write request from the central processor to have the highest priority, and the other read-write requests may determine the respective priorities based on a round robin scheduling algorithm.
The synchronization processing module 360 in the embodiment of the present disclosure is connected to each external device, and is configured to perform clock synchronization processing on data returned after the external device receives the read/write request, and send the data subjected to the clock synchronization processing to the direct memory access controller.
The synchronization processing module 360 in the embodiment of the present disclosure includes a matching unit 361 and a first sending unit 362, where the matching unit 361 is configured to match data returned by an external device with a channel in a direct storage access controller, specifically, may select, according to a peripheral address sent by a pre-integrated direct storage access controller, data corresponding to the peripheral address from all received data returned by the external device, and determine, according to a mapping relationship between an address of the external device and an address of the channel, an address of a target channel that is matched with an address of the external device included in the data returned by the external device; the first sending unit 362 is configured to send, after determining an address of an external device included in data returned by the external device and a corresponding address of a target channel, the data returned by the external device to the direct memory access controller through the target channel, that is, send the data returned by the external device to the target channel according to the address of the target channel.
According to the embodiment of the disclosure, through setting the first transfer bridge and the first peripheral address decoding module which are connected with the direct memory access controller, the second transfer bridge and the second peripheral address decoding module which are connected with the central processing unit, the peripheral arbitration module and the synchronous processing module comprising the matching unit and the first sending unit, the read-write request can be subjected to structural conversion through the first transfer bridge and the second transfer bridge, after the address of the external device is obtained through extraction of the first peripheral address decoding module and the second peripheral address decoding module, the read-write request is sent to the arbiter corresponding to the external device for arbitration, so that access conflicts among read-write requests of different external devices are avoided, the overall processing speed of the system is further improved, and meanwhile, the synchronous processing module also enables the communication limited degree between the external device and channels in the direct memory access controller to be smaller, and the flexible degree of communication is improved.
Fig. 4 is a schematic structural diagram of a direct memory access controller according to an embodiment of the present disclosure.
As shown in fig. 4, the direct memory access controller 400 provided in the embodiment of the present disclosure includes a third interface 410, a register 420, a channel 430, a preset arbitration module 440, and a multiplexing module 450. The channel 430 includes a query unit 431 and a second transmitting unit 432, and the channels 430-1 and 430-2 are two existing data transmission channels.
The third interface 410 in the embodiment of the present disclosure is connected to the register 420, and is configured to receive the configuration parameters sent by the central processing unit.
In an exemplary implementation of the disclosed embodiment, the third interface 410 may be connected to the central processor through an AHB bus, that is, the third interface 410 is connected to the AHB bus, and the AHB bus is connected to the central processor, where the third interface 410 may receive the configuration parameters sent by the central processor through the AHB bus.
The register 420 in the embodiment of the present disclosure is connected to the channel 430, and is configured to store configuration parameters after receiving, through the third interface 410, configuration parameters sent by the cpu for configuring the channel, where the configuration parameters may include, for example, a channel address, a priority, a data transmission direction, for example, whether an external device is to a memory block or a memory block is to an external device, and may further include format parameters for transmitting data, for example, whether a data width, an address is an increment address, a cycle mode, a data transmission amount, and the like, which are not limited herein.
The channel 430 in the embodiment of the disclosure is configured to send a read-write request to a preset arbitration module, and receive data returned by the preset arbitration module, where the channel 430 includes a query unit 431 and a second sending unit 432, where the query unit 431 is configured to query, based on a configuration parameter stored in a register, whether a read-write request corresponding to the channel currently exists, specifically, whether a read-write request corresponding to an address of the channel exists or not may be queried based on the configuration parameter stored in the register, and the second sending unit 432 is configured to send the read-write request to the preset arbitration module when the read-write request corresponding to the channel is queried.
The preset arbitration module 440 in the embodiment of the present disclosure is configured to arbitrate a read/write request sent through a channel, send the read/write request to a memory bus or a peripheral bus corresponding to the read/write request according to a priority order from high to low, and arbitrate data returned by the memory bus and the peripheral bus, and send the returned data to a channel corresponding to an address of the channel included in the data according to the priority order from high to low.
The multiplexing module 450 in the embodiment of the present disclosure can combine a plurality of signals, transmit the signals on a physical channel, and is configured to combine a plurality of received read-write requests sent by the preset arbitration module 440, send the read-write requests to a peripheral bus and a memory bus, and forward the read-write requests to corresponding peripheral devices and memory blocks through the peripheral bus and the memory bus, and further, is configured to combine a plurality of groups of data returned by the peripheral devices and the memory blocks, and forward the data to the preset arbitration module 440.
In an exemplary implementation manner of the embodiment of the present disclosure, the direct storage access controller may include the third interface, the register, the channel, the preset arbitration module, and the multiplexing module, where the channel may be a plurality of independent channels, and by way of example, the direct storage access controller may include at most 8 independent channels; the interface for communication between the peripheral bus and the multiplexing module and the interface for communication between the memory bus and the multiplexing module can also comprise a switching bridge which is used for converting the structure of the read-write request and the data, so that the communication between the peripheral bus and the multiplexing module is convenient, for example, the format of the read-write request sent to the peripheral bus is converted into an APB structure.
In an exemplary implementation of the disclosed embodiment, the specific operation manner of the direct storage access controller may be: in the initial stage, the central processing unit configures the direct memory access controller through the third interface, configures mutually independent configuration parameters for each channel, after the configuration is completed, the direct memory access controller starts to operate, the query processing unit of the channel queries the read-write request of the corresponding external device or memory block according to the configuration parameters, when the read-write request comes, the read-write request is sent to the preset arbitration module and waits for response, after the channel occupation is determined, the memory block and the external device are respectively operated through the memory bus and the peripheral bus, the process of data migration is completed, the channel is released, and the next read-write request is waited.
According to the embodiment of the disclosure, the third interface connected with the central processing unit is arranged, the configuration parameters which are sent by the central processing unit and used for configuring the channels are received, the register is arranged for storing the configuration parameters, after the channel configuration is completed, the read-write requests aiming at different memory blocks or external devices are sent to the preset arbitration module based on the channels comprising the query unit and the second sending unit, the priority of the read-write requests and the data is arbitrated by the preset arbitration module, the read-write requests are sent to the peripheral bus or the memory bus through the multiplexing module, the returned data is sent to the corresponding channels, flexible configuration can be carried out on the channels, meanwhile, the read-write requests of a plurality of memory blocks or the external devices are processed, and the overall processing speed of the system is further improved.
Fig. 5 is a schematic structural diagram of a data transmission system according to an embodiment of the present disclosure.
As shown in fig. 5, the data transmission system 500 includes a data transmission device 510, a direct memory access controller 520, a central processing unit 530, a memory block 540, and an external device 550.
In the embodiment of the disclosure, the central processor 530 is connected to the direct storage access controller 520, the memory bus 511 in the data transmission device 510 is connected to the memory block 540, the direct storage access controller 520, and the central processor 530, and the peripheral bus 512 in the data transmission device 510 is connected to the external device 550, the direct storage access controller 520, and the central processor 530.
It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing is merely a specific embodiment of the disclosure to enable one skilled in the art to understand or practice the disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown and described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A data transmission apparatus, comprising:
the system comprises a memory bus and a peripheral bus, wherein the memory bus is used for sending read-write requests of a direct memory access controller and a central processing unit to a memory block to the memory block, and the peripheral bus is used for sending read-write requests of the direct memory access controller and the central processing unit to external equipment to the external equipment;
the memory bus comprises a memory arbitration module, wherein the memory arbitration module is used for arbitrating a first read-write request of the received direct memory access controller to the memory block and a second read-write request of the central processing unit to the memory block, and comprises a first arbitration unit and a second arbitration unit;
the first arbitration unit is used for determining the priority of the received read-write request as the highest priority when the received read-write request is the same as the initiator of the read-write request being processed;
the second arbitration unit is used for determining the priority of the received read-write request based on a polling scheduling algorithm when the received read-write request is different from the initiator of the read-write request being processed.
2. The apparatus of claim 1, wherein the memory bus comprises:
the first interface is connected with the direct memory access controller, and the first memory address decoding module is used for decoding a first read-write request of the memory block by the direct memory access controller and extracting the address of the memory block from the decoded first read-write request;
the second memory address decoding module is used for decoding a second read-write request of the memory block from the central processing unit and extracting the address of the memory block from the decoded second read-write request.
3. The apparatus of claim 2, wherein the memory arbitration module is coupled to the first memory address decoding module and the second memory address decoding module and configured to send the first read and write requests and the second read and write requests to memory blocks corresponding to the memory arbitration module according to priorities of the first read and write requests, wherein the memory arbitration module is in one-to-one correspondence with the memory blocks.
4. The apparatus of claim 1, wherein the peripheral bus comprises:
the first switching bridge is connected with the direct storage access controller and is used for converting the structure of the received third read-write request of the direct storage access controller to the external equipment into a first preset structure;
the first peripheral address decoding module is used for decoding the third read-write request after the structure conversion and extracting the address of the external equipment from the decoded third read-write request;
the second switching bridge is connected with the central processing unit and is used for converting the structure of the received fourth read-write request of the central processing unit to the external equipment into a second preset structure;
and the second external address decoding module is used for decoding the fourth read-write request after the structure conversion and extracting the address of the external equipment from the decoded fourth read-write request.
5. The apparatus of claim 4, wherein the peripheral bus further comprises:
the peripheral arbitration module is connected with the first peripheral address decoding module and the second peripheral address decoding module and used for arbitrating the received third read-write request and the received fourth read-write request, and sending the third read-write request and the fourth read-write request to external equipment corresponding to the peripheral arbitration module according to the priorities of the third read-write request and the fourth read-write request, wherein the peripheral arbitration module is in one-to-one correspondence with the external equipment;
and the synchronous processing module is connected with the external equipment and is used for carrying out clock synchronous processing on the data returned by the external equipment and sending the data to the direct memory access controller.
6. The apparatus of claim 5, wherein the synchronization processing module comprises:
a matching unit, configured to determine an address of a target channel corresponding to an address of an external device included in data returned by the external device, based on a mapping relationship between the address of the external device and an address of a channel in the direct memory access controller;
and the first sending unit is used for sending the data returned by the external equipment to the direct memory access controller through the target channel according to the address of the target channel.
7. The apparatus of claim 1, wherein the direct memory access controller comprises:
the third interface is connected with the central processing unit and the register is used for storing configuration parameters sent by the central processing unit, and the configuration parameters are used for configuring channels connected with the register;
the channel is used for sending a read-write request to a preset arbitration module and receiving data returned by the preset arbitration module;
the preset arbitration module is used for arbitrating the read-write request sent by the channel and the data returned by the memory bus and the peripheral bus, sending the read-write request to the memory bus or the peripheral bus according to the order of priority from high to low, and sending the data to the channel.
8. The apparatus of claim 7, wherein the channel comprises:
the inquiring unit is used for inquiring whether a read-write request corresponding to the channel exists or not based on the configuration parameters;
and the second sending unit is used for sending the read-write request to the preset arbitration module when the read-write request corresponding to the channel is inquired.
9. The apparatus of claim 7, wherein the direct memory access controller further comprises:
and the multiplexing module is used for forwarding the received read-write requests sent by the preset arbitration module to the external equipment and the memory block through the peripheral bus and the memory bus, and forwarding a plurality of groups of data returned by the external equipment and the memory block to the preset arbitration module.
10. A data transmission system comprising the data transmission device according to any one of claims 1 to 9, a direct memory access controller, a central processing unit, a memory block, and an external device;
the central processing unit is connected with the direct memory access controller, the memory bus is connected with the memory block, the direct memory access controller and the central processing unit, and the peripheral bus is connected with the external equipment, the direct memory access controller and the central processing unit.
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| EP1096387A1 (en) * | 1999-10-26 | 2001-05-02 | Bull S.A. | An arbitration unit for a bus |
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| WO2007023975A1 (en) * | 2005-08-22 | 2007-03-01 | Ssd Company Limited | Multi-processor, direct memory access controller, and serial data transmitting/receiving apparatus |
| JP5906625B2 (en) * | 2011-09-15 | 2016-04-20 | 株式会社リコー | Access control apparatus, image forming apparatus, and access control method |
| CN105404596B (en) * | 2015-10-30 | 2018-07-20 | 华为技术有限公司 | A kind of data transmission method, apparatus and system |
| CN109117396A (en) * | 2018-08-30 | 2019-01-01 | 山东经安纬固消防科技有限公司 | memory access method and system |
| CN113590512B (en) * | 2021-07-30 | 2023-09-29 | 眸芯科技（上海）有限公司 | Self-starting DMA device capable of directly connecting peripheral equipment and application |
| CN115048323B (en) * | 2022-08-16 | 2022-11-04 | 南京芯驰半导体科技有限公司 | Data transmission system and method based on DMA handshake protocol |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| EP1096387A1 (en) * | 1999-10-26 | 2001-05-02 | Bull S.A. | An arbitration unit for a bus |
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