CN1139880C - Bus arbitration method for controlling queue insertion function between chip sets - Google Patents

Abstract

The present invention relates to a bus arbitration method for controlling queue insertion functions among chip sets. A system sets a certain control chip to control a bus control right among chips at the beginning; when the other control chip has higher priority transaction data, the system can request the chip with the bus control right for releasing the control right via a queue insertion request signal; when the chip which has the control right receives the queue insertion request signal, a delay timer is started, and the chip needs to release the bus control right to the other party before the timer stops timing. Therefore, the control chip with higher transaction priority can deliver data in a short time, and the entire transmission efficiency is increased.

Description

The bus arbitration method that has the function of jumping the queue between the control chip group

Technical field

The present invention relates to a kind of chipset, the bus arbitration method that has the function of jumping the queue between the chip in data trade method in the control chip group in particularly a kind of computer system, the control chip group between the chip and the control chip group.

Background technology

Shown in Figure 1 is a kind of structure of using pci system in computer architecture.Central processing unit 10 is couple to pci bus 14 via main bridge (host bridge) 12.Pci bus 14 can couple the primary controller (master) of the peripheral device of a plurality of PCI compatibilities, and these master controllers can be as shown in the figure graphics adapter (graphic adapter) 16a, expansion bus bridge joint device (expansion bus bridge) 16b, network adapter (LAN adapter) 16c and personal computer system host bus adapter (SCSI host busadapter) 16d or the like.Each primary controller all can be sent request signal, and (request REQ) asks to use pci bus 14, and (grant GNT) gives primary controller, agrees that it uses pci bus 14 and the moderator in the main bridge 12 (arbiter) can be sent approval signal.

Data between the PCI compatible apparatus (as the north bridge in primary controller or the computer chip group) transmit and are mainly controlled by following adapter control signal.(cycle frame FRAME) was sent by beginning device (it can be primary controller or north bridge), in order to the beginning and the duration of indicating an accessing operation periodic frame.When the FRAME signal was sent, expression began to carry out by the data trade (transaction) of pci bus, represents that when the FRAME signal maintains electronegative potential data trade continues to carry out.At this moment, address bus AD just can send effective address (valid address) during address cycle, simultaneously can be at order/byte enable (command/byte enable, CBE[3:0]) line sends effective bus line command (satisfying the PCI specification), in order to destination apparatus is pointed out to begin the desired data trade kenel of device, wherein order/byte enable line is encoded into 16 kinds of different orders with 4, and it has specific definition in the PCI specification.And then send after the effective address, address bus AD sends the data that will transmit, and is called cycle data this period, is sent the byte enable signal of coding back bus line command simultaneously by the CBE line, thereby transmits data.When the FRAME signal stopped to send, the expression stateful transaction transmitted for the finishing touch data, or had finished data and transmitted.The beginning device is ready for signal, and (initiator ready, (target ready, TRDY) both are used, thereby can carry out the data transmission in order to indicate starting apparatus and destination apparatus to be ready for respectively IRDY) to be ready for signal with destination apparatus.Read action when carrying out one, the IRDY signal indication begins device and is ready to receive data; And when carrying out a write operation, TRDY signal indication destination apparatus is ready to receive data.(stop STOP) begins device in order to the indicating target matching requirements and stops present data trade behavior stop signal.

With reference to figure 2, the time sequential routine figure when this illustrates and carries out read operation with pci bus adapter.With pci bus carry out and finish that data shift during be called the bus trade cycle (bustransaction) 20, it comprises an address cycle (address phase) 22 and a plurality of cycle datas (dataphase), as 24a, 24b and 24c.Each cycle data 24a/b/c divides into latent period (wait cycle) 26a/b/c and data migration period (data transfer cycle) 28a/b/c again respectively.Then, come the effect of operation of simple declaration pci system and previously described PCI specification control signal by a read operation in conjunction with the sequential chart of Fig. 2.

When period T 1, beginning device (primary controller) is sent the REQ signal, with request master control pci bus, if there are not other more device request use pci buss of high priority this moment, then when period T 2, main bridge (moderator) is sent the GNT signal, to allow beginning device master control pci bus, during period T 3, the beginning device is sent the FRAME signal, represents that data shift to carry out beginning, and sends start address (start address) in the AD bus, in order to specify a destination apparatus, send a reading order by the CBE line simultaneously.And then the reading order of sending, CBE line can be sent byte enable signal (byte enable), and this byte enable signal (comprises 24a, 24b and 24c) during whole cycle data can continue to send always.When period T 4, the beginning device is sent and is ready for signal IRDY, and expression can begin the sending and receiving data, however since this moment destination apparatus fail to be ready for, be the latent period 26a of cycle data 24a this period, promptly begins device and wait for that destination apparatus is ready for data.When period T 5, destination apparatus has been ready for and has been sent and has been ready for signal TRDY, therefore during the data migration period 28a that IRDY and TRDY signal are all sent, begins device from the destination apparatus reading of data.Destination apparatus finishes to send the TRDY signal in period T 6, transmits with the expression end data, and begins to prepare second batch data, and be the latent period 26a of cycle data 24b this moment.When period T 7, TRDY sends once again, and the expression data are ready for, and during the data migration period 28b that IRDY and TRDY signal are all sent, begins device from the destination apparatus reading of data.When the beginning device had little time reading of data, the beginning device finished to send the IRDY signal in period T 8, and still send because of the TRDY signal this moment, so this waits for that cycle 26c is started by the beginning device.After device is ready for, send IRDY signal in period T 9 Deng beginning, begin device from the destination apparatus reading of data this moment during the data migration period 28c that IRDY and TRDY signal are all sent again.No longer need reading of data because the beginning device when period T 9, has just been known, so the beginning device finishes to send the FRAME signal and finishes to send the REQ signal, when period T 10, moderator finishes to send the GNT signal.So far, finish a read operation.

As mentioned above, in the PCI specification,, must use frequent control signal, waiting status and procedures of arbitration etc., and the signal of PCI defined have 45-50 signal pins at least in order to finish the data trade of PCI specification.Structure in the present PC and system shown in Figure 1 are closely similar, wherein main bridge 12 is exactly the north bridge chips of motherboard inner control chipset, and South Bridge chip comprises expansion bus bridge joint device 16b, and the south bridge in the personal computer system is main and a certainly exist primary controller.Graphics adapter Mk as in the personal computer system is not connected to pci bus, and (accelerated graphic port, AGP) adapter is connected to north bridge chips but quicken port by a drawing.

Yet, in general the data trade of chip chamber does not often need to use the so complicated function program of general multi-usage bus in the control chip group, for example: the data trade of the north and south bridge of motherboard control chip group inside, do not need to use the so complicated program of complete pci bus, and the program of this complexity has in most cases been sacrificed many performance characteristics in order to ensure being suitable for multiple applied environment.And trend along with Highgrade integration, arbitrary control chip may merge greater functionality, for example CPU and north bridge chips are merged into a chip, or control chip group itself is merged into a chip, make the pin on the packing chip become a very valuable resource, must reduce pin as far as possible to reduce the cost of control chip.Therefore in order to quicken the data trade between the control chip group inside, and save the resource of chip pin, a kind of simplification but still satisfy that the special bus specification of data trade is needs between control chip.For example: a kind of high-speed bus specification that can simplify a plurality of signal wires of design between the bridge of north and south, and this bus specification handle at chip internal must as far as possible approximate general PCI specification, with chip in other module group compatibilities, avoid control chip to make too much modification.

Between chipset,, chip temporary just can transmit data when having bus master, but when a certain chip is occupied bus master power always, and another chip has higher prior to conclude the business in the time of will carrying out (for example having data such as sound or image to transmit), because can not get bus master power the higher prior transaction can't be carried out.

Summary of the invention

The purpose of this invention is to provide a kind of referee method of jumping the queue when arbitrary control chip is the bus owner, make between chipset and can finish the high priority transaction by the mode of jumping the queue.

Correspondingly, the invention provides a kind of method of between control chip group, carrying out bus arbitration, be used for a computer system, described control chip group comprises one first control chip and one second control chip, when described first and second control chip transmits data mutually by a chip chamber bus, can finish high priority transaction by the request signal of jumping the queue, described chip chamber bus comprises uses bidirectional bus altogether, and described bus arbitration method comprises the following steps:

When described second control chip need use described chip chamber bus, described second control chip sent one second bus request signal;

When described first control chip detects described second bus request signal, if first bus request signal of described first control chip is for forbidding, then described second control chip will become next described bus owner, if described first bus request signal of described first control chip is for enabling, then described first control chip still is described bus owner, but if the request signal of described second control chip is high when preferential, then described second control chip can send the described request signal of jumping the queue; And

Send described jumping the queue during request signal when described first control chip detects described second control chip, start a delay timer, before this delay timer timing stops, described second control chip will become next described bus owner.

According to the referee method of jumping the queue when arbitrary control chip is the bus owner of the present invention, set a certain control chip when system begins and grasp the control of chip chamber bus, when another control chip has the higher-priority transaction data, can discharge control by the chip that the request of jumping the queue (preempt request) request signal has a bus control right, when the chip that has control is received start delay timer (latency timer) when jumping the queue request signal, before the timer timing ends, must discharge bus control right and give the other side, make to have higher-priority controls transactions chip and can at short notice data be sent, and then improve whole transmission benefit.

According to the method for in control chip group, carrying out the method for data trade and in control chip group, carrying out bus arbitration between the chip between the chip of the present invention, can improve the usefulness of control chip group data trade, and the kind and the quantity of the signal wire in the simplification control chip group, that is the bus between the simplification control chip.

For above-mentioned purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and in conjunction with the accompanying drawings, be described in detail below.

The simple declaration of accompanying drawing

Fig. 1 illustrates a kind of structural representation that uses the pci bus system in computer architecture of prior art;

Sequential chart when the primary controller that Fig. 2 illustrates a pci system carries out read operation is in order to each control signal of simple declaration pci system;

Fig. 3 illustrates the block diagram according to a kind of control chip group of a preferred embodiment of the present invention;

Fig. 4 illustrates the timing diagram between the data bit time of transmitting in one embodiment of the invention (bit time) and bus clock pulse signal and the line trigger signal;

Fig. 5 illustrates in one embodiment of the invention to Fig. 6, and the signal timing diagram of bus is used in relevant first control chip and the second control chip request; And

Fig. 7 illustrates in one embodiment of the invention, and relevant first control chip and second control chip reach to pass down by upload command (up link command) signal wire orders (down link command) signal wire to carry out the signal timing diagram of jumping the queue and asking.

Label declaration:

10 central processing units, 12 main bridges

14 pci bus 16a graphics adapter

16b expansion bus bridge joint device 16c network adapter

The 16d scsi adapter

20 bus trade cycles 22 address cycles

24a/b/c cycle data 26a/b/c latent period

The 28a/b/c data transfer cycles

30 south bridges, 32 north bridges

34 CPU, 36 storeies

Preferred embodiment

The invention provides the data trade method of chip chamber in a kind of control chip group and the bus arbitration method of the interior chip chamber of control chip group, can improve the usefulness of control chip group data trade, and the kind and the quantity of the signal wire in the simplification control chip group, that is the bus between the simplification control chip.The present invention is an example with the control chip group that south bridge and north bridge were constituted in the computer motherboard, redefine several command signals, be called the high-transmission storer at this and link (High Through-put Memory Link is called for short HTML), to simplify the pci bus signal of original complexity.In this preferred embodiment, original south bridge and the signal wire between the north bridge need 45 signal line, and the present invention replaces original pci bus signal wire with 15 command signal line.

Please refer to Fig. 3 and table one, wherein Fig. 3 is the block diagram according to a kind of control chip group of a preferred embodiment of the present invention, and Fig. 3 also illustrates south bridge in the control chip group and the signal wire between north bridge; And table one describes the meaning of these signal wires in detail.By Fig. 3 and table one as can be known, control chip group of the present invention comprises south bridge 30 and north bridge 32 these two control chips, 45 original between south bridge 30 and the north bridge 32 signal pins are reduced to 15, and unnecessary pin can be provided as other purposes, to promote the function of control chip group.

Shown in Fig. 3 and table one, keep between south bridge 30 and the north bridge 32 original pci bus agreement specification fixed address data bus (AD bus), but it is reduced to only 8 bidirectional signal lines, other are as CBE, FRAME, IRDY, TRDY, STOP, DEVSEL, REQ and GNT equisignal line, be reduced to two-way upload command (uplink command) UPCMD who enables the BE signal wire and driven, upload triggering (up link strobe) UPSTB by south bridge 30; And by following biography order (the down link command) DNCMD that north bridge 32 drove, following triggering (down linkstrobe) the DNSTB signal wire etc. that passes.South bridge 30 respectively drives an independently command signal line with north bridge 32, represents this preferred embodiment to have full duplex order transmitting function, can send bus line command separately at any time.If when sending bus line command, have the bus right to use, can send data at address data bus simultaneously, also can on address data bus, send the address, and send the length information of present order at the BE signal wire.

Table one

Signal	Driver	Explanation
			CLK		The clock pulse signal of 66MHz
DNSTB	North bridge	The following biography triggered
			UPSTB	South bridge	Upload triggering
DNCMD	North bridge	The following biography ordered
			UPCMD	South bridge	Upload command
BE	Northbridge/southbridge	Byte enable
			AD[7:0]	Northbridge/southbridge	Address/data bus
VREF		Reference voltage
			COMP		Impedance ratio

Please refer to Fig. 4, this figure defines the sequential relationship between arbitrary data line transmission data bit time of the present invention and bus clock pulse signal and the line trigger signal.As can be seen from the figure, comprise clock cycle two clock pulse signals that trigger STB, that is be 2 times of clock frequency on the clock pulse signal line uploading line trigger signal and pass line trigger signal down operation frequency when activating.Utilize the rise and fall edge of trigger pip can define four bit times 0～3 altogether, utilize these four bit times can obtain the data of 4 positions altogether, and can carry out the coding of bus line command.So 8 data lines, can obtain 32 data each clock cycle, and its effect equals in pci bus, has 32 data lines transmitting data simultaneously.And when representing length information, can draw 1-16 (4) data length information a clock cycle such as the BE signal wire.

Upload command UPCMD and the following order DNCMD that passes define various data trade kenel.Comprised by the upload command UPCMD that south bridge 30 drove: north bridge confirms that to reading of south bridge order C2PRA, north bridge confirm to order C2PWA, the south bridge write command P2CW to the reading order P2CR of north bridge, south bridge to north bridge etc. to writing of south bridge.The encoding relation of they and bit time as shown in Table 2, please note, the REQ bus request signal is to send at bit time 0, also underlapped with the order of other data trade kenels, so at any time, even, can send this REQ signal simultaneously in the same clock cycle of sending the order of data trade kenel.The following biography order DNCMD that is driven by north bridge 32 comprises: north bridge orders P2CRA, south bridge to the write affirmation of north bridge to order P2CWA to memory writer command C2PMW, the south bridge of south bridge to the affirmation of reading of north bridge to output input write command C2PIOW, the north bridge of south bridge to memory read command fetch C2PMR, the north bridge of south bridge to the output of south bridge input reading order C2PIOR, north bridge, and the encoding relation of they and bit time as shown in Table 3.Note that the signal definition that does not have in the present embodiment about GNT.

Table two (upload command UPCMD)

Bit time 0 REQ	Bit time	1 PMSTR	Bit time	2 MIO	Bit time 3 WR	Explanation
							-	0	-	0	C2PRA
-	0	-	1	C2PWA
					-	1	0	0	P2CR
-	1	0	1	P2CW
					-	1	1	1	NOP
0	-	-	-	UPREQ

Table three (passing order DNCMD down)

Bit time 0 REQ	Bit time	1 PMSTR	Bit time	2 MIO	Bit time 3 WR	Explanation
							-	0	0	0	C2PIOR
-	0	0	1	C2PIOW

-	0	1	0	C2PMR
					-	0	1	1	C2PMW
-	1	0	0	P2CRA
					-	1	0	1	P2CWA
-	1	1	1	NOP
					0	-	-	-	DNREQ

South bridge is corresponding with the order that north bridge chips is sent in the mentioned order, and after south bridge sent several P2CR and/or P2CW order in regular turn, the order that north bridge must be given an order according to south bridge was fully responded corresponding P2CRA and/or P2CWA order.After north bridge sent several C2PIOR, C2PMR, C2PIOW and C2PMW order in regular turn, south bridge must be responded corresponding C2PRA and C2PWA order in regular turn.In the present embodiment, when each control chip was given an order, its related data must be ready to earlier.For example, when south bridge sends P2CW, must the data that will write are ready, when north bridge sends P2CRA, the sense data that will pass back must be ready to fully, the situation can't continue to avoid having data to pause in the middle of the transmission data, when not having other orders to send, control chip sends nop command.

A kind of referee method of jumping the queue when arbitrary control chip is the bus owner of the present invention, its environment of operation must be: control chip group comprises first control chip (as: north bridge chips) and second control chip (as: South Bridge chip), when first and second control chip by chip chamber bus (as: HTML) when transmitting data mutually, do not have latent period, described chip chamber bus must include shared bidirectional bus, otherwise just need not arbitrate.Shown in a kind of motherboard north and south bridge control chip group of preferred embodiment of the present invention as shown in Figure 3.

At first, second control chip must know that all have the bus line command of fixed clock umber of pulse and the clock pulses number of the described shared bidirectional bus of its use about first control chip.When second control chip sends first order (as: reading order) to first control chip, second control chip must be stored first of first control chip transmission correspondence and order accept one's fate really order and the required clock pulses number of data, and the information during wherein the clock pulses number that first control chip response affirmation is ordered and data are required is ordered by first decides.For example: south bridge sends P2CR when ordering to north bridge, because the data that sense data length is arranged are interior, because HTML does not have latent period when transmitting data, sends corresponding P2CRA order and the required clock pulses number of data so south bridge is known north bridge again.

Table four (referee method of jumping the queue when arbitrary control chip is the bus owner)

Bus is gathered around

DNRE

UPR

Next bus is gathered around

The function of jumping the queue

The person of having	Q	EQ	The person of having
					N	0	0	N
N	0	1	S
					N
	1	0	N
					N
	1	1	N	S can jump the queue
					S	0	0	S
S
		1	0	N
S						0	1	S
	S
		1	1	S	N can jump the queue

Table four is depicted as the various combinations of the referee method of jumping the queue when arbitrary control chip is the bus owner, wherein N represents first control chip (for example being north bridge chips), S represents second control chip (for example being South Bridge chip), on behalf of first control chip, DNREQ send first bus request signal, on behalf of second control chip, UPREQ send second bus request signal, S can jump the queue and represent first control chip to have bus control right, and second control chip has the data of higher-priority transaction, thereby send the request signal of jumping the queue, N can jump the queue and represent second control chip to have bus control right, and first control chip has the data of higher-priority transaction, thereby sends the request signal of jumping the queue.

First control chip has bus control right when system begins, if first control chip and second control chip all do not send bus request signal, then first control chip will continue to have bus control right.

When first control chip has bus control right, first control chip does not send first bus request signal and second control chip when sending the second bus request signal UPREQ, and second control chip will become next bus control right owner.

When first control chip has bus control right, first control chip sends the first bus request signal DNREQ and second control chip when not sending second bus request signal, and first control chip will continue to become next bus control right owner.

When first control chip has bus control right, first control chip sends the first bus request signal DNREQ and second control chip when also sending the second bus request signal UPREQ, this moment, first control chip will continue to become next bus control right owner, but second control chip can be sent the request signal of jumping the queue by the upload command signal wire, before delay timer (latency timer) timing stops, obtain bus control right with request, thereby finish the transaction of higher prior.

When second control chip has bus control right, when second control chip or first control chip did not all send bus request signal, second control chip will continue to have bus control right.

When second control chip has bus control right, second control chip does not send second bus request signal and first control chip when sending the first bus request signal DNREQ, and first control chip will become next bus control right owner.

When second control chip has bus control right, second control chip sends the second bus request signal UPREQ and first control chip when not sending first bus request signal, and second control chip will continue to become next bus control right owner.

When second control chip has bus control right, second control chip sends the second bus request signal UPREQ and first control chip when also sending the first bus request signal DNREQ, this moment, second control chip will continue to become next bus control right owner, but first control chip can by under pass command signal line and send the request signal of jumping the queue, before the delay timer timing stops, obtain bus control right with request, thereby finish the transaction of higher prior.

After second control chip sends the second bus request signal UPREQ, whether testbus is just used by first control chip, when second control chip does not detect first control chip and is just using described chip chamber bus, second control chip is waited for behind the predetermined period and is continued to detect described chip chamber bus, drive described chip chamber bus again, the fundamental purpose of waiting for described predetermined period is, because signal transmits in the chip chamber bus and has transmission delay, so described predetermined period can avoid first control chip to send order, and second control chip takes for first control chip and is not just using described chip chamber bus.In addition, drive described chip chamber bus simultaneously for avoiding two control chips, the conversion bus control right will have the transformation cycle (turn-around cycle) of a clock cycle at least.

When second control chip detects first control chip and just using the chip chamber bus, must wait for that first control chip surrenders the bus right to use up to it.If second control chip is waited for too for a long time or is had the transaction data of higher prior to send, can send the signal of jumping the queue at upload command UPCMD signal wire, force first control chip to abdicate the bus right to use.

The time sequences of embodiments of the invention then is described with several examples.

Fig. 5 shows in one embodiment of the invention to Fig. 6, and the signal timing diagram of bus is used in relevant first control chip and the second control chip request.Please refer to Fig. 5, wherein HCLK represents the clock pulse signal of HTML, DNREQ# represents first bus request signal of first control chip, wherein # represents the electronegative potential action, UPREQ# represents second bus request signal of second control chip, NOE# represents the output enable signal of first control chip, and SOE# represents the output enable signal of second control chip, and AD represents the shared bidirectional bus signal between first control chip and second control chip.

Please refer to Fig. 5, at time T 1 and T2, because DNREQ# and UPREQ# are for forbidding (noble potential), therefore first control chip has bus control right (systemic presupposition value).For transaction (transaction) can be begun at T4, DNREQ# must become when T3 and enables (electronegative potential).UPREQ# becomes and enables when T5, but enables because of DNREQ# maintains before T11, and therefore second control chip can not become the bus owner.Because first control chip does not need bus when T11, therefore become and forbid at T10 DNREQ# in season.Because UPREQ# keeps and enables T9 and DNREQ# and become when T10 and forbid, NOE# becomes and forbids during T11, therefore through T11 change all after date second control chips when T12 driving data to bus.Second control chip does not need bus when T13, so UPREQ# becomes and forbids during T12.But, DNREQ# forbids that therefore second control chip still is the bus owner because of keeping when T11 and the T12.DNREQ# becomes and enables when T13, and UPREQ# keeps and enables when T14, and therefore second control chip still is the bus owner, begins a transaction when T15.When T16 UPREQ# become forbid and when T15 DNREQ# become and enable, therefore second control chip loses bus control right when T17, first control chip becomes the bus owner once more when T18.

Please refer to Fig. 6, except DNREQ# when the T16 become forbid and become during at T17 enable, all the other and Fig. 5 are similar.This result is a false request (dummy request).First control chip still is bus owner (bus owner) and begins a transaction when T18.Second control chip that becomes bus recipient (busreceiver) can not become the bus owner when T18, forbid though first control chip has become DNREQ# when T16, and the bus recipient has become UPREQ# when T15 and enables.Therefore, after a control chip becomes the bus recipient from the bus owner, can not become the bus owner once more in two cycles after the change-over period.

Please refer to Fig. 7, this illustrates in one embodiment of the invention, and relevant first control chip and second control chip reach by the upload command signal wire and pass the signal timing diagram that command signal line is carried out the request of jumping the queue down.Please refer to Fig. 7, in Fig. 5, first control chip T7 not transaction to carry out, therefore can be when T6 DNREQ# be become and forbids, so will cause bus to enter the transformation cycle at T7.First control chip loses bus control right and second control chip is obtained bus control right at T8 at T7.Above-mentioned situation depends on whether the bus owner can become request signal when next cycle is not wanted to use bus forbids.

Please refer to Fig. 5, be noted that, want to use bus during at T5, still, do not forbid that therefore second control chip can not begin its transaction because first control chip makes DNREQ# become when second control chip.In the case, second control chip drives the order of jumping the queue by upload command signal wire UPCMD, and it has the transaction of higher prior to carry out to inform first control chip.Please refer to Fig. 7, want to use bus during at T7, still, do not forbid that therefore first control chip can not begin its transaction because second control chip makes UPREQ# become when first control chip.In the case, first control chip by under pass command signal line DNCMD and drive the order of jumping the queue, it has the transaction of higher prior to carry out to inform second control chip, after second control chip is received this order, can start a delay timer, stop preceding second control chip in the timer timing and must discharge bus control right, first control chip like this can guarantee to obtain within a certain period of time bus control right to carry out the transaction of higher prior.

In sum; though the present invention is disclosed as above with preferred embodiment; yet the various embodiments described above are not in order to limit the present invention; those of ordinary skills are under the situation that does not break away from the spirit and scope of the present invention; can do various changes and retouching to the present invention, so protection scope of the present invention should be by being as the criterion that the accompanying Claim book is limited.

Claims (9)

1. method of between control chip group, carrying out bus arbitration, be used for a computer system, described control chip group comprises one first control chip and one second control chip, when described first and second control chip transmits data mutually by a chip chamber bus, can finish high priority transaction by the request signal of jumping the queue, described chip chamber bus comprises uses bidirectional bus altogether, and described bus arbitration method comprises the following steps:

When described second control chip need use described chip chamber bus, described second control chip sent one second bus request signal;

When described first control chip detects described second bus request signal, if first bus request signal of described first control chip is for forbidding, then described second control chip will become next described bus owner, if described first bus request signal of described first control chip is for enabling, then described first control chip still is described bus owner, but if the request signal of described second control chip is high when preferential, then described second control chip can send the described request signal of jumping the queue; And

Send described jumping the queue during request signal when described first control chip detects described second control chip, start a delay timer, before this delay timer timing stops, described second control chip will become next described bus owner.

2. the method for claim 1, wherein when described computer system began, default described first control chip was the bus owner, described second control chip is the bus recipient.

3. the method for claim 1, wherein said bus recipient only forbids described bus request signal described bus owner before two cycles, and when described bus recipient enables described bus request signal before three cycles, just can drive described shared bidirectional bus.

4. method as claimed in claim 3 wherein when described bus recipient becomes described bus owner, needs to wait for that one changes all after dates and just can drive described shared bidirectional bus.

5. the method for claim 1, wherein said bus owner is two all after dates before the described bus request signal of one-period and described bus recipient before the more described bus request signal, and whether following 1 cycle of decision continues to have the described bus right to use.

6. the method for claim 1, described chip chamber bus comprises: an address data bus, one length/byte enable signal wire, a upload command signal wire, are uploaded line trigger signal, are passed command signal line once, pass a line trigger signal and a time clock signal wire once, wherein said shared bidirectional bus comprises described address data bus and described length/byte enable signal wire.

7. method as claimed in claim 6, the wherein said request signal of jumping the queue sends via described upload command signal wire and the described command signal line that passes down.

8. the method for claim 1, wherein said first control chip is a north bridge chips, described second control chip is a South Bridge chip.

9. the method for claim 1, wherein said first control chip is a South Bridge chip, described second control chip is a north bridge chips.

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