CN116028413A - Bus arbiter, bus arbitration method, device and medium - Google Patents
Bus arbiter, bus arbitration method, device and medium Download PDFInfo
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Abstract
The application relates to the technical field of bus arbitration, and discloses a bus arbiter, a bus arbitration method, a bus arbitration device and a bus arbitration medium, wherein the bus arbiter comprises the following components: the system comprises an arbitration unit and a processing unit, wherein the arbitration unit comprises a read arbitration module and a write arbitration module which support multi-path arbitration, the output end of the arbitration unit is connected with the processing unit, the input end of the arbitration unit is connected with each main device, and the arbitration unit is used for arbitrating the request of each main device based on a preset arbitration algorithm after determining that the request instruction sent by each main device is received, and transmitting the arbitration result to the processing unit. The processing unit is connected with the slave device and is used for sending a corresponding operation instruction to the slave device according to the arbitration result. Therefore, the read arbitration module and the write arbitration module supporting multi-path arbitration form an arbitration unit, so that parallel arbitration of read-write requests is realized in order to improve arbitration efficiency besides simultaneously arbitrating requests of a plurality of main devices, namely, the separation design of read-write arbitration can further improve arbitration efficiency, further realize high-efficiency completion of bus transmission and improve system reliability.
Description
Technical Field
The present disclosure relates to the field of bus arbitration technologies, and in particular, to a bus arbiter, a method, an apparatus, and a medium for bus arbitration.
Background
With the continuous development of nano-processing technology, the feature size of integrated circuit chips is smaller and smaller, and more transistors are on unit chips, so that the realization of a complex electronic system on a single integrated circuit chip has become one of the hot subjects of the researches of students. Integrated circuits have thus come into the era of System on Chip (SoC), and with the rapid development of SoC, more and more modules are integrated on the same Chip, and the communication bus technology between the modules of the System has become one of the key problems of SoC, so at present, bus structure and bus arbitration are the main methods for solving the resource conflicts of the System on Chip.
Bus structures are commonly used to interconnect devices, and are widely used in high performance computer systems and servers today to interconnect processors due to their low cost and simple construction. An important issue in bus architecture is bus arbitration, a mechanism whereby one and only one device is selected to control the bus when multiple devices contend for bus resources.
When a plurality of master devices simultaneously need to use buses, competition for resources can occur, and arbitration scheduling is a main method for solving the conflict of SoC resources. The bus arbitration device with arbitration scheduling controls the use right of the bus, determines the use priority of the main devices on the bus, monitors the bus request initiated by each main device, grants the control right of the bus to the main device with the highest priority according to the priority of an arbitration algorithm, reasonably schedules a plurality of main devices, and avoids congestion or data loss caused by the occurrence of a jam of a random order.
Currently, bus resources are typically scheduled using a peripheral bus (Advanced Peripheral Bus, abbreviated APB) arbitrated multiplexer scheme. In the APB bus arbitrated multiplexer, a digital selector (MUX) needs to be controlled by a system configuration or a chip external selection signal, so as to realize the selection of a plurality of APB main devices.
FIG. 1 is a block diagram of an APB bus arbiter circuit as shown in FIG. 1As shown, when the number of hosts is greater than 2, arbitration needs to be achieved through multi-stage concatenation, when the number of hosts is 4, 3 arbitration modules are needed to perform 2-stage arbitration, and so on, when the number of hosts is 4 2 n When it is needed 2 n The n-level arbitration is performed by 1 arbitration module, and obviously, too many arbitration stages can result in low arbitration efficiency. In addition, the problems of time sequence coordination, mutual interference and the like are required to be considered among all levels of cascade connection, so that the complexity of accessing the APB bus space by a plurality of main devices and the complexity of switching access are increased, and if the access switching is frequent, the overall access efficiency of the bus is further reduced.
Therefore, how to improve the bus arbitration efficiency and efficiently complete the bus transmission is a problem to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a bus arbiter, a bus arbitration method, a bus arbitration device and a bus arbitration medium, which improve bus arbitration efficiency and efficiently complete bus transmission.
To solve the above technical problem, the present application provides a bus arbiter, including: an arbitration unit and a processing unit;
the arbitration unit comprises a read arbitration module and a write arbitration module which support multi-path arbitration, the output end of the arbitration unit is connected with the processing unit, and the input end of the arbitration unit is connected with each main device;
after determining that the request instruction sent by each main device is received, the arbitration unit arbitrates the request of each main device based on a preset arbitration algorithm to obtain an arbitration result, and transmits the arbitration result to the processing unit;
The processing unit is connected with the slave device and is used for sending a corresponding operation instruction to the slave device according to the arbitration result after receiving the arbitration result.
Preferably, the arbitration unit further comprises a logic operation module;
the input end of the logic operation module is used as the input end of the arbitration unit, the output end of the logic operation module is respectively connected with the read arbitration module and the write arbitration module and is used for analyzing the request instruction of the main equipment, and a mark register is maintained according to the analysis result so that the read arbitration module and the write arbitration module can determine whether the request instruction of the main equipment is received or not according to the mark register.
Preferably, the processing unit comprises a read address distribution module and a write cache module;
the input end of the read address distribution module is connected with the output end of the read arbitration module, and is used for sequentially gating and obtaining authorized main equipment addresses according to the arbitration result sequence of the read arbitration module and generating corresponding read operation requests;
the input end of the write buffer module is connected with the output end of the write arbitration module, and is used for sequentially temporarily storing the write address and write data information of each main device according to the arbitration result sequence of the write arbitration module, and generating a corresponding write operation request.
Preferably, the processing unit further comprises a read-write ping-pong operation module;
the input end of the read-write ping-pong operation module is respectively connected with the output end of the read address distribution module and the output end of the write cache module, and the output end of the read-write ping-pong operation module is connected with the slave device and is used for sending a corresponding operation instruction to the slave device according to a ping-pong operation strategy after the read operation request and the write operation request are acquired.
Preferably, the processing unit further comprises a read data distribution module and a response distribution module;
the input end of the read data distribution module is connected with the output end of the read-write ping-pong operation module, the output end of the read data distribution module is respectively connected with the input end of the response distribution module, the input end of the read arbitration module and each main device are connected, and the read data distribution module is used for latching the arbitration result of the read arbitration module, and when receiving the data returned by the read-write ping-pong operation module, the read data distribution module is used for gating the returned data to the corresponding main device according to the latched arbitration result and simultaneously sending a first state control instruction to the response distribution module;
the input end of the response distribution module is connected with the output end of the write arbitration module, and the output end of the response distribution module is connected with each main device and is used for acquiring the second state control instruction and the first state control instruction sent by the write arbitration module and setting the transmission state of the corresponding main device according to the first state control instruction or the second state control instruction.
Preferably, the ping-pong operation policy is that if a read operation request is sent last time, a write operation request is sent currently, and if a write operation request is sent last time, a read operation request is sent currently; and if the read operation request and the slave equipment address information corresponding to the write operation request are the same, transmitting data corresponding to the write operation request to the read data distribution module.
In order to solve the above technical problems, the present application further provides a method for bus arbitration, which is applied to the bus arbiter, and includes:
determining whether a request instruction sent by the main equipment is received;
if yes, carrying out arbitration on the requests of the master devices based on a preset arbitration algorithm to obtain an arbitration result;
and transmitting the arbitration result to a processing unit so that the processing unit can conveniently transmit a corresponding operation instruction to the slave device according to the arbitration result.
In order to solve the above technical problem, the present application further provides a device for bus arbitration, which is applied to the bus arbiter, and includes:
the determining module is used for determining whether a request instruction sent by the main equipment is received, and if yes, the arbitration module is called;
The arbitration module is used for arbitrating the requests of the master devices based on a preset arbitration algorithm to obtain arbitration results;
and the transmission module is used for transmitting the arbitration result to the processing unit so that the processing unit can conveniently transmit a corresponding operation instruction to the slave device according to the arbitration result.
In order to solve the technical problem, the present application further provides a bus arbitration device, including a memory for storing a computer program;
and a processor for implementing the steps of the method of bus arbitration when executing the computer program.
To solve the above technical problem, the present application further provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor, implements the steps of the bus arbitration method.
The invention provides a bus arbiter, comprising: the system comprises an arbitration unit and a processing unit, wherein the arbitration unit comprises a read arbitration module and a write arbitration module which support multi-path arbitration, the output end of the arbitration unit is connected with the processing unit, the input end of the arbitration unit is connected with each main device, the arbitration unit arbitrates the request of each main device based on a preset arbitration algorithm to obtain an arbitration result after determining that the request instruction sent by each main device is received, and the arbitration result is transmitted to the processing unit. The processing unit is also connected with the slave device and is used for sending a corresponding operation instruction to the slave device according to the arbitration result after receiving the arbitration result. Therefore, according to the technical scheme provided by the application, the read arbitration module and the write arbitration module supporting multi-path arbitration form an arbitration unit, so that parallel arbitration of read-write requests is realized in order to improve arbitration efficiency besides simultaneously arbitrating requests of a plurality of main devices, namely, the separation design of read-write arbitration can further improve arbitration efficiency, further realize high-efficiency completion of bus transmission, and improve system reliability.
In addition, the application also provides a bus arbitration method, device and medium, which correspond to the bus arbiter and have the same effects.
Drawings
For a clearer description of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of an APB bus arbitration circuit provided herein;
FIG. 2 is a schematic diagram of an APB bus state transition according to an embodiment of the present disclosure;
FIG. 3 (a) is a timing diagram of APB bus read transfer provided in an embodiment of the present application;
FIG. 3 (b) is a timing diagram of APB bus write transfer provided by an embodiment of the present application;
FIG. 4 is a block diagram of a bus arbiter according to an embodiment of the present application;
FIG. 5 is a block diagram of another bus arbiter according to an embodiment of the present application;
FIG. 6 is a flow chart of a method for bus arbitration according to an embodiment of the present application;
FIG. 7 (a) is a diagram illustrating a write transfer timing sequence for an APB wait-free state according to an embodiment of the present disclosure;
FIG. 7 (b) is a diagram illustrating a read transfer timing of an APB wait state according to an embodiment of the present disclosure;
FIG. 8 is a timing diagram of an arbitration transmission according to an embodiment of the present application;
FIG. 9 is a block diagram of a bus arbitrating device according to an embodiment of the present application;
FIG. 10 is a block diagram of a bus arbitrating device according to another embodiment of the present application;
the reference numerals are as follows: the system comprises an arbitration unit 1, a processing unit 2, a read arbitration module 3, a write arbitration module 4, a logic operation module 5, a read address distribution module 6, a write cache module 7, a read-write ping-pong operation module 8, a read data distribution module 9 and a response distribution module 10.
Detailed Description
The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments herein without making any inventive effort are intended to fall within the scope of the present application.
The core of the application is to provide a bus arbiter, a bus arbitration method, a bus arbitration device and a bus arbitration medium, wherein an arbitration unit is formed by a read arbitration module and a write arbitration module which support multi-path arbitration, so that the multi-path master equipment is utilized to simultaneously perform arbitration so as to improve the arbitration efficiency, and the read arbitration and the write arbitration are mutually independent, thereby further improving the arbitration efficiency.
In order to provide a better understanding of the present application, those skilled in the art will now make further details of the present application with reference to the drawings and detailed description.
With the continuous development of nano-processing technology, the feature size of integrated circuit chips is smaller and smaller, and more transistors are on unit chips, so that the realization of a complex electronic system on a single integrated circuit chip has become one of the hot subjects of the researches of students. Integrated circuits have thus come into the era of System on Chip (SoC), and with the rapid development of SoC, more and more modules are integrated on the same Chip, and the communication bus technology between the modules of the System has become one of the key problems of SoC, so at present, bus structure and bus arbitration are the main methods for solving the resource conflicts of the System on Chip.
Bus structures are commonly used to interconnect devices, and are widely used in high performance computer systems and servers today to interconnect processors due to their low cost and simple construction. An important issue in bus architecture is bus arbitration, a mechanism whereby one and only one device is selected to control the bus when multiple devices contend for bus resources.
When a plurality of master devices simultaneously need to use buses, competition for resources can occur, and arbitration scheduling is a main method for solving the conflict of SoC resources. The bus arbitration device with arbitration scheduling controls the use right of the bus, determines the use priority of the main devices on the bus, monitors the bus request initiated by each main device, grants the control right of the bus to the main device with the highest priority according to the priority of an arbitration algorithm, reasonably schedules a plurality of main devices, and avoids congestion or data loss caused by the occurrence of a jam of a random order.
Currently, bus resources are typically scheduled using a peripheral bus (Advanced Peripheral Bus, abbreviated APB) arbitrated multiplexer scheme. In the APB bus arbitrated multiplexer, a digital selector (MUX) needs to be controlled by a system configuration or a chip external selection signal, so as to realize the selection of a plurality of APB main devices.
As shown in fig. 1, when the number of hosts is greater than 2, arbitration needs to be achieved through multi-stage cascading, when the number of hosts is 4, 3 arbitration modules are needed to perform 2-stage arbitration, and so on, when the number of hosts is 4 2 n When it is needed 2 n The n-level arbitration is performed by 1 arbitration module, and obviously, too many arbitration stages can result in low arbitration efficiency. In addition, the problems of time sequence coordination, mutual interference and the like are required to be considered among all levels of cascade connection, so that the complexity of accessing the APB bus space by a plurality of main devices and the complexity of switching access are increased, and if the access switching is frequent, the overall access efficiency of the bus is further reduced.
In bus arbitration, arbitration schemes can be classified into distributed arbitration and centralized arbitration. In the distributed arbitration mode, each master device has its own corresponding arbitration component, and the arbitration component determines whether to occupy the priority of the bus resource by querying the current state of the bus and the states of other modules in the system. In the centralized arbitration mode, all the master devices occupy bus resources through a separate arbitration device. Because the arbitration speed of distributed arbitration is relatively slow and the hardware circuit is complex, most of the current systems on chip adopt a centralized arbitration mode.
In the centralized arbitration scheme, the arbitration policy has a very important impact on system performance. The arbitration policy refers to the specific arbitration algorithm employed by the system. In the running process of the SoC system, according to the control of the main equipment on the arbitration process, the arbitration algorithm is divided into a dynamic arbitration algorithm and a static arbitration algorithm. In a system of a dynamic arbitration algorithm, a master device can dynamically adjust the arbitration algorithm and the occupation size of bandwidth according to the running state of the system, while in a system of a static arbitration algorithm, the arbitration process is not influenced by the state of the master device.
Besides adopting the scheme of the multipath selector for APB arbitration to schedule bus resources, the method of network on chip (NoC) can be adopted to realize arbitration, the NoC adopts a packet switching and layering method to realize separation of a processing unit and a communication structure, and the NoC is mainly used for the communication structure of large-scale multi-core SoC design at present, and needs to carry out authorization and various parameter configuration, so that the circuit complexity is higher, and the chip realization cost is higher. While employing this approach in small circuit designs or simple bus interconnects (e.g., APB buses) increases circuit complexity and chip development costs.
In summary, in order to solve the above technical problems, improve bus arbitration efficiency, and efficiently complete bus transmission, the embodiments of the present application provide a bus arbiter, which uses a read arbitration module and a write arbitration module that support multi-path arbitration to form an arbitration unit, so as to simultaneously arbitrate requests of multi-path master devices, and further improve arbitration efficiency through a read-write arbitration separation design.
First, it should be noted that the bus arbiter provided in the present application may be used for APB protocol arbitration and may also be used for AHB bus arbitration, where AHB (Advanced High Performance Bus) is an advanced high-performance bus, and may provide a high-bandwidth bus interface between modules for large data transmission. That is, the bus arbiter provided in the present application may be applied to other AMBA bus structures such as an AHB, for example, the current state of the AHB transmission is determined according to the control signal in the AHB bus, and if the AHB transmission is in the address phase, the bus request is sent. For specific application fields, the application is not limited in particular, and the following embodiments are all described by taking APB bus arbitration as an example.
The APB bus is an advanced peripheral bus, and is mainly used for connection between low-bandwidth peripheral peripherals, for example, a universal asynchronous receiver/transmitter (Universal Asynchronous Receiver Transmitter, abbreviated as UART), a two-wire serial bus (Inter-Integrated Circuit, abbreviated as I2C), and the like, and the main device of the APB bus is an APB bridge.
Fig. 2 is a schematic diagram of an APB bus state transition provided in the embodiment of the present application, in APB bus transmission, as shown in fig. 2, IDLE is a default state of the APB bus, when transmission is required, the APB bus moves to a SETUP state, in which a proper selection signal PSEL is asserted, the bus maintains the SETUP state for only one clock period, and always moves to an ACCESS state, in which a PENABLE signal is asserted, and in the transition process from the SETUP state to the ACCESS state, address writing, address selection, data writing signals and the like must remain stable.
Fig. 3 (a) is a timing chart of APB bus read and transfer provided in this embodiment, as shown in fig. 3 (a), where the timing chart shows a change condition of signals such as left PCLK and the like in different clock cycles, the PCLK signal is flipped once in each clock cycle, the PRESETn signal is pulled high at time T1, the PWRITE signal is low after time T1, the PREADY signal is pulled high after time T2 and after time T4, and the PREADY signal is pulled low for 2 clock cycles for waiting read and transfer. Fig. 3 (b) is a timing chart of APB bus write transfer provided in the embodiment of the present application, as shown in fig. 3 (b), in which the PREADY signal is high for a wait-free write transfer period T2.
FIG. 4 is a block diagram of a bus arbiter according to an embodiment of the present application, as shown in FIG. 4, the system includes: the system comprises an arbitration unit 1 and a processing unit 2, wherein the output end of the arbitration unit 1 is connected with the processing unit 2, the input end of the arbitration unit 1 is connected with each main device, after the arbitration unit 1 determines that a request instruction sent by each main device is received, the request of each main device is arbitrated based on a preset arbitration algorithm to obtain an arbitration result, and the arbitration result is transmitted to the processing unit 2. The processing unit 2 is connected with the slave device, and is configured to send a corresponding operation instruction to the slave device according to the arbitration result after receiving the arbitration result.
As shown in fig. 4, the arbitration unit 1 includes a read arbitration module 3 and a write arbitration module 4 that support multi-path arbitration, and a logic operation module 5, in implementation, the logic operation module 5 analyzes a request instruction sent by each master device, and maintains a flag register according to the analysis result, where the read arbitration module 3 and the write arbitration module 4 determine whether to perform arbitration of bus resources according to information in the flag register in the logic operation module 5.
In implementation, the flag register 1 maintained by the logic operation module 5 represents that there is an unfinished read request or write request for the corresponding master device, and the corresponding bit is cleared after the transmission is finished. Therefore, the read arbitration module 3 and the write arbitration module 4 monitor the flag registers output by the logic operation module 5, if the flag registers are not all 0, read request arbitration or write request arbitration is started, and during arbitration, the 32-bit flag registers are compared with the previous arbitration result to realize the output of the arbitration result in one clock cycle.
The arbitration algorithm may be implemented by a fair polling algorithm or other algorithms through configuration selection signals, for example, a fixed priority algorithm may also be used, that is, a bus master with more frequent access request initiation is set to a higher priority and a bus master with occasional access is set to a lower priority when configured by default. When a plurality of bus master devices all initiate bus requests, arbitration is performed according to a fixed priority order, and the lowest priority is highest during initialization. The arbitration algorithms selected by the read arbitration module 3 and the write arbitration module 4 may be set according to actual service requirements, for example, when the service requirements need to pay special attention to a certain master device, the priorities thereof may be set in a self-defined manner, which is not particularly limited in this application. The processing unit 2 comprises a read address distribution module 6, a write buffer module 7, a read-write ping-pong operation module 8, a read data distribution module 9 and a response distribution module 10, wherein the read address distribution module 6 sequentially gates the main equipment addresses of the obtaining means according to the arbitration result sequence of the read arbitration module 3 in the arbitration unit 1, and generates corresponding read operation requests. The write buffer module 7 sequentially stores the write address and write data information of each master device according to the arbitration result sequence of the write arbitration module 4, and generates a corresponding write operation request.
The read address distribution module 6 and the write buffer module 7 send the generated read operation request and write operation request to the read-write ping-pong operation module 8, at this time, the read-write ping-pong operation module 8 sends a corresponding operation instruction to the slave device according to the ping-pong operation policy, and transmits the returned data to the read data distribution module 9.
The read data distribution module 9 gates the return data to the corresponding master, i.e., notifies the corresponding master that the transmission request is completed, according to the latched arbitration result of the read arbitration module 3, and sends a first status control instruction to the response distribution module 10.
The response distribution module 10 is configured to obtain the second state control instruction and the first state control instruction sent by the write arbitration module 4, and set a transmission state of the corresponding master device according to the first state control instruction or the second state control instruction.
It should be noted that, in the read arbitration module 3 and the write arbitration module 4, different arbitration policies may be set according to different service requirements, for example, fair polling, weighted arbitration, fixed priority, and the like, which is not limited in this application. Since the request priority of each arbitration of the fair polling algorithm is dynamically changed and fair, the fair polling algorithm is preferably used in the embodiments of the present application.
In addition, it should be noted that, in the embodiment of the present application, the bus arbiter provided by the present application may implement parameterized configuration, and in a specific implementation, the read arbitration module 3 and the write arbitration module 4 are generally modules supporting 2-32 ways of arbitration, so when the number of the masters does not exceed 32, as shown in fig. 4, the masters are connected with the logic operation module 5, so that the common arbitration of the masters can be implemented, that is, when the number of the masters does not exceed 32, the bus resource priority arbitration of the masters can be implemented by using only one bus arbiter provided by the embodiment of the present application.
However, when the number of masters exceeds 32, arbitration for any number of APB bus masters can be achieved in parallel by the bus arbiter provided in the present application. Fig. 5 is a block diagram of another bus arbiter according to an embodiment of the present application, for example, when the number of master devices is 64, and two-stage two-way circuits are used in the prior art, 63 arbiters are needed to perform 6-stage arbitration. However, as shown in fig. 5, the embodiment of the application only needs 3 arbiters to perform 2-level arbitration, so that the number of cascade connections is reduced, and the probability of occurrence of problems such as time sequence and interference is improved. The interface from the master device with the sequence number 1 to the master device with the sequence number 32 passes through the arbiter with the sequence number 1 to obtain a temporary result 1, the interface from the master device with the sequence number 33 to the master device with the sequence number 64 passes through the arbiter with the sequence number 2 to obtain a temporary result 2, the temporary result 1 and the temporary result 2 pass through the arbiter with the sequence number 3 to obtain a final arbitration result, and the final arbitration result directly accesses the APB slave device on the APB bus space.
The bus arbiter provided by the embodiment of the application comprises the following components: the system comprises an arbitration unit and a processing unit, wherein the arbitration unit comprises a read arbitration module and a write arbitration module which support multi-path arbitration, the output end of the arbitration unit is connected with the processing unit, the input end of the arbitration unit is connected with each main device, the arbitration unit arbitrates the request of each main device based on a preset arbitration algorithm to obtain an arbitration result after determining that the request instruction sent by each main device is received, and the arbitration result is transmitted to the processing unit. The processing unit is also connected with the slave device and is used for sending a corresponding operation instruction to the slave device according to the arbitration result after receiving the arbitration result. Therefore, according to the technical scheme provided by the application, the read arbitration module and the write arbitration module supporting multi-path arbitration form an arbitration unit, so that parallel arbitration of read-write requests is realized in order to improve arbitration efficiency besides simultaneously arbitrating requests of a plurality of main devices, namely, the separation design of read-write arbitration can further improve arbitration efficiency, further realize high-efficiency completion of bus transmission, and improve system reliability.
In a specific embodiment, the arbitration unit includes a logic operation module in addition to a read arbitration module and a write arbitration module. As shown in fig. 4, the input end of the logic operation module is used as the input end of the arbitration unit, and the output end is respectively connected with the read arbitration module and the write arbitration module, and is used for analyzing the request instruction of the main equipment, and maintaining the flag register according to the analysis result, so that the read arbitration module and the write arbitration module determine whether to perform president according to the flag register.
And the logic operation module judges whether an APB transmission request exists according to the PSEL signal and the PENABLE signal in the APB transmission process, and if the APB transmission is in a SETUP stage, the logic operation module sends a bus arbitration request to the read arbitration module or the write arbitration module. In practice, the logic operation module maintains two 32-bit flag registers, a read request flag register and a write request flag register, respectively. A position of 1 in the flag register represents that an unfinished read request or write request exists in the corresponding master device, and after the read arbitration module or the write arbitration module arbitrates and finishes transmission, the corresponding bit is cleared.
Therefore, the read arbitration module can judge whether to perform priority arbitration of bus resources according to whether all the read request flag registers are 0, can realize output of arbitration results in one clock period, and can start next arbitration after receiving the read operation completion instruction transmitted by the read data distribution module.
Similarly, the write arbitration module judges whether to perform priority arbitration of the bus resource according to whether all the write request flag registers are 0, and realizes output of arbitration results in one clock cycle. The write arbitration module transmits the arbitration result corresponding to the write control, write address, write data information and the like of the master device to the write cache module, and simultaneously informs the response distribution module to immediately pull up the PREADY signal of the corresponding master device, and if the write cache module is not full, the next arbitration is started. Wherein, as shown in fig. 2, the pull-up PREADY signal indicates that the slave device has completed writing data transfer, and can jump to other states. If there is still data transmission, the state is directly jumped to the SETUP state, and if there is no data transmission, the state is directly jumped back to the IDLE state. If the write cache module is not full, starting the next arbitration.
According to the bus arbiter provided by the embodiment of the application, the logic operation module for maintaining the read request mark register and the write request mark register is arranged in the arbitration unit, so that the read arbitration module and the write arbitration module determine whether to perform bus request arbitration according to the mark register, and therefore independent arbitration is performed on the read request operation and the write request operation, and arbitration efficiency is improved.
As shown in fig. 4, in the bus arbiter provided by the present application, the processing unit includes a read address distribution module and a write buffer module, where an input end of the read address distribution module is connected to an output end of the read arbitration module, and the read address distribution module is configured to sequentially gate a master device address of an obtaining means according to an arbitration result sequence of the read arbitration module, and generate a corresponding read operation request. The input end of the write buffer module is connected with the output end of the write arbitration module, and is used for sequentially temporarily storing the write address and the write data information of each main device according to the arbitration result sequence of the write arbitration module and generating a corresponding write operation request.
In practice, a multiplexer is implemented in the read address distribution module, and its output is connected to the read-write ping-pong operation module. The function of the module is to gate the address of the master device which obtains arbitration authorization from the address lines of all the master devices with read requests according to the arbitration result of the read arbitration module, so that the master device outputs from the multiplexer.
And the write buffer module maintains a buffer with the width of 64 bits and the depth of which is configurable, temporarily stores the 32bit write address and the 32bit write data information of the main equipment according to the arbitration result sequence of the write arbitration module, and when the buffer is not empty, the write buffer module sequentially transmits the 64bit write address and the write data information to the read-write ping-pong operation module. The cache depth may be set to 4, 8, 16, or 32 groups depending on the delay required for actual reading and writing. It can be understood that the buffer module is used for temporarily storing multiple sets of data transmitted by the main device, for example, 4 sets of write addresses and 4 sets of write data information can be stored, and the buffer depth can be selected according to the actual requirement of the user, which is not particularly limited in this application.
According to the bus arbiter provided by the embodiment of the application, the read address distribution module and the write buffer module respectively process arbitration results of the read arbitration module and the write arbitration module, and the overall arbitration efficiency is further improved through the independent processing design.
In implementation, as shown in fig. 4, the processing unit further includes a read-write ping-pong operation module, where an input end of the read-write ping-pong operation module is connected to an output end of the read address distribution module and an output end of the write cache module, and an output end of the read-write ping-pong operation module is connected to the slave device, and is configured to send a corresponding operation instruction to the slave device according to a ping-pong operation policy after obtaining the read operation request and the write operation request.
In implementation, the read-write ping-pong operation module receives operation requests from the read address distribution module and the write cache module respectively, and sends an APB bus signal to the slave device according to a ping-pong operation strategy. It should be noted that, the ping-pong operation policy refers to that if a read operation request is sent last time, a write operation request is currently sent, and if a write operation request is sent last time, a read operation request is currently sent.
In particular, the ping-pong operation module compares address information of simultaneous read-write requests, if the address information points to the same address, write data sent by the write cache module is directly transmitted to the read data distribution module, APB read operation is not sent to the slave device any more, and only APB write operation is sent. If the read operation is sent, when the read data is returned from the equipment, the read-write ping-pong operation module transmits the returned data to the read data distribution module.
According to the bus arbiter provided by the embodiment of the application, the ping pong operation strategy of the read-write ping pong operation module is used for sending the APB bus signal to the slave equipment so as to realize arbitration of bus resources, meanwhile, address information of the read-write request is compared, and when the address information is the same, write data sent by the write cache module is transmitted to the read data distribution module, so that arbitration efficiency is further improved.
Further, as shown in fig. 4, the processing unit further includes a read data distribution module and a response distribution module, where an input end of the read data distribution module is connected to an output end of the read data distribution module, and an output end of the read data distribution module is respectively connected to an input end of the response distribution module, an input end of the read arbitration module, and each master device, and is configured to latch an arbitration result of the read arbitration module, and when receiving data returned by the read/write ping-pong operation module, gate the returned data to the corresponding master device according to the latched arbitration result, and simultaneously send a first state control instruction to the response distribution module.
Specifically, the read data distribution module maintains a read data multiplexer to each master device, latches the arbitration result of the read arbitration module, and when the read/write ping-pong operation module returns read data, gates the data onto the data line of the corresponding master device according to the arbitration result, and simultaneously notifies the response distribution module to set the PREADY signal of the corresponding master device.
As shown in fig. 4, the input end of the response distribution module is connected with the output end of the write arbitration module, and the output end of the response distribution module is connected with each master device, so as to obtain the second state control instruction and the first state control instruction sent by the write arbitration module, and set the transmission state of the corresponding master device according to the first state control instruction or the second state control instruction. That is, the response distribution module is responsible for receiving the indications from the write arbitration module and the read data distribution module, asserting the PREADY signal of the response master, and maintaining one clock cycle.
The bus arbiter provided by the embodiment of the application informs the master device whether the current transmission is finished or not through the read data distribution module, and sets the corresponding transmission state based on the instruction sent by the response distribution module so as to conveniently finish the arbitration of the arbiter.
In the above embodiments, the bus arbiter is described in detail, and the present application further provides a corresponding embodiment of a method for bus arbitration. Fig. 6 is a flowchart of a method for bus arbitration according to an embodiment of the present application, as shown in fig. 6, where the method includes:
s10: after determining that the request instruction sent by the main equipment is received, carrying out arbitration on the request of each main equipment based on a preset arbitration algorithm to obtain an arbitration result;
s11: and transmitting the arbitration result to the processing unit so that the processing unit can send the corresponding operation instruction to the slave device according to the arbitration result.
Since the specific arbitration process of the arbiter has been described in detail in the above embodiments, the bus arbitration method provided in the embodiments of the present application corresponds to the specific arbitration process of the arbiter in the above embodiments, and thus is not described herein again.
The period of APB bus transfer is determined by the PREADY signal whether or not there is a waiting period, and if the PREADY signal is high, no waiting transfer is performed, whereas if the PREADY signal is low, a waiting transfer is performed.
Fig. 7 (a) shows a write transmission timing sequence of an APB no-wait state provided in this embodiment of the present application, as shown in fig. 7 (a), the master device 1 initiates a write transmission request in a period T1, the master device 1 normally enters an ENABLE state, the arbiter transmits address Addr1 and Data1 information of the master device 1 to the APB bus, the period T2 enters an ACCESS state, and APB write operations.
Fig. 7 (b) is a read transmission sequence of an APB waiting state provided in the embodiment of the present application, as shown in fig. 7 (b), the master device 1 initiates a read transmission request in a period T1, and the master device 1 normally enters an ENABLE state. At this time, the response signal pready_i returned from the apparatus 1 is low, and enters a waiting state. Until the T3 cycle transmission request is allowed to be executed, the arbiter initiates transmission on the bus to transmit the Data information Data1 of the master 1 to the bus. The number of clock cycles waiting for the state is determined by the PREADY _ i signal given by the slave device.
Based on the bus arbitration method provided by the embodiment of the application, the transmission request of the master device with the highest bus arbitration priority is directly responded, the transmission and the reading of other master devices can stay in the ENABLE state, and the transmission is carried out when the back pressure signal of the data of the arbiter allows the transmission. The write information of other main equipment can be temporarily stored in a write cache module, and write response is returned to the response information of the main equipment. Therefore, n master devices always have access rights to the bus, can initiate transmission requests at any time and can normally execute and complete the transmission requests, and the switching of the bus ownership is realized without additional operation, namely, MUX is not required to be controlled through system configuration or a chip external selection signal, thereby realizing the control of the access rights of the AAPB master devices and reducing the complexity of bus space access.
For ease of understanding, the following will exemplify, for example, that the priority of the lower master is higher than that of the higher master by default, assuming that masters 1, 2, 3 and 4 numbered master 2, 3 and 4 initiate bus requests simultaneously. The logic operation judges that the master 1 and the master 2 request the read operation, the master 3 and the master 4 request the write operation, and the read arbitration module arbitrates that the priority order is that the master 1 is higher than the master 2, and the write arbitration module arbitrates that the priority order is that the master 3 is higher than the master 4.
The write response module sends write response signals to the master 3 and the master 4 according to the write arbitration module result. The write buffer module sequentially writes the write addresses and write data information of the main device 3 and the main device 4 according to the result of the write arbitration module, and the read address distribution module transmits the addresses of the main device 1 and the main device 2 according to the result of the read arbitration module.
The read-write ping-pong operation module sequentially performs address information transmission and read response distribution of the main device 1, write address and write data information transmission of the main device 3, address information transmission and read response distribution of the main device 2, and write address and write data information transmission of the main device 4. The operation sequence may be that the write address and write data information of the master device 3 are sequentially transmitted, the address information of the master device 1 is transmitted, and the read response is distributed, the write address and write data information of the master device 4 is transmitted, and the address information of the master device 2 is transmitted, and the read response is distributed, which is not limited in this application.
Fig. 8 is a timing chart of arbitration transmission provided in the embodiment of the present application, and for the above-mentioned example, as shown in fig. 8, in the period T1, the master 1 and the master 2 request a read operation, and the master 3 and the master 4 request a write operation. The arbitration unit determines that the master 1 and the master 2 request a read operation and the master 3 and the master 4 request a write operation. And the read arbitration module Zhong Caichu reads higher priority orders for master 1 than master 2, and the write arbitration module Zhong Caichu writes higher priority orders for master 3 than master 4.
In the period T2, the master 1 enters the APB transmission ACCESS phase, at this time, the preday_i is low and enters the waiting state, in the period T3, the master 1 enters the APB transmission ACCESS phase, at this time, preday_i is high, the read operation of the master 1 is completed, the slave returns the read response signal predy_o1 to be high, in the period T4, the ACCESS transmission of the master 3 is completed, in the period T6, the ACCESS transmission of the master 2 is completed, and in the period T7, the ACCESS transmission of the master 4 is completed.
The method for bus arbitration provided in the embodiment of the present application is applied to the bus arbiter in the above embodiment, and includes: after the request instruction sent by the master device is determined to be received, the request of each master device is arbitrated based on a preset arbitration algorithm to obtain an arbitration result, and the arbitration result is transmitted to the processing unit, so that the processing unit sends a corresponding operation instruction to the slave device according to the arbitration result. Therefore, according to the technical scheme provided by the application, the read arbitration module and the write arbitration module supporting multi-path arbitration form an arbitration unit, so that parallel arbitration of read-write requests is realized in order to improve arbitration efficiency besides simultaneously arbitrating requests of a plurality of main devices, namely, the separation design of read-write arbitration can further improve arbitration efficiency, further realize high-efficiency completion of bus transmission and improve system reliability.
In the above embodiments, the method for bus arbitration is described in detail, and the present application further provides a corresponding embodiment of an apparatus for bus arbitration. It should be noted that the present application describes an embodiment of the device portion from two angles, one based on the angle of the functional module and the other based on the angle of the hardware structure.
Fig. 9 is a block diagram of an apparatus for bus arbitration according to an embodiment of the present application, as shown in fig. 9, where the apparatus includes:
the arbitration module 10 is configured to arbitrate the requests of the master devices based on a preset arbitration algorithm to obtain an arbitration result after determining whether the request instruction sent by the master device is received;
the transmission module 11 is configured to transmit the arbitration result to the processing unit, so that the processing unit sends the corresponding operation instruction to the slave device according to the arbitration result.
Since the embodiments of the apparatus portion and the embodiments of the method portion correspond to each other, the embodiments of the apparatus portion are referred to the description of the embodiments of the method portion, and are not repeated herein.
The device for bus arbitration provided in the embodiment of the present application is applied to the bus arbiter in the above embodiment, and includes: after the request instruction sent by the master device is determined to be received, the request of each master device is arbitrated based on a preset arbitration algorithm to obtain an arbitration result, and the arbitration result is transmitted to the processing unit, so that the processing unit sends a corresponding operation instruction to the slave device according to the arbitration result. Therefore, according to the technical scheme provided by the application, the read arbitration module and the write arbitration module supporting multi-path arbitration form an arbitration unit, so that parallel arbitration of read-write requests is realized in order to improve arbitration efficiency besides simultaneously arbitrating requests of a plurality of main devices, namely, the separation design of read-write arbitration can further improve arbitration efficiency, further realize high-efficiency completion of bus transmission and improve system reliability.
Fig. 10 is a block diagram of an apparatus for bus arbitration according to another embodiment of the present application, and as shown in fig. 10, the apparatus for bus arbitration includes: a memory 20 for storing a computer program;
a processor 21 for implementing the steps of the method of bus arbitration as mentioned in the above embodiments when executing a computer program.
The bus arbitration device provided in this embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, or the like.
Processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 may be implemented in hardware in at least one of a digital signal processor (Digital Signal Processor, abbreviated as DSP), a Field programmable gate array (Field-Programmable Gate Array, abbreviated as FPGA), and a programmable logic array (Programmable Logic Array, abbreviated as PLA). The processor 21 may also include a main processor and a coprocessor, the main processor being a processor for processing data in an awake state, also referred to as a central processor (Central Processing Unit, CPU for short); a coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 21 may be integrated with an image processor (Graphics Processing Unit, GPU for short) for rendering and drawing of content required to be displayed by the display screen. In some embodiments, the processor 21 may also include an artificial intelligence (Artificial Intelligence, AI) processor for processing computing operations related to machine learning.
Memory 20 may include one or more computer-readable storage media, which may be non-transitory. Memory 20 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 20 is at least used for storing a computer program 201, which, when loaded and executed by the processor 21, is capable of implementing the relevant steps of the method of bus arbitration disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may further include an operating system 202, data 203, and the like, where the storage manner may be transient storage or permanent storage. The operating system 202 may include Windows, unix, linux, among others. The data 203 may include, but is not limited to, related data involved in the method of bus arbitration, and the like.
In some embodiments, the bus arbitrating device may further include a display 22, an input/output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.
Those skilled in the art will appreciate that the structure shown in fig. 10 is not limiting of the apparatus for bus arbitration and may include more or fewer components than shown.
The bus arbitration device provided by the embodiment of the application comprises a memory and a processor, wherein the processor can realize the following method when executing a program stored in the memory: a bus arbitration method.
According to the bus arbitration device, the arbitration unit is formed by the read arbitration module and the write arbitration module which support multi-path arbitration, so that parallel arbitration of read-write requests is realized in order to improve arbitration efficiency besides simultaneously arbitrating requests of a plurality of main devices, namely, the separation design of read-write arbitration can further improve arbitration efficiency, further high-efficiency bus transmission is achieved, and system reliability is improved.
Finally, the present application also provides a corresponding embodiment of the computer readable storage medium. The computer-readable storage medium has stored thereon a computer program which, when executed by a processor, performs the steps as described in the method embodiments above.
It will be appreciated that the methods of the above embodiments, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored on a computer readable storage medium. With such understanding, the technical solution of the present application, or a part contributing to the prior art or all or part of the technical solution, may be embodied in the form of a software product stored in a storage medium, performing all or part of the steps of the method described in the various embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The above describes in detail a bus arbiter, a method, an apparatus and a medium for bus arbitration. In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section. It should be noted that it would be obvious to those skilled in the art that various improvements and modifications can be made to the present application without departing from the principles of the present application, and such improvements and modifications fall within the scope of the claims of the present application.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. A bus arbiter, comprising: an arbitration unit and a processing unit;
the arbitration unit comprises a read arbitration module and a write arbitration module which support multi-path arbitration, the output end of the arbitration unit is connected with the processing unit, and the input end of the arbitration unit is connected with each main device;
after determining that the request instruction sent by each main device is received, the arbitration unit arbitrates the request of each main device based on a preset arbitration algorithm to obtain an arbitration result, and transmits the arbitration result to the processing unit;
the processing unit is connected with the slave device and is used for sending a corresponding operation instruction to the slave device according to the arbitration result after receiving the arbitration result.
2. The bus arbiter of claim 1, wherein the arbitration unit further comprises a logic operation module;
the input end of the logic operation module is used as the input end of the arbitration unit, the output end of the logic operation module is respectively connected with the read arbitration module and the write arbitration module and is used for analyzing the request instruction of the main equipment, and a mark register is maintained according to the analysis result so that the read arbitration module and the write arbitration module can determine whether the request instruction of the main equipment is received or not according to the mark register.
3. The bus arbiter of claim 2, wherein the processing unit comprises a read address distribution module and a write cache module;
the input end of the read address distribution module is connected with the output end of the read arbitration module, and is used for sequentially gating and obtaining authorized main equipment addresses according to the arbitration result sequence of the read arbitration module and generating corresponding read operation requests;
the input end of the write buffer module is connected with the output end of the write arbitration module, and is used for sequentially temporarily storing the write address and write data information of each main device according to the arbitration result sequence of the write arbitration module, and generating a corresponding write operation request.
4. The bus arbiter of claim 3, wherein the processing unit further comprises a read-write ping-pong operation module;
the input end of the read-write ping-pong operation module is respectively connected with the output end of the read address distribution module and the output end of the write cache module, and the output end of the read-write ping-pong operation module is connected with the slave device and is used for sending a corresponding operation instruction to the slave device according to a ping-pong operation strategy after the read operation request and the write operation request are acquired.
5. The bus arbiter of claim 4, wherein the processing unit further comprises a read data distribution module and a response distribution module;
the input end of the read data distribution module is connected with the output end of the read-write ping-pong operation module, the output end of the read data distribution module is respectively connected with the input end of the response distribution module, the input end of the read arbitration module and each main device are connected, and the read data distribution module is used for latching the arbitration result of the read arbitration module, and when receiving the data returned by the read-write ping-pong operation module, the read data distribution module is used for gating the returned data to the corresponding main device according to the latched arbitration result and simultaneously sending a first state control instruction to the response distribution module;
the input end of the response distribution module is connected with the output end of the write arbitration module, and the output end of the response distribution module is connected with each main device and is used for acquiring the second state control instruction and the first state control instruction sent by the write arbitration module and setting the transmission state of the corresponding main device according to the first state control instruction or the second state control instruction.
6. The bus arbiter of claim 5, wherein the ping-pong policy is to send a write request currently if a read request was sent last, and send a read request currently if a write request was sent last; and if the read operation request and the slave equipment address information corresponding to the write operation request are the same, transmitting data corresponding to the write operation request to the read data distribution module.
7. A method of bus arbitration as claimed in any one of claims 1 to 6, comprising:
determining whether a request instruction sent by the main equipment is received;
if yes, carrying out arbitration on the requests of the master devices based on a preset arbitration algorithm to obtain an arbitration result;
and transmitting the arbitration result to a processing unit so that the processing unit can conveniently transmit a corresponding operation instruction to the slave device according to the arbitration result.
8. An apparatus for bus arbitration, applied to the bus arbiter of any one of claims 1 to 6, comprising:
the determining module is used for determining whether a request instruction sent by the main equipment is received, and if yes, the arbitration module is called;
the arbitration module is used for arbitrating the requests of the master devices based on a preset arbitration algorithm to obtain arbitration results;
and the transmission module is used for transmitting the arbitration result to the processing unit so that the processing unit can conveniently transmit a corresponding operation instruction to the slave device according to the arbitration result.
9. An apparatus for bus arbitration, comprising a memory for storing a computer program;
A processor for implementing the steps of the method of bus arbitration as recited in claim 7 when executing the computer program.
10. A computer readable storage medium, characterized in that it has stored thereon a computer program which, when executed by a processor, implements the steps of the method of bus arbitration according to claim 7.
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| CN202310109420.2A CN116028413A (en) | 2023-02-10 | 2023-02-10 | Bus arbiter, bus arbitration method, device and medium |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116961761A (en) * | 2023-09-21 | 2023-10-27 | 厦门优迅高速芯片有限公司 | Hardware arbitration circuit and method applied to optical fiber transceiver |
| CN117009266A (en) * | 2023-10-07 | 2023-11-07 | 芯动微电子科技(武汉)有限公司 | Handshake protocol bus arbitration module and system on chip |
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2023
- 2023-02-10 CN CN202310109420.2A patent/CN116028413A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116961761A (en) * | 2023-09-21 | 2023-10-27 | 厦门优迅高速芯片有限公司 | Hardware arbitration circuit and method applied to optical fiber transceiver |
| CN116961761B (en) * | 2023-09-21 | 2024-01-23 | 厦门优迅高速芯片有限公司 | Hardware arbitration circuit and method applied to optical fiber transceiver |
| CN117009266A (en) * | 2023-10-07 | 2023-11-07 | 芯动微电子科技(武汉)有限公司 | Handshake protocol bus arbitration module and system on chip |
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