CN115811371B

CN115811371B - Threshold programmable loss of signal detection circuit with temperature and process compensation

Info

Publication number: CN115811371B
Application number: CN202211574623.0A
Authority: CN
Inventors: 李景虎; 陈德焱; 吴阳吉; 陈福洁; 熊守芬; 林其芃
Original assignee: Xiamen EOchip Semiconductor Co Ltd
Current assignee: Xiamen EOchip Semiconductor Co Ltd
Priority date: 2022-12-08
Filing date: 2022-12-08
Publication date: 2023-09-05
Anticipated expiration: 2042-12-08
Also published as: CN115811371A

Abstract

The invention discloses a programmable threshold signal LOSs detection circuit with temperature and process compensation, belongs to the field of optical communication, and aims to solve the problems that the threshold of a traditional LOS circuit is fixed, the requirement of a new circuit system cannot be met, the LOS circuit must be redesigned, and the design cost of the circuit is further increased. The invention comprises a pre-operational amplifier, a peak value detection circuit, a comparator and a bias current source; the bias current source is used for providing bias current related to temperature and compensating the LOS circuit temperature; the front-end operational amplifier adjusts the amplitude of an input signal of the optical receiver; the peak detection circuit is used for detecting the peak value of the signal after the adjustment of the AMP; the comparator is used for judging whether the amplitude of the input signal reaches the threshold value of the LOS circuit or not; the pre-operational amplifier and the peak detection circuit are both provided with a threshold control port TH <3:0>, and the gain of the pre-operational amplifier and the threshold resistance of the peak detection circuit are adjusted by inputting a four-bit binary coding instruction to the threshold control port so as to realize the threshold programming of the LOS circuit.

Description

Threshold programmable loss of signal detection circuit with temperature and process compensation

Technical Field

The invention relates to a signal loss detection circuit for a receiving end in an optical communication system, belonging to the field of optical communication.

Background

Optical communication technology is widely applied to the fields of the internet, data centers and the like due to high speed, low loss and large information carrying quantity. The optical receiver is the most important component of an optical communication system, and is used to receive an optical signal in an optical fiber and convert it into a digital signal again. And a Limiting Amplifier (LA) is an integral part of the optical receiver. When an input optical signal is received by a Photodiode (PD) in an optical receiver, a current is generated, which is converted into a voltage signal by a transimpedance amplifier (TIA). Since the TIA needs to be considered between noise, bandwidth and gain, the gain of a typical TIA will not be very high, and thus the output signal amplitude of a typical TIA is tens of millivolts. However, clock and Data Recovery (CDR) circuits in optical receivers require the amplitude of the input signal to be on the order of hundreds of millivolts, so a LA needs to be added between TIA and CDR.

LA in an optical receiver has a very high gain and can amplify the signal from TIA to the extent required by CDR. Meanwhile, LA has a clipping function, and when the amplitude of a signal from TIA is too large, LA can reduce the gain so that the amplitude of an output signal is kept at a stable value. However, when the amplitude of the signal from the TIA is too small, the LA has no way to increase the gain, and the too small signal still does not meet the CDR requirements after passing through the LA, so that the whole optical receiver may generate an erroneous output. Therefore, when the amplitude of the signal from the TIA is too small, an additional circuit is required to output a signal to the outside, indicating that the signal received in the optical receiver circuit at this time is too small, the output thereof is not trusted, and the subsequent circuit is controlled to stop operating. A circuit for monitoring the intensity of an optical Signal received in an optical receiver is called a LOSs of Signal (LOS) detection circuit.

A LOSs of signal detection circuit (LOS) is located in a limiting amplifier at the receiving end of the optical communication for monitoring the amplitude of the input signal of the current system. When the amplitude of the input signal is lower than the LOS threshold value, the LOS circuit judges that the signal is lost, and the system controls the subsequent circuits to stop working so as to save power consumption and reduce the error rate of the system. A conventional LOS circuit is described below in conjunction with fig. 1. The conventional LOS circuit is composed of an operational Amplifier (AMP) for amplifying an input signal, a Peak Detector for detecting a Peak value of the input signal, and a hysteresis comparator (Hysteresis Comparator) for judging whether the Peak value of the current input signal reaches a threshold value. Let it be the input signal V _IN Peak value V _peak The gain of AMP is A _V The peak value of the output signal of AMP is A _V V _peak . Suppose that when the output signal of AMP is high level, Q ₁ Can be fully conductedWhen the output signal is low level, Q ₁ Fully closed, at this point, Q ₁ And conducting for half a period. Setting current I ₁ For flowing through bipolar transistor Q ₁ Average value of current, I _C Flows through Q when the input signal is high ₁ Instantaneous current (collector current) of (a) then there is I _C ＝2I ₁ . Peak Detector is a symmetrical circuit, so there is I ₁ ＝I ₂ . According to the base-emitter voltage (V) _BE ) Collector current (I) _C ) The relation between the two is:

the peak detection circuit output voltage can be obtained as:

V _PD -V _ref ＝A _V V _peak -V _T ln2-I ₁ R ₃

wherein I is _S Is the saturation current of the bipolar transistor, R ₃ Is the threshold resistance of the Peak Detector, V _T ln2 is the detection error of the Peak Detector in an ideal state, and in a non-ideal state, since the bipolar transistor in the Peak Detector is difficult to be fully turned on and off, the input signal is high, and flows through the bipolar transistor Q ₁ Transient current I of (2) _C Has I ₁ ＜I _C ＜2I ₁ At this time, the detection error of the Peak Detector isWhen V is _PD -V _ref When=0, the amplitude of the input signal of the LOS circuit at this time is the threshold value of the LOS circuit. The threshold of the LOS circuit can be expressed as:

when V is _PD -V _ref When > 0, the hysteresis comparator outputs a low level, representing V _{TH_LOS} ＜V _peak The LOS circuit considers that the current input signal amplitude meets the requirement of a circuit system; when V is _PD -V _ref When < 0, the hysteresis comparator outputs a high level, representing V _{TH_LOS} ＞V _peak The LOS circuit considers that the current signal amplitude cannot meet the requirements of the circuit system, sends out an alarm signal of signal LOSs, and controls the subsequent circuit to stop working.

Conventional LOS circuits are typically only specific to a particular circuitry, and the required threshold is typically a fixed value. However, today, in the case of integrated circuit design modularization, if the LOS circuit is still designed by using a conventional circuit design method, the threshold requirement of the LOS circuit may be changed whenever the circuit system is slightly changed, and the LOS circuit needs to be redesigned, so that the cost of the circuit design is greatly increased. It is therefore of great importance to design a threshold programmable LOS circuit. In addition, since the LOS circuit is susceptible to the influence of the process, the power supply voltage and the temperature, and the accuracy thereof is reduced, in order to accurately determine whether the amplitude of the input signal reaches the threshold value of the LOS circuit, the generation and compensation of the detection error of the LOS circuit are also very important.

Disclosure of Invention

Aiming at the problems that the threshold value of the traditional LOS circuit is fixed, the requirement of a new circuit system cannot be met, and the LOS circuit must be redesigned, so that the circuit design cost is increased, the invention provides a programmable threshold value signal LOSs detection circuit with temperature and process compensation.

The invention relates to a signal loss detection circuit with programmable threshold value and temperature and process compensation, which comprises a pre-operational amplifier AMP, a Peak detection circuit Peak Detector, a comparator COMP, a bias Current source IBias Current, a capacitor C1 and a capacitor C2;

the bias Current source IBias Current is used for providing bias Current IB which is dependent on temperature ₁ 、IB ₂ Bias current IB ₁ 、IB ₂ Respectively supplying a front-end operational Amplifier (AMP) and a Peak detection circuit (Peak Detector) to realize temperature compensation of an LOS circuit;

the pre-operational amplifier AMP is used for receiving an input signal of the optical receiver and adjusting the amplitude of the input signal of the optical receiver; the regulated signal output by the pre-operational amplifier AMP is coupled through the capacitors C1 and C2 and then output to the Peak detection circuit Peak Detector;

the Peak Detector is configured to detect a Peak value of the signal after AMP adjustment, and output a detected result to the comparator COMP;

The comparator COMP is configured to determine whether the amplitude of the input signal reaches a threshold of the LOS circuit, and output a determination result of whether the signal is lost;

the front operational amplifier AMP and the Peak detection circuit Peak Detector are both provided with a threshold control port TH <3:0>, the gain of the front operational amplifier AMP and the threshold resistance of the Peak detection circuit Peak Detector are adjusted by inputting a four-bit binary coding instruction to the threshold control port TH <3:0>, so that the threshold of the LOS circuit is programmable, and the output of the comparator COMP controls the bias current of the Peak detection circuit Peak Detector so as to realize fixed hysteresis.

Preferably, the pre-operational amplifier AMP comprises a Gain adjusting unit Gain-adjust, a bipolar transistor Q _a1 ～Q _a6 Resistance R _a1 ～R _a8 NMOS transistor M _a1 ～M _a7 An inductance L1 and an inductance L2;

the input end of the Gain-adjusting unit Gain-adjust is a threshold control port TH<3:0>The Gain adjusting unit Gain-adjust translates and outputs the input four-bit binary code instruction, the Gain adjusting unit Gain-adjust output terminal O _a1 ，O _a2 ，O _a3 The output state of (2) is: 001. 010 or 100; output terminal O _a1 ，O _a2 ，O _a3 Respectively connected with NMOS transistor M _a5 、M _a6 、M _a7 A gate electrode of (a);

one end of the inductor L1 and one end of the inductor L2 are connected with a power supply VDD;

the other end of the inductor L1 and the resistor R _a7 Is connected with one end of the connecting rod;

the other end of the inductor L2 and the resistor R _a8 Is connected with one end of the connecting rod;

resistor R _a7 The other end of the transistor (B) is connected with the same-direction output end OUTP of the operational amplifier AMP and the bipolar transistor Q _a1 Collector, bipolar transistor Q _a3 Collector and bipolar transistor Q of (2) _a5 Is connected with the collector of the capacitor;

resistor R _a8 The other end of the (A) and the inverted output end OUTN of the operational amplifier AMP, the bipolar transistor Q _a2 Collector, bipolar transistor Q _a4 Collector and bipolar transistor Q of (2) _a6 Is connected with the collector of the capacitor;

bipolar transistor Q _a1 Bipolar transistor Q _a3 Bipolar transistor Q _a5 The bases of the two are connected with the reverse input end INN of the operational amplifier AMP;

bipolar transistor Q _a2 Bipolar transistor Q _a4 Bipolar transistor Q _a6 The bases of the (a) are connected with the same-direction input end INP of the operational amplifier AMP;

bipolar transistor Q _a1 Emitter and resistor R of (2) _a1 Is connected with one end of the connecting rod;

bipolar transistor Q _a2 Emitter and resistor R of (2) _a2 Is connected with one end of the connecting rod;

bipolar transistor Q _a3 Emitter and resistor R of (2) _a3 Is connected with one end of the connecting rod;

bipolar transistor Q _a4 Emitter and resistor R of (2) _a4 Is connected with one end of the connecting rod;

bipolar transistor Q _a5 Emitter and resistor R of (2) _a5 Is connected with one end of the connecting rod;

bipolar transistor Q _a6 Emitter and resistor R of (2) _a6 Is connected with one end of the connecting rod;

resistor R _a1 Resistance R _a2 At the same time with NMOS transistor M _a5 Is connected with the drain electrode of the transistor;

resistor R _a3 Resistance R _a4 At the same time with NMOS transistor M _a6 Is connected with the drain electrode of the transistor;

resistor R _a5 Resistance R _a6 At the same time with NMOS transistor M _a7 Is connected with the drain electrode of the transistor;

NMOS transistor M _a5 Source of (d) and NMOS transistor M _a1 Is connected with the drain electrode of the transistor;

NMOS transistor M _a6 Source of (d) and NMOS transistor M _a2 Is connected with the drain electrode of the transistor;

NMOS transistor M _a7 Source of (d) and NMOS transistor M _a3 Is connected with the drain electrode of the transistor;

NMOS transistor M _a1 NMOS transistor M _a2 NMOS transistor M _a3 NMOS transistor M _a4 Gate of (d) and NMOS transistor M _a4 Is connected to the source of the bias current IB ₁ ；

NMOS transistor M _a1 NMOS transistor M _a2 NMOS transistor M _a3 NMOS transistor M _a4 The source of (c) is grounded.

Preferably, the four-bit binary code instruction is input by TH <3:0> to adjust the gain of the pre-op AMP is:

gain A of AMP _V The method comprises the following steps:

in the formula g _m Transconductance of bipolar transistor as conducting branch;

R _S is a source negative feedback resistor of a bipolar transistor in a conduction branch, and the negative feedback resistor R _a1 ～R _a6 Divided into three groups, resistor R _a1 And R is _a2 A group of resistors R _a3 And R is _a4 A group of resistors R _a5 And R is _a6 The resistance values of the two resistors in the group are equal, and the resistance values among the groups are unequal;

When O is _a1 ，O _a2 ，O _a3 Gain A of AMP when outputting different states _V The corresponding adjustment is as follows:

O _a1 ，O _a2 ，O _a3 ＝001，A _V ＝g _m R _a8 /(1+g _m R _a6 )；

O _a1 ，O _a2 ，O _a3 ＝010，A _V ＝g _m R _a8 /(1+g _m R _a4 )；

O _a1 ，O _a2 ，O _a3 ＝100，A _V ＝g _m R _a8 /(1+g _m R _a2 )。

preferably, the Peak Detector comprises a threshold resistance adjusting unit Res-adjust, a bipolar transistor Q _p1 ～Q _p4 Resistance R _p1 ～R _p20 NMOS transistor M _p0 NMOS transistor M _p1 ～M _p15 Capacitance C _p1 And capacitor C _p2 ；

The input end of the threshold resistance adjusting unit Res-adjust is a threshold control port TH<3:0>The threshold resistance adjusting unit Res-adjust translates and outputs the input four-bit binary coded instruction, and the threshold resistance adjusting unit Res-adjust eight output terminals O _p1 ～O _p8 Its output is high and active, O _p1 ～O _p8 At the same TH<3:0>Only one valid bit is output during input; output terminal O _p1 ～O _p8 Respectively connected with NMOS transistor M _p1 ～M _p8 A gate electrode of (a);

power supply VDD is simultaneously connected with bipolar transistor Q _p1 ～Q _p4 Is connected with the collector of the capacitor; bipolar transistor Q _p1 ～Q _p4 Respectively cross-over resistor R between base electrode of (C) and power supply VDD _p17 ～R _p20 The method comprises the steps of carrying out a first treatment on the surface of the Bipolar transistor Q _p1 、Q _p2 The bases of the (a) are respectively connected with the input ends VIN1 and VIN2 of the Peak detection circuit Peak Detector;

bipolar transistor Q _p1 Emitter, bipolar transistor Q of (2) _p2 Emitter of (a) and NMOS transistor M _p0 Is connected with the source electrode of the transistor;

NMOS transistor M _p0 NMOS transistor M _p1 ～M _p8 Drain electrode of (C) and capacitor (C) _p1 Is simultaneously connected with the amplitude voltage output terminal V of the Peak Detector _PD Are connected;

resistor R _p1 ～R _p8 In series in turn, resistance R _p1 One end is connected with NMOS transistor M _p0 Is connected with the source electrode of the resistor R _p1 ～R _p8 Respectively with NMOS transistor M _p1 ～M _p8 The sources of the electrodes are connected one by one;

NMOS transistor M _p12 Drain of NMOS transistor M _p9 Is simultaneously with the drain of NMOS transistor M _p8 Is connected with the source electrode of the transistor;

bipolar transistor Q _p3 Emitter, bipolar transistor Q of (2) _p4 Emitter, resistor R of (2) _p9 One end of (C) capacitor _p2 At the same time as the reference voltage output terminal V of the Peak Detector _ref Are connected;

resistor R _p9 ～R _p16 Sequentially connected in series;

resistor R _p16 At the same time with NMOS transistor M _p15 NMOS transistor M _p10 Is connected with the drain electrode of the transistor;

NMOS transistor M _p13 Drain of (d) and NMOS transistor M _p9 Is connected with the source electrode of the transistor;

NMOS transistor M _p14 Drain of (d) and NMOS transistor M _p10 Is connected with the source electrode of the transistor;

NMOS transistor M _p11 NMOS transistor M _p12 NMOS transistor M _p13 NMOS transistor M _p14 NMOS transistor M _p15 Is simultaneously with the gate of NMOS transistor M _p11 Is connected to the drain of the transistor and is connected to a bias current IB ₂ ；

NMOS transistor M _p11 NMOS transistor M _p12 NMOS transistor M _p13 NMOS transistor M _p14 NMOS transistor M _p15 Source of (C) and capacitor C _p1 Capacitance C _p2 The other end of the first electrode is grounded;

NMOS transistor M _p9 NMOS transistor M _p10 Gate of (c) and output end LOS of comparator COMP _out Are connected.

Preferably, the NMOS transistor M in the Peak Detector circuit Peak Detector _p11 ，M _p12 ，M _p13 ，M _p14 ，M _p15 Is a current mirror, M _p13 ，M _p14 Respectively with NMOS transistor M _p9 ，M _p10 Two additional current branches are formed;

the output voltage of the Peak Detector is

Wherein A is _V Gain of AMP, V _peak For peak value of AMP input signal, V _T Is thermal voltage, I _C Is a bipolar transistor Q _p1 And Q _p2 The sum of collector currents of I ₀ 、I ₁ 、I _HYS0 、I _HYS1 Is the tail current and has the relation I ₀ +I _HYS0 ＝I ₁ +I _HYS1 ；R _uar A threshold resistance which is a Peak Detector of the Peak detection circuit;

when the amplitude of the input signal is smaller than the threshold value of the LOS circuit, the NMOS transistor M is controlled _p9 ，M _p10 Conducting, at this time, the bias current is I ₀ +I _HYS0 And I ₁ +I _HYS1 When the input signal amplitude is greater than the threshold of the LOS circuit, the NMOS transistor M _p9 ，M _p10 Is not conductive, its bias current becomes I ₀ And I ₁ ，I ₀ ＝I ₁ ；

Threshold resistance R _var The magnitude of (2) is controlled and regulated by four-bit binary code input from outside, and the threshold resistance R _var The size is equal to the resistance R _p1 ～R _p8 The series resistance sum of the access working parts is specifically: the threshold resistance adjusting unit Res-adjust translates and outputs the input four-bit binary coded instruction, O _p1 ～O _p8 At the same TH<3:0>Only one valid bit is output during input; corresponding control NMOS transistor M _p1 ～M _p8 Any one of the tubes is turned on, the resistance R _p1 ～R _p8 The number of the access operations is changed along with the change of the number of the access operations, thereby realizing the threshold resistance R _var And (5) adjusting the size.

Preferably, NMOS transistor M _p0 Gate and switch K of (2) _c1 -K _c1 SwitchIs controlled by an external digital circuit and is used for eliminating offset voltage generated by the Peak detection circuit Peak Detector and the comparator COMP due to device mismatch.

Preferably, the comparator COMP output LOS _out The output judgment result controls the magnitude of the bias current of the Peak Detector to realize hysteresis, and the hysteresis sensitivity of the comparator COMP is as follows:

and the hysteresis is fixed.

Preferably, the bias Current source IBias Current comprises a PMOS transistor M _i1 ～M _i9 Operational amplifier AMP _i1 Bipolar transistor Q _i1 ～Q _i3 Capacitance C _i1 Capacitance C _i2 PMOS transistor M _i10 PMOS transistor M _i11 PMOS transistor M _i12 And resistance R _i1 ～R _i4 ；

PMOS transistor M _i1 ～M _i9 The source electrode of the capacitor is connected with the power supply VDD at the same time;

PMOS transistor M _i1 ～M _i3 Gate of (c) and PMOS transistor M _i1 The drain of (a) is connected with the resistor R at the same time _i1 Is a member of the group;

resistor R _i1 And NMOS transistor M _i12 Is connected with the drain electrode of the transistor;

NMOS transistor M _i12 Is connected with bias voltage V _iB Are connected;

PMOS transistor M _i2 Drain electrode of (d) bipolar transistor Q _i1 Is connected with the collector and base of the same and the operational amplifier AMP _i1 Is connected with the non-inverting input end of the circuit;

bipolar transistor Q _i1 Emitter pass resistance R of (2) _i2 Grounding;

Operational amplifier AMP _i1 Output of (2)end-to-NMOS transistor M _i11 Connected to the gate of (C) and passing through a capacitor C _i1 Grounding;

PMOS transistor M _i3 Drain electrode of (d) bipolar transistor Q _i2 Is connected with the collector and base of the same and the operational amplifier AMP _i1 Is connected with the inverting input terminal of the circuit;

NMOS transistor M _i11 Source and bipolar transistor Q _i2 Is connected with the emitter of the resistor R _i3 Grounding;

PMOS transistor M _i4 ～M _i6 Gate of (2), PMOS transistor M _i4 Is simultaneously with the drain of NMOS transistor M _i11 Is connected with the drain electrode of the transistor;

PMOS transistor M _i5 For outputting bias current IB ₁ ；

PMOS transistor M _i6 Drain of NMSO transistor M _i10 Is simultaneously with the gate of the bipolar transistor Q _i3 Is connected with the collector of the capacitor;

PMOS transistor M _i7 ～M _i9 Gate of (2), PMOS transistor M _i8 Is simultaneously with the drain of NMOS transistor M _i10 Is connected with the drain electrode of the transistor;

PMOS transistor M _i6 Drain of (d) and PMOS transistor M _i7 Across capacitance C between drains of (C) _i2 ，

PMOS transistor M _i7 Drain of (d) and bipolar transistor Q _i3 Is connected with the base electrode of (C) and passes through a resistor R _i4 Grounding;

PMOS transistor M _i9 For outputting bias current IB ₂ ；

NMSO transistor M _i12 Source, bipolar transistor Q _i3 Emitter of (a) and NMSO transistor M _i10 The source of (c) is grounded.

Preferably, the bias Current source IBias Current provides a bias Current IB proportional to absolute temperature to the pre-op AMP ₁ The gain of the pre-operational amplifier AMP is made independent of temperature, and a bias current IB is introduced ₁ The gain of post AMP is:

wherein n is a resistor R _i2 And R is _i3 Resistance ratio of n=r _i3 /R _i2 M is the number ratio of the transistors participating in the operation, m=q _i2 /Q _i1 ，R _S Is a source negative feedback resistor of a bipolar transistor in a conduction branch;

bias Current source IBias Current provides bias Current IB inversely related to absolute temperature to Peak Detector ₂ To reduce the absolute value of the temperature coefficient of the Peak Detector output voltage.

Preferably, the comparator COMP comprises a PMOS transistor M _c1 ～M _c7 Current source I _c1 ～I _c12 Inverter A _c1 Switch K with complementary switches _c1 ～K _c6 And a switch

PMOS transistor M _c1 PMOS transistor M _c2 PMOS transistor M _c6 The source electrode of the power supply is connected with the power supply VDD;

PMOS transistor M _c1 Gate of (2), PMOS transistor M _c2 Gate of (2), PMOS transistor M _c1 Drain of NMOS transistor M _c3 Is simultaneously with the switch K _c1 ～K _c6 Is connected with one end of the connecting rod;

PMOS transistor M _c2 Drain of PMOS transistor M _c6 Gate of (2) NMOS transistor M _c4 Is simultaneously with the switch of the drain electrode of (a)Is connected with one end of the connecting rod;

NMOS transistor M _c3 Reference voltage output terminal V of grid electrode and Peak detection circuit Peak Detector _ref Are connected;

NMOS transistor M _c4 Amplitude voltage output terminal V of grid electrode and Peak detection circuit Peak Detector _PD Are connected;

NMOS transistor M _c3 NMOS transistor M _c4 Source of (d) and NMOS transistor M _c5 Is connected with the drain electrode of the transistor;

NMOS transistor M _c5 NMOS transistor M _c7 Is connected with bias voltage V _cB Are connected;

switch K _c1 ～K _c6 Respectively through the other ends of the current sources I _c1 ～I _c6 Grounding;

switchRespectively through the other ends of the current sources I _c7 ～I _c12 Grounding;

each switch is correspondingly connected with one current source;

PMOS transistor M _c6 Drain of NMOS transistor M _c7 Is simultaneously with the drain of the inverter A _c1 Is connected with the input end of the power supply;

NMOS transistor M _c5 Source of (d) and NMOS transistor M _c7 The source electrode of the transistor is grounded;

inverter A _c1 Output of (2) and output of LOSs of signal detection circuit (LOS) _out Are connected.

The invention has the beneficial effects that: the invention provides an improvement on the basis of the traditional LOS circuit, improves the operational amplifier with fixed gain into an operational amplifier with adjustable gain, improves the threshold resistance of the peak detection circuit into a resistance value which is variable, and combines the two to realize the programmable threshold of the LOS circuit. And the high-precision detection of the LOS circuit is realized by carrying out temperature compensation on the operational amplifier and carrying out temperature and process compensation on the peak detection circuit.

The signal loss detection circuit can adapt to different system requirements by realizing the programmable threshold value of the signal loss detection circuit, so that the detection precision of the signal loss detection circuit is improved, and the circuit can adapt to complex application environments. The LOS circuit has been validated by simulation.

Drawings

FIG. 1 is a schematic diagram of a prior art loss of signal detection circuit;

FIG. 2 is a schematic diagram of a programmable threshold loss of signal detection circuit with temperature and process compensation according to the present invention;

FIG. 3 is a schematic circuit diagram of a gain adjustable pre-sense amplifier;

FIG. 4 is a schematic circuit diagram of a peak detection circuit with adjustable threshold resistance;

FIG. 5 is a schematic circuit diagram of a temperature dependent bias current source circuit;

FIG. 6 is a schematic circuit diagram of a comparator with process compensation;

FIG. 7 is a graph of the relationship between the threshold of the loss of signal detection circuit and the input values of the threshold control ports TH <3:0 >; wherein fig. 7 (a) is two curves of alarm voltage and alarm voltage, and fig. 7 (b) is a graph comparing curves under different temperature and input voltage conditions;

fig. 8 is a relationship between the gain and temperature of the operational amplifier AMP;

FIG. 9 is a graph of peak detection circuit output voltage versus temperature;

FIG. 10 is a plot of offset voltage between the COMP inputs of the comparator;

fig. 11 is a hysteresis sensitivity curve for different thresholds in a loss of signal detection circuit.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.

The invention is further described below with reference to the drawings and specific examples, which are not intended to be limiting.

The first embodiment is as follows: the present embodiment will be described below with reference to fig. 2. This embodiment describes the framework of a threshold programmable loss of signal detection circuit with temperature and process compensation.

As known from the threshold voltage of the conventional LOS circuit, the threshold value of the LOS circuit is related to the gain of the operational amplifier AMP and the magnitude of the threshold resistance of the Peak Detector, and thus the threshold value of the LOS circuit can be programmable by adjusting the gain of the operational amplifier AMP and the magnitude of the threshold resistance of the Peak Detector. By analyzing the influence of factors affecting the LOS circuit threshold, including temperature variations, power supply voltage fluctuations and process variations, on the LOS circuit threshold voltage, several factors with greater influence on the LOS threshold are found: the effect of temperature variation on the gain of the operational amplifier AMP, the effect of temperature variation on the output voltage of the Peak Detector, the effect of process deviation on the output voltage of the Peak Detector, and the effect of process deviation on the hysteresis comparator COMP. These factors are then compensated for: the gain of the operational amplifier AMP is subjected to temperature compensation, the output voltage of the peak detection circuit is subjected to temperature compensation, and the peak detection circuit and the hysteresis comparator are subjected to process compensation, so that the detection precision of the LOS circuit is improved, and the peak detection circuit adopting a symmetrical structure can reduce the temperature change to a certain extent, the power supply voltage change and the influence of the process on the LOS circuit precision. In addition, the LOS circuit requires a hysteresis voltage with stable sensitivity to prevent jitter at the output of the LOS circuit caused by unwanted noise when the input signal amplitude approaches the LOS circuit threshold. The traditional LOS circuit has the advantages that the threshold value is fixed, so that the hysteresis sensitivity stability of LOS can be realized only by using one hysteresis comparator; when the LOS circuit threshold is changed, if it is desired that the hysteresis sensitivity of the LOS circuit remains unchanged, the hysteresis voltage window size needs to change with the threshold of the LOS circuit, which presents challenges to the design of the LOS circuit. According to the invention, the comparator and the peak detection circuit are combined, and the bias current of the peak detection circuit is controlled by the output voltage of the comparator, so that the LOS circuit has a hysteresis with stable sensitivity while the threshold is programmable.

In view of this, the present embodiment designs a threshold programmable loss of signal detection circuit with temperature and process compensation, as shown in fig. 2, including a pre-op AMP, a Peak Detector, a comparator COMP, a bias Current source IBias Current, a capacitor C1, and a capacitor C2;

IBias Current is the bias Current source of the LOS circuit, which outputs two currents IB ₁ And IB (group B) ₂ Bias current is provided to AMP and Peak Detector. The differential input signal is input from INP, INN and fed into the gain-adjustable operational amplifier AMP. Gain of AMP through TH<3:0>And adjusting. TH (TH)<3:0>For four-bit binary coding, can be rootedThe setting is made manually as required. After the differential signal passes through AMP, it is passed through two coupling capacitors (C ₁ ，C ₂ ) Is fed to a Peak Detector for Peak detection. The threshold resistance of the Peak Detector may be determined by TH<3:0>Setting is performed. Output voltage V of Peak Detector _PD -V _ref Is sent to a comparator COMP for judgment, when V _PD -V _ref When the voltage is more than 0, COMP outputs a low level; when V is _PD -V _ref When < 0, COMP outputs high level.

The threshold programming of the LOS circuit is accomplished by both AMP and Peak Detector.

The second embodiment is as follows: next, this embodiment will be further described with reference to fig. 2 to 11, which give a detailed description of the specific structure of each part in the frame described in this embodiment, and a detailed analysis of the principle thereof.

First, a threshold programmable implementation of the LOS circuit will be described.

Threshold programmable implementation of LOS circuit: the LOS circuit controls the gain of the AMP and the threshold resistance of the Peak Detector through TH <3:0>, so that the threshold of the LOS circuit is programmable.

Fig. 3 shows a structural diagram of AMP, specifically: the pre-operational amplifier AMP includes a Gain adjusting unit Gain-adjust, a bipolar transistor Q _a1 ～Q _a6 Resistance R _a1 ～R _a8 NMOS transistor M _a1 ～M _a7 An inductance L1 and an inductance L2;

resistor R _a3 Resistance R _a4 At the same time as the other end ofAnd NMOS transistor M _a6 Is connected with the drain electrode of the transistor;

Wherein the circuit module Gain-adjust is a decoder for encoding four bits of binary code TH<3:0>Translation, its output terminal O _a1 ，O _a2 ，O _a3 There are three cases of output states: 001 010, 100,1 represents an output high level, and 0 represents an output low level. NMOS transistor M _a5 ，M _a6 ，M _a7 Is used as a switch to control the gain of the AMP. M is M _a5 ，M _a6 ，M _a7 Gate and gate-adjust output terminal O _a1 ，O _a2 ，O _a3 Connected when M _a5 ，M _a6 ，M _a7 When the gate of one of the NMOS is at a high level, the NMOS is in a conductive state, and the other NMOS is in a non-conductive state, the gain on the branch of the conductive NMOS is equal to the gain of the entire AMP. Resistor R _a1 And R is _a2 ，R _a3 And R is _a4 ，R _a5 And R is _a6 The resistor is divided into three groups, the resistance values in each group are equal, and the resistance values among the groups are unequal.

The gain process of the pre-op AMP is adjusted by TH <3:0> input of a four bit binary code instruction as follows:

gain A of AMP _V The method comprises the following steps:

O _a1 ，O _a2 ，O _a3 ＝001，A _V ＝g _m R _a8 /(1+g _m R _a6 )；

O _a1 ，O _a2 ，O _a3 ＝010，A _V ＝g _m R _a8 /(1+g _m R _a4 )；

O _a1 ，O _a2 ，O _a3 ＝100，A _V ＝g _m R _a8 /(1+g _m R _a2 )。

due to resistance R _a2 ，R _a4 And R is _a6 The values of (2) are different, so that the gain of AMP will be dependent on O _a1 ，O _a2 ，O _a3 The output of (a) changes. I.e. the gain of AMP is derived from TH<3:0>And (5) controlling.

Next, fig. 4 shows a specific structure of a Peak Detector (Peak Detector) with a variable threshold resistance: the Peak Detector includes a threshold resistance adjusting unit Res-adjust, a bipolar transistor Q _p1 ～Q _p4 Resistance R _p1 ～R _p20 NMOS transistor M _p0 NMOS crystalTube M _p1 ～M _p15 Capacitance C _p1 And capacitor C _p2 ；

bipolar transistor Q _p3 Emitter, bipolar transistor Q of (2) _p4 Emitter, resistor R of (2) _p9 One end of (C) capacitor _p2 At the same time of one end of (a)Reference voltage output terminal V of Peak Detector _ref Are connected;

resistor R _p9 ～R _p16 Sequentially connected in series;

Wherein the threshold resistance (R _var ) Output terminal V of Peak Detector _PD To bipolar transistor Q _p1 And Q _p2 The sum of the resistances between the emitters of (a). The sum of which is controlled by the circuit block Res-adjust. Res-adjust is a decoder whose input inputs a four-bit binary code TH<3:0>The output end is O _p1 ～O _p8 Its output is high and active, O _p1 ～O _p8 At the same TH<3:0>Only one valid bit is output when input. Res-adjust output O _p1 ～O _p8 And NMOS transistor M _p1 ～M _p8 Is connected to the gate of (c). When M _p1 ～M _p8 When one of the gates is at a high level, the NMOS is in a conductive state, the NMOS is equivalently a short circuit,at this time R of Peak Detector _var Source-to-bipolar transistor Q for the NMOS _p1 And Q _p2 The sum of the resistances between the emitters of (a). TH therefore<3:0>The threshold resistance R of the Peak Detector can be controlled by Res-adjust _var Is a value of (2).

Similar to the conventional LOS circuit analysis method, the output voltage analysis process of the Peak Detector in the present invention is as follows: differential signals are fed from the input terminals VIN1 and VIN2 of the Peak Detector, and the single-ended signal amplitude of the differential signals is A _V V _peak . Setting bipolar transistor Q _p1 And Q _p2 The sum of instantaneous collector currents of (a) is I _C Average current is I ₀ +I _HYS0 . Since the Peak Detector is a symmetrical circuit in the present invention, there is I ₁ +I _HYS1 ＝I ₀ +I _HYS0 . As can be seen from the output voltage formula of the Peak Detector in the conventional LOS circuit, the output voltage of the Peak Detector in the present invention is

Wherein, the liquid crystal display device comprises a liquid crystal display device,is the detection error of the output voltage of the Peak Detector in the present invention; a is that _V Is the gain of AMP in the present invention; r is R _var Is the threshold resistance of the Peak Detector in the present invention.

From the output voltage of the Peak Detector in the present invention, the threshold voltage of the present invention is obtained

Due to the gain of AMP in the present invention (A _V ) And a threshold resistance (R _var ) Are all variable values and are each a set of four-bit binary codes TH<3:0>Control, so can be achieved by controlling TH<3:0>Thereby controlling the threshold voltage of the present invention. The invention is thatThreshold programmable implementation of LOS circuit figure 7 illustrates the threshold voltage vs. TH of the present invention <3:0>Wherein FIG. 7 (a) shows two curves of the alarm voltage and the alarm voltage, respectively representing the current I _HYS0 Fig. 7 (b) shows a graph comparing threshold voltages of the present invention under different temperature and input voltage conditions, and it can be seen from the graph that temperature variation and power supply voltage variation have no influence on the threshold voltages of the present invention.

Next, the principle of how AMP proposed by the present invention improves circuit accuracy is analyzed:

embodiments of the present invention for improving AMP gain stability are described below with reference to fig. 3 and 5. Fig. 3 is a block diagram of AMP. Wherein NMOS transistor M _a1 ，M _a4 ，M _a3 ，M _a4 Constitute a current mirror, IB ₁ For bias current, provided by the bias circuit of fig. 5; resistor R _a1 ，R _a2 ，R _a3 ，R _a4 ，R _a5 ，R _a6 Is a source negative feedback resistor for improving the linearity of the AMP.

The bias Current source IBias Current includes a PMOS transistor M _i1 ～M _i9 Operational amplifier AMP _i1 Bipolar transistor Q _i1 ～Q _i3 Capacitance C _i1 Capacitance C _i2 PMOS transistor M _i10 PMOS transistor M _i11 PMOS transistor M _i12 And resistance R _i1 ～R _i4 ；

NMOS transistor M _i12 Is connected with bias voltage V _iB Are connected;

PMOS transistor M _i2 Drain electrode of (C) and bipolar crystalBody tube Q _i1 Is connected with the collector and base of the same and the operational amplifier AMP _i1 Is connected with the non-inverting input end of the circuit;

bipolar transistor Q _i1 Emitter pass resistance R of (2) _i2 Grounding;

operational amplifier AMP _i1 And NMOS transistor M _i11 Connected to the gate of (C) and passing through a capacitor C _i1 Grounding;

PMOS transistor M _i5 For outputting bias current IB ₁ ；

PMOS transistor M _i9 For outputting bias current IB ₂ ；

Because of nonlinearity in the circuit, the small signal gain of the AMP changes along with the change of the amplitude of the input signal, so that the threshold value of the LOS circuit changes, and the detection precision of the LOS circuit is reduced. Therefore, the invention improves the linearity of the AMP and reduces the dependence of the gain of the AMP on the amplitude of the input signal by adopting the source negative feedback technology. For AMP in FIG. 3, the gain is

Wherein g _m Is the transconductance, R, of the bipolar transistor of the conducting branch in the AMP _S Is the source degeneration resistor of the bipolar transistor in the turn-on branch. Rewriting gain formula of AMP

As can be seen from the gain formula of the rewritten AMP, g _m When large, 1/g _m ≈0，R _S ＞＞1/g _m . At this time, g in the gain of the AMP _m The contribution of (2) is far smaller than R _S And with R _S Increase in g _m The smaller the contribution of (c). Due to g _m The value of (2) varies with the amplitude of the input signal, resulting in the gain of AMP varying with the amplitude of the input signal, so when g _m The smaller the gain contribution to AMP, the weaker the relationship between the gain of AMP and the input signal amplitude, i.e. the better the linearity of AMP.

Second, AMP gain is susceptible to temperature changes. The reason is that the device parameter of the bipolar transistor is sensitive to temperature change, and the relation between the transconductance of the bipolar transistor and the temperature is that

Wherein I is _C Collector current of bipolar transistor, V _T Is a thermal voltage. The present invention achieves AMP gain independent of temperature by providing a bias current to AMP that is positively correlated to absolute temperature. The following describes the embodiment with reference to fig. 5. The invention realizes a bias current proportional to absolute temperature by utilizing the fact that the difference value of the base-emitter voltages of the bipolar transistors under unequal current densities is proportional to absolute temperature. In fig. 5, an operational amplifier AMP _i1 The voltages of the non-inverting input terminal and the inverting input terminal are the same; bipolar transistor Q _i1 And Q _i2 Single size is the same, the number ratio is m, Q _i2 /Q _i1 =m; resistor R _i2 And R is _i3 The ratio is n, R _i3 /R _i2 =n; PMOS transistor M _i2 And M _i3 The ratio of the dimensions of (2) is M _i2 /M _i3 N, so, it can be assumed that M _i2 Is nI, M _i3 Is I; PMOS transistor M _i4 And M _i5 The size ratio is 1:1; m is M _i4 And M _i5 Is a current mirror, so M _i11 Is also IB ₁ The method comprises the steps of carrying out a first treatment on the surface of the First, due to AMP _i1 Is present at the non-inverting input voltageAnd an inverting input voltage +.>Identical, and

so that

And because of R _i3 /R _i2 ＝n，

And according to the collector current formula of the bipolar transistor

In bipolar transistor Q _i1 And Q _i2 The method comprises the following steps:

so there are:

V _T ln(mn)＝IB ₁ R _i3

establishment; so that:

can be derived from IB ₁ The current of (2) is of the magnitude of

The temperature coefficient is as follows

IB ₁ Is an output current positively correlated with absolute temperature, IB ₁ Is fed into the AMP as a bias current so that the gain of the AMP is independent of temperature. Will IB ₁ Substituted into the gain of AMP:

from the gain formula of AMP, A _V Independent of temperature. Fig. 8 shows the gain of AMP as a function of temperature. Wherein A is _V 1,A _V 2,A _V 3 is a curve of the gain of AMP after temperature compensation along with the change of temperature, A _V 4,A _V 5,A _V 6 is a graph showing the gain of AMP without temperature compensation as a function of temperature, which shows that the gain of AMP is insensitive to temperature change after temperature compensation.

An implementation of temperature compensation of the Peak Detector is described below with reference to fig. 4 and 5. FIG. 4 is a diagram showing the structure of the Peak Detector in the present invention, in which the NMOS transistor M _p11 ,M _p12 ,M _p13 ,M _p14 ,M _p15 Is a current mirror, IB ₂ The temperature coefficient of the output voltage of the Peak Detector is reduced by providing the Peak Detector with a bias current that is inversely related to the absolute temperature. The output voltage of the Peak Detector in the invention is

The gain of AMP in the present invention is independent of temperature after temperature compensation. The temperature coefficient of the output voltage of the Peak Detector in the present invention is:

for ease of calculation, assume the current ratioIndependent of temperature. Assuming that the temperature coefficient of the output voltage of the Peak Detector is 0 in the present invention, then

The temperature coefficient of the bias current is negative and variable, but this increases the complexity of the circuit design. In order to obtain the minimum temperature coefficient of the Peak Detector output voltage while simplifying the circuit design, the influence of the temperature coefficient of the bias current on the threshold value of the LOS circuit is considered. When the threshold voltage of the LOS circuit is large, R _var The bias current changes with temperature to cause the threshold voltage of the LOS circuit to change with temperature to a larger extent, so the temperature coefficient of the bias current has a larger influence on the threshold voltage of the LOS circuit, and when R _var When larger, the bias current of the peak detection circuit should have a smaller temperature coefficient. When the threshold voltage of the LOS circuit is small, R _var The bias current changes with temperature to cause the threshold voltage of the LOS circuit to change less with temperature, so the temperature coefficient of the bias current has less influence on the threshold voltage of the LOS circuit, when R _var The bias current of the peak detection circuit allows for a larger temperature coefficient when smaller. Setting R in the temperature coefficient of the bias current _var At maximum value R _max . Then the temperature coefficient of the bias current is substituted into the temperature coefficient of the output voltage of the Peak Detector to be

When R is _var At the time of maximum value, the maximum value,is 0 when R _var In case of change, the wearer is strapped with->The temperature coefficient is the smallest. />

The bias circuit of FIG. 5 provides a negative absolute temperature dependent bias current IB for the Peak Detector ₂ . Due to the base-collector voltage V of bipolar transistors _BE Is inversely related to absolute temperature, so that when temperature increases, Q _i3 Base collector voltage V of (2) _BEi3 Drop, resistance R _i4 Voltage drop across resistor R _i4 Is decreased; PMOS transistor M _i7 ,M _i8 ,M _i9 Make up of current mirror, IB ₂ Is fed into the peak detection circuit as a bias current. IB (IB) ₂ Is of the size of

IB ₂ The temperature coefficient of (2) is:

E _g is the band gap energy of silicon, E _g ≈1.12eV；

q: electron charge quantity

T: thermodynamic temperature

m is about equal to-3/2

k: boltzmann constant

Regulation of IB ₂ Is of the temperature coefficient of

The temperature coefficient of the output voltage of the Peak Detector can be lowered.

FIG. 9 shows the output voltage V of the Peak Detector _PD -V _ref Curve as a function of temperature. Firstly, selecting an output value at normal temperature to enable V _PD -V _ref And then the value of (2) is 0, the input value is kept unchanged, the simulation environment temperature is changed, and the output is observed. Where temp. comp indicates that the peak detection circuit is temperature compensated. Taking maximum and minimum threshold resistances of the Peak detectors as examples, it is known that when temperature compensation is not performed, the output voltage V is at the maximum threshold resistance of the Peak Detector _PD -V _ref The change along with the temperature is large; when the threshold resistance of the Peak Detector is minimum, the influence of temperature change on the output voltage is small, and even if a large temperature coefficient exists, the influence on the output voltage is small. Therefore, a better temperature compensation effect can be realized through the temperature compensation mode. Temp. Comp in FIG. 9 shows the temperature compensated Peak Detector output voltage V _PD -V _ref As a result, the Peak Detector can be configured to output a high voltage even when the Peak Detector has a high threshold resistance or the Peak Detector has a low threshold resistance. This demonstrates the effectiveness of this temperature compensation. After temperature compensation, the output voltage of the Peak Detector becomes insensitive to temperature variations.

The implementation of the process compensation according to the invention is described below with reference to fig. 4 and 6. Fig. 4 shows the Peak Detector of the present invention. The Peak Detector is symmetrical, bipolar transistor Q _p1 ，Q _p2 ，Q _p3 ，Q _p4 Are transistors of the same size. FIG. 6 shows COMP in the present invention, specifically: the comparator COMP includes a PMOS transistor M _c1 ～M _c7 Current source I _c1 ～I _c12 Inverter A _c1 Switch K with complementary switches _c1 ～K _c6 And a switch

each switch is correspondingly connected with one current source;

Wherein, NMOS transistor M _c3 ，M _c4 ，M _c5 ，M _c7 PMOS transistor M _c1 ，M _c2 ，M _c6 And inverter A _c1 Composition comparator, switch K _c1 -K _c6 ，And a current source I _c1 -I _c12 A process compensation circuit is formed. Switch K _c1 -K _c6 And->Is complementary. For example K _c1 Opening and/or closing>Then it is closed. These switches have a set of six-bit binary coded controls. Current I _c1 -I _c6 The magnitude relation between the two is an exponential relation, I _ci ＝2 ^i-1 I _c1 ，i＝1，2，...，6。

Current I _c7 -I _c12 The size between is I _ci ＝I _c(i-6) . Current I _os4 Is the current I _c7 -I _c12 The sum of the currents between, current I _os3 Is the current I _c1 -I _c6 The sum of the currents in between. Due to device mismatch, there is a random variation of symmetrical devices in the circuit, resulting in errors in the actual circuit. In the present invention, since the symmetrical devices exist in both the Peak Detector and the comparator, it is necessary to analyze and process compensate for the mismatch. NMOS transistor M _p0 Gate and switch K of (2) _c1 -K _c1 SwitchIs controlled by an external digital circuit and is used for eliminating offset voltage generated by the Peak detection circuit Peak Detector and the comparator COMP due to device mismatch. The digital circuit is used for storing the offset cancellation information of the LOS circuit. The digital circuit is assumed to store a value of 1 after the offset cancellation circuit of the LOS circuit is completed, and to store a value of 0 when the offset cancellation circuit of the LOS circuit is not operated. Then M is given before the offset cancellation circuit of LOS is operated because the stored information is 0 _p0 Is turned on by a high level, and then the offset cancellation operation is completed. If the stored information is 1, then give M _p0 Is turned off by a low level.

In the present invention, the mismatch existing in the Peak Detector is finally reflected on the output voltage of the Peak Detector. Ideally, when the input signal of the Peak Detector is 0 and the transistor M _p0 In the on state, the output voltage V of the Peak Detector _PD -V _ref Is 0. However, due to mismatch, transistor Q _p1 ，Q _p2 ，Q _p3 ，Q _p4 May be different, resulting in V _PD ≠V _ref . In the invention, mismatch of the Peak Detector and the comparator is equivalent to offset voltage of the COMP input end, and the process compensation in the invention is realized by eliminating the whole offset voltage. The process compensation mode in the invention is as follows: first, in fig. 4, NMOS transistor M of Peak Detector _p0 Gate O of (2) _p0 Giving a high level such that M _p0 Conducting. Output terminal V of Peak Detector _PD And V _ref Connected to the input of the comparator of fig. 6. Due to bipolar transistor Q in Peak Detector _p1 -Q _P4 Is the same in size, so Q _p1 -Q _P4 The emitter voltages of (a) should be the same. Due to M _p0 On, so V _PD And V _ref Should be the same. The input voltages of the comparators of fig. 6 should be the same, which is equivalent to shorting the comparator inputs. Second, switch K _c1 -K _c6 ，Control current I _os4 Maximum sum current I _os3 Minimum, and with I _os1 +I _os3 ＜I _os2 +I _os4 . At this time, the comparator outputs a low level. Then through control switch K _c1 -K _c6 ，/>Control current I _os4 Reducing sum current I _os3 And (3) increasing. When the current I _os1 +I _os3 And current I _os2 +I _os4 When the difference crosses zero, i.e. I _os1 +I _os3 ≥I _os2 +I _os4 The current stops changing and the comparator changes from low to high. NMOS transistor M in Peak Detector of FIG. 4 _p0 Becomes non-conductive. At this time current I _os3 And current I _os4 Current to be compensated for by the process.

FIG. 10 shows the result of the input offset voltage equivalent to the input terminal of COMP after process compensation. 100 times of simulation are carried out by adopting Monte Carlo simulation, wherein the equivalent input offset voltage after offset elimination is the simulation result of the equivalent input offset voltage of the COMP input end when process compensation is adopted, and most offset voltages are in the range of-1 to 0; the equivalent input offset voltage before offset elimination is the equivalent input offset voltage of the COMP input end when process compensation is not adopted, and the result is normally distributed. It can be seen that the input offset voltage equivalent to the input terminal of COMP is greatly reduced by the process compensation circuit.

The implementation of hysteresis in the present invention is described below in connection with fig. 4 and 6.

Because of the large programmable threshold range of the present invention, it is not desirable to rely on comparators alone to achieve a hysteresis effect, and it is difficult to achieve a fixed optical hysteresis. We pass through the output LOS of COMP in fig. 6 _out The magnitude of the bias current of the Peak Detector is controlled in fig. 4 to achieve hysteresis. The invention is specific to hysteresisThe working principle is as follows: when the amplitude of the input signal is smaller than the threshold value of the LOS circuit, COMP outputs high level to control NMOS transistor M in Peak Detector _p9 ，M _p10 Conducting, at this time, the bias current is I ₀ +I _HYS0 And I ₁ +I _HYS1 The method comprises the steps of carrying out a first treatment on the surface of the When the amplitude of the input signal is just larger than the threshold value of the LOS circuit, the output of COMP is changed from high level to low level, and the NMOS transistor M in the Peak Detector _p9 ，M _p10 Is not conductive, its bias current becomes I ₀ And I ₁ Output terminal V of Peak Detector _ref Voltage rise I _HYS0 R _var +ΔV _BE ，V _PD The voltage will rise by DeltaV _BE ，R _var The threshold resistance of the Peak Detector is the same as that of the threshold resistor, so that if V _PD Falling such that the COMP output goes low again to high requires falling I _HYS0 R _var . Hysteresis is generated thereby. The hysteresis sensitivity of COMP in the present invention is:

the sensitivity is only the same as the bias current I in the Peak Detector _HYS0 To the size of the hysteresis so that the hysteresis is fixed. Fig. 11 shows that the hysteresis of the loss of signal detection circuit is fixed at different thresholds.

The high-precision threshold programmable LOS provided by the invention compensates factors influencing the threshold of the LOS circuit, so that the LOS can realize high-precision detection under the condition of programmable threshold, the implementation mode of hysteresis of the LOS circuit is modified, and the hysteresis sensitivity of the LOS circuit under the condition of programmable threshold is fixed by utilizing the change of the bias current of the Peak Detector. The circuit can operate in different systems and complex environments due to its large programmable threshold range and high accuracy.

Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that the different dependent claims and the features described herein may be combined in ways other than as described in the original claims. It is also to be understood that features described in connection with separate embodiments may be used in other described embodiments.

Claims

1. The programmable threshold value signal loss detection circuit with temperature and process compensation is characterized by comprising a front-end operational amplifier AMP, a Peak detection circuit Peak Detector, a comparator COMP, a bias Current source IBias Current, a capacitor C1 and a capacitor C2;

the pre-op AMP and Peak Detector are both provided with a threshold control port TH <3:0>, by controlling port TH <3 to the threshold value: 0> inputting a four-bit binary coding instruction to adjust the gain of the pre-operational amplifier AMP and the threshold resistance of the Peak Detector circuit so as to realize the programmable threshold of the LOS circuit, and controlling the bias current of the Peak Detector circuit by the output of the comparator COMP so as to realize fixed hysteresis;

The pre-operational amplifier AMP includes a Gain adjusting unit Gain-adjust, a bipolar transistor Q _a1 ～Q _a6 Resistance R _a1 ～R _a8 NMOS transistor M _a1 ～M _a7 An inductance L1 and an inductance L2;

the input end of the Gain-adjusting unit Gain-adjust is a threshold control port TH<3：0>The Gain adjusting unit Gain-adjust translates and outputs the input four-bit binary code instruction, the Gain adjusting unit Gain-adjust output terminal O _a1 ，O _a2 ，O _a3 The output state of (2) is: 001. 010 or 100; output terminal O _a1 ，O _a2 ，O _a3 Respectively connected with NMOS transistor M _a5 、M _a6 、M _a7 A gate electrode of (a);

NMOS transistor M _a1 NMOS transistor M _a2 NMOS transistor M _a3 NMOS transistor M _a4 The source electrode of the transistor is grounded;

by TH <3:0> the four-bit binary code instruction is input to adjust the gain of the pre-op AMP by:

gain A of AMP _V Pressing down typeObtaining:

O _a1 ，O _a2 ，O _a3 ＝001，A _V ＝g _m R _a8 /(1+g _m R _a6 )；

O _a1 ，O _a2 ，O _a3 ＝010，A _V ＝g _m R _a8 /(1+g _m R _a4 )；

O _a1 ，O _a2 ，O _a3 ＝100，A _V ＝g _m R _a8 /(1+g _m R _a2 )；

the Peak Detector includes a threshold resistance adjusting unit Res-adjust, a bipolar transistor Q _p1 ～Q _p4 Resistance R _p1 ～R _p20 NMOS transistor M _p0 NMOS transistor M _p1 ～M _p15 Capacitance C _p1 And capacitor C _p2 ；

The input end of the threshold resistance adjusting unit Res-adjust is a threshold control port TH<3：0>The threshold resistance adjusting unit Res-adjust translates and outputs the input four-bit binary coded instruction, and the threshold resistance adjusting unit Res-adjust eight output terminals O _p1 ～O _p8 Its output is high and active, O _p1 ～O _p8 At the same timeTH<3：0>Only one valid bit is output during input; output terminal O _p1 ～O _p8 Respectively connected with NMOS transistor M _p1 ～M _p8 A gate electrode of (a);

resistor R _p1 ～R _p8 In series in turn, resistance R _p1 One end is connected with NMOS transistor M _p0 Is connected with the source electrode of the resistor R _p1 ～R _p8 Respectively with NMOS transistor M _p1 ～M _pa The sources of the electrodes are connected one by one;

NMOS transistor M _p12 Drain of NMOS transistor M _p9 Is simultaneously with the drain of NMOS transistor M _pa Is connected with the source electrode of the transistor;

resistor R _p9 ～R _p16 Sequentially connected in series;

2. The programmable threshold loss of signal detection circuit with temperature and process compensation of claim 1, wherein the NMOS transistor M in Peak Detector circuit Peak Detector _p11 ，M _p12 ，M _p13 ，M _p14 ，M _p15 Is a current mirror, M _p13 ，M _p14 Respectively with NMOS transistor M _p9 ，M _p10 Two additional current branches are formed;

the output voltage of the Peak Detector is

Wherein V is _PD The amplitude voltage V output by the Peak Detector is _ref A is the reference voltage of the Peak Detector _V Gain of AMP, V _peak For peak value of AMP input signal, V _T Is thermal voltage, I _C Is a bipolar transistor Q _p1 And Q _p2 The sum of collector currents of I ₀ 、I ₁ 、I _HYS0 、I _HYS1 Is the tail current and is presentRelation I ₀ +I _HYS0 ＝I ₁ +I _HYS1 ；R _var A threshold resistance which is a Peak Detector of the Peak detection circuit;

Threshold resistance R _var The magnitude of (2) is controlled and regulated by four-bit binary code input from outside, and the threshold resistance R _var The size is equal to the resistance R _p1 ～R _p8 The series resistance sum of the access working parts is specifically: the threshold resistance adjusting unit Res-adjust translates and outputs the input four-bit binary coded instruction, O _p1 ～O _p8 At the same TH<3：0>Only one valid bit is output during input; corresponding control NMOS transistor M _p1 ～M _p8 Any one of the tubes is turned on, the resistance R _p1 ～R _p8 The number of the access operations is changed along with the change of the number of the access operations, thereby realizing the threshold resistance R _var And (5) adjusting the size.

3. The programmable threshold loss of signal detection circuit with temperature and process compensation of claim 1, wherein NMOS transistor M _p0 Gate and switch K of (2) _c1 -K _c6 SwitchIs controlled by an external digital circuit and is used for eliminating offset voltage generated by the Peak detection circuit Peak Detector and the comparator COMP due to device mismatch.

4. A programmable threshold LOSs of signal detection circuit with temperature and process compensation according to claim 2, wherein the comparator COMP output LOS _out Judgment of outputThe off-state results control the magnitude of the bias current of the Peak Detector to realize hysteresis, and the hysteresis sensitivity of the comparator COMP is:

and the hysteresis is fixed.

5. The programmable threshold loss of signal detection circuit with temperature and process compensation of claim 1, wherein the bias Current source IBias Current comprises a PMOS transistor M _i1 ～M _i9 Operational amplifier AMP _i1 Bipolar transistor Q _i1 ～Q _i3 Capacitance C _i1 Capacitance C _i2 PMOS transistor M _i10 PMOS transistor M _i11 PMOS transistor M _i12 And resistance R _i1 ～R _i4 ；

NMOS transistor M _i12 Is connected with bias voltage V _iB Are connected;

bipolar transistor Q _i1 Emitter pass resistance R of (2) _i2 Grounding;

PMOS transistor M _i3 Drain electrode of (d) bipolar transistor Q _i2 Is identical to the collector and base of (a)Time and operational amplifier AMP _i1 Is connected with the inverting input terminal of the circuit;

PMOS transistor M _i5 For outputting bias current IB ₁ ；

PMOS transistor M _i9 For outputting bias current IB ₂ ；

6. The programmable threshold loss of signal detection circuit with temperature and process compensation of claim 5, wherein the bias Current source IBias Current provides a bias Current IB proportional to absolute temperature to the pre-op AMP ₁ The gain of the pre-operational amplifier AMP is made independent of temperature, and a bias current IB is introduced ₁ The gain of post AMP is:

wherein n is a resistor R _i3 And R is _i2 Resistance ratio of n=r _i3 /R _i2 M is the number ratio of the transistors participating in the operation, is a bipolar transistor Q _i2 Number of (A)>Is a bipolar transistor Q _i1 Number of R _S Is a source negative feedback resistor of a bipolar transistor in a conduction branch;

7. The programmable threshold loss of signal detection circuit with temperature and process compensation of claim 1, wherein the comparator COMP comprises a PMOS transistor M _c1 ～M _c7 Current source I _c1 ～I _c12 Inverter A _c1 Switch K with complementary switches _c1 ～K _c6 And a switch

each switch is correspondingly connected with one current source;