CN115810652A - Semiconductor device, protection circuit, and method for manufacturing semiconductor device - Google Patents
Semiconductor device, protection circuit, and method for manufacturing semiconductor device Download PDFInfo
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- CN115810652A CN115810652A CN202210172025.4A CN202210172025A CN115810652A CN 115810652 A CN115810652 A CN 115810652A CN 202210172025 A CN202210172025 A CN 202210172025A CN 115810652 A CN115810652 A CN 115810652A
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Abstract
Embodiments provide a semiconductor device with high dimensional controllability, a protection circuit, and a method for manufacturing the semiconductor device. The semiconductor device of the embodiment includes a 1 st semiconductor layer, a 2 nd semiconductor layer, a 3 rd semiconductor layer, a gate electrode, a 1 st layer, and an insulating layer. The 1 st semiconductor layer has a 1 st conductivity type. The 2 nd semiconductor layer is disposed on the 1 st semiconductor layer and has a 2 nd conductivity type. The 3 rd semiconductor layer is provided on the 1 st semiconductor layer, is arranged in parallel with the 2 nd semiconductor layer in the 1 st direction, and has a 2 nd conductivity type. The gate electrode is disposed on the 1 st semiconductor layer and between the 2 nd and 3 rd semiconductor layers. The 1 st layer has a lower impurity concentration than the 2 nd semiconductor layer, is provided on the 1 st semiconductor layer, and has one end in contact with the 2 nd semiconductor layer. The insulating layer is arranged on the 1 st layer, and one end of the insulating layer is connected with the 2 nd semiconductor layer.
Description
[ reference to related applications ]
The present application enjoys priority of application based on Japanese patent application No. 2021-149536 (application date: 9/14/2021) and Japanese patent application No. 2021-201871 (application date: 12/13/2021). The present application incorporates the entire contents of the base application by reference thereto.
Technical Field
Embodiments of the present invention relate to a semiconductor device, a protection circuit, and a method for manufacturing a semiconductor device.
Background
A protection circuit for protecting an electronic device from a surge such as electrostatic discharge may include a transistor for performing a switching operation so as to prevent the input of the surge to the electronic device, and a protection resistor for protecting the transistor. As a method for forming such a protective resistor, a method using a silicide block is known. However, the conventional method has a problem that it is difficult to control the size of the protection resistor.
Disclosure of Invention
The present invention addresses the problem of providing a protection circuit with high dimensional controllability and a method for manufacturing a semiconductor device.
A semiconductor device according to one embodiment of the present invention includes a 1 st semiconductor layer, a 2 nd semiconductor layer, a 3 rd semiconductor layer, a gate electrode, a 1 st layer, and an insulating layer. The 1 st semiconductor layer has a 1 st conductivity type. The 2 nd semiconductor layer is disposed on the 1 st semiconductor layer and has a 2 nd conductivity type. The 3 rd semiconductor layer is provided on the 1 st semiconductor layer, is arranged in parallel with the 2 nd semiconductor layer in the 1 st direction, and has a 2 nd conductivity type. The gate electrode is disposed on the 1 st semiconductor layer and between the 2 nd and 3 rd semiconductor layers. The 1 st layer has a lower impurity concentration than the 2 nd semiconductor layer, is provided on the 1 st semiconductor layer, and has one end in contact with the 2 nd semiconductor layer. The insulating layer is arranged on the 1 st layer, and one end of the insulating layer is connected with the 2 nd semiconductor layer.
Drawings
Fig. 1 is a diagram showing an example of a usage form of the protection circuit according to the embodiment.
Fig. 2 is a plan view showing an example of the configuration of the protection circuit according to the embodiment.
Fig. 3 isbase:Sub>A sectional viewbase:Sub>A-base:Sub>A in fig. 2 of the protection circuit of the embodiment.
Fig. 4 is a B-B sectional view of the protection circuit of the embodiment in fig. 2.
Fig. 5 (a) to (E) are sectional views B-B in fig. 2 showing an example of the method for manufacturing the semiconductor device according to the embodiment.
Fig. 6 (a) to (E) are cross-sectional views C-C in fig. 2 showing an example of the method of manufacturing the semiconductor device according to the embodiment.
Detailed Description
Embodiments of the present invention will be described below with reference to the drawings. The present invention is not limited to the embodiments. Further, the constituent elements of the embodiments include those which can be easily conceived by a practitioner or those which are substantially the same.
Fig. 1 is a diagram showing an example of a usage mode of the protection circuit 1 according to the embodiment. The protection circuit 1 of the present embodiment protects a predetermined electronic device (for example, a processor, a memory, or the like) from a surge such as an Electro-Static Discharge (ESD). In the configuration illustrated in fig. 1, a plurality of (4 in this example) protection circuits 1 are connected in parallel between a ground electrode and a lead wire 10 connected to an electronic device to be protected and through which an external current flows.
Each protection circuit 1 includes a transistor 11 and a protection resistor 12. The transistor 11 is a switching element that operates according to the magnitude of the surge voltage or the surge current, and operates to conduct the surge current to the ground electrode when the surge current or the surge voltage exceeds a threshold value. The protection resistor 12 is a resistor connected between the wire 10 and the transistor 11, and has an effect of preventing the transistor 11 from being damaged by a surge current. The protection resistors 12 are provided for the plurality of protection circuits 1, respectively, and each protection resistor 12 exerts a buffering effect of attenuating the surge current, thereby suppressing the surge current from concentrating on 1 protection circuit 1 (transistor 11).
Fig. 1 illustrates a case where the Transistor 11 is an N-channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), but the configuration of the Transistor 11 is not limited thereto. When the transistor 11 is an N-channel MOSFET, the drain of the transistor 11 is connected to the protection resistor 12, the source is connected to the ground electrode, and the gate is input with the ground voltage. Next, a case where the transistor 11 is an N-channel MOSFET will be described as an example.
Fig. 2 is a plan view showing an example of the configuration of the protection circuit 1 according to the embodiment. Fig. 3 isbase:Sub>A sectional viewbase:Sub>A-base:Sub>A in fig. 2 of the protection circuit 1 of the embodiment. Fig. 4 is a B-B cross-sectional view of the protection circuit 1 of the embodiment in fig. 2. In the figure, the X direction corresponds to the left-right direction of the paper surface (the arrangement direction of the transistor 11 and the protection resistor 12), the Y direction corresponds to the direction perpendicular to the paper surface (the width direction of the transistor 11 or the protection resistor 12), and the Z direction corresponds to the direction perpendicular to the XY plane (the stacking direction). The X direction is an example of the 1 st direction, the Y direction is an example of the 2 nd direction, and the Z direction is an example of the 3 rd direction.
As shown in fig. 2 and 3, the protection circuit 1 includes a transistor 11, a protection resistor 12, a 1 st contact 21, a 2 nd contact 22, a 1 st insulating portion 25, and a 2 nd insulating portion 26. The 1 st contact 21 is connected to the lead wire 10, and the 2 nd contact 22 is connected to a ground electrode.
The transistor 11 illustrated here is an N-channel MOSFET, and includes, as shown in fig. 3, a gate electrode 31, an oxide insulating film 32, insulating portions 33 and 34, a drain electrode 41, a source electrode 42 (an example of a 1 st region), a P-type semiconductor layer 55 (an example of a 1 st semiconductor layer), an N-type diffusion layer 56 (an example of a 2 nd semiconductor layer or a diffusion layer), and an N-type diffusion layer 57 (an example of a 3 rd semiconductor layer).
The P-type semiconductor layer 55 is a region which becomes an inversion layer in accordance with a voltage input to the gate electrode 31, and contains an impurity such as B at a predetermined concentration. The N-type diffusion layer 56 in contact with the drain electrode 41 is in contact with a resistive layer 63 of the protective resistor 12 described below. The N-type diffusion layer 57 in contact with the source electrode 42 is connected via the 2 nd contact 22 and the ground electrode.
As shown in fig. 2 to 4, the protective resistor 12 includes a trench portion 61, an insulating layer 62, a resistive layer 63 (an example of a 1 st layer), a semiconductor layer 65 (an example of a 4 th semiconductor layer), and a silicide layer 66. Silicide layer 66 (an example of the 2 nd region) is in contact with 1 st contact 21 and semiconductor layer 65. The 1 st contact 21, the silicide layer 66, and the semiconductor layer 65 constitute an input portion 70 that conducts an external current flowing through the conductive line 10 (fig. 1) to the inside of the protection circuit 1. The semiconductor layer 65 may be the same semiconductor layer as the N-type diffusion layer 57 or may be a different semiconductor layer from the N-type diffusion layer 57. In addition, the semiconductor layer 65 may be a conductive layer having higher electrical conductivity than the N-type diffusion layer 57.
The trench portion 61 is formed in the N-type diffusion layer 56 so as to separate the input portion 70 from the transistor 11. That is, the Trench portion 61 is a structure similar to so-called STI (Shallow Trench Isolation). An insulating layer 62 and a resistive layer 63 are formed inside the groove portion 61 of the present embodiment. As shown in fig. 4, the groove 61 of the present embodiment has an inverted trapezoidal cross-sectional shape along the YZ plane. That is, the width Wt of the opening of the groove 61 is larger than the width Wb of the bottom 71 of the groove 61.
The insulating layer 62 is made of an insulating material, for example, siO 2 SiN, etc. as a main component.
The resistive layer 63 is a region having a prescribed resistance value (electrical conductivity). The resistance value of resistive layer 63 is set to a value that can protect transistor 11 from a surge current input from input unit 70. The resistance layer 63 of the present embodiment has a higher resistance value than the N-type diffusion layer 56 and a lower resistance value than the insulating layer 62.
The resistive layer 63 and the N-type diffusion layer 56 of the present embodiment contain impurities (e.g., B) contained in the P-type semiconductor layer 55, and the impurity concentration of the resistive layer 63 is lower than the impurity concentration of the N-type diffusion layer 56. Such adjustment of the impurity concentration can be performed with relatively high accuracy by a known ion implantation method or the like. The impurity contained in the resistive layer 63 is not limited to the above, and may vary depending on the structure of the transistor 11. For example, when the transistor 11 is a P channel MOSFET, impurities such As and P contained in the N-type semiconductor layer are contained in the resistive layer and the diffusion layer.
In addition, resistive layer 63 of the present embodiment is formed on bottom portion 71 of groove portion 61. By forming the resistive layer 63 at such a position, the manufacturability of the protective resistor 12 (protective circuit 1) is improved, but the position where the resistive layer 63 is formed is not limited to this. For example, the resistive layer 63 may be formed on the side surface portion 72 of the groove 61 or the center portion of the insulating layer 62.
By forming the protection resistor 12 with a structure similar to STI as described above, the dimensional controllability of the protection resistor 12 can be improved as compared with a method using a silicide block or the like that needs to take into consideration the amount of penetration of liquid or the like. In addition, by improving the dimensional controllability, an extra margin in design can be reduced. Further, with the structure in which the protective resistor 12 includes the resistor layer 63 having an impurity concentration lower than that of the N-type diffusion layer 56, the protective resistor 12 having a capacitance (length in the X direction) smaller than that of the conventional resistor can have a resistance value equivalent to that of the conventional resistor. This makes it possible to reduce the size of the entire protection circuit 1.
Next, a method for manufacturing the protection circuit 1 as described above will be described.
Fig. 5 is a sectional view B-B in fig. 2 showing an example of a method for manufacturing the protection circuit 1 according to the embodiment. Fig. 6 is a cross-sectional view taken along line C-C in fig. 2, showing an example of a method for manufacturing the protection circuit 1 according to the embodiment. Fig. 5 (a) to (E) show, as an example, changes in YZ plane of a portion where the protection resistor 12 is formed as the manufacturing method of the present embodiment proceeds. Fig. 6 (a) to (E) show an example of changes in the XZ plane of the portion where the protective resistor 12 is formed as the manufacturing method of the present embodiment proceeds.
First, as shown in fig. 5 a and 6 a, an amorphous silicon layer 101 is formed on the upper surface of the P-type semiconductor layer 55, a resist 102 is formed on a predetermined portion (a portion corresponding to the resistor layer 63) on the amorphous silicon layer 101, and then RIE (Reactive Ion Etching) is performed. As a result, as shown in fig. 5 (B) and 6 (B), an amorphous silicon layer 101 having a thickness corresponding to the thickness of the resist 102 shown in fig. 5 (a) and 6 (B) remains on the P-type semiconductor layer 55. The amorphous silicon layer 101 is, for example, a 1 st mask (mask) layer.
Next, as shown in fig. 5 (B) and 6 (B), an SiN layer 105 is formed on the P-type semiconductor layer 55 where the amorphous silicon layer 101 remains, a resist 103 is formed on an outer edge portion of the SiN layer 105, and then RIE is performed. The SiN layer 105 is, for example, a 2 nd mask layer. In this case, the resist 102 shown in fig. 5B corresponds to the region outside the groove 61 in the Y direction, and the resist 102 shown in fig. 6B corresponds to the region outside the groove 61 in the X direction (the N-type diffusion layer 56 and the semiconductor layer 65). As a result, as shown in fig. 5 (C) and 6 (C), the groove 61 having a depth corresponding to the thickness of the resist 102 shown in fig. 5 (B) and 6 (B) is formed. In this case, since the distance (depth) from the upper surface is larger in terms of the nature of the RIE process, etching becomes more difficult, and the shape of the groove portion 61 naturally becomes an inverted trapezoid. Since only the P-type semiconductor layer 55 having the thickness of the amorphous silicon layer 101 shown in fig. 5 (B) and 6 (B) is not etched, a convex portion 110 in which the P-type semiconductor layer 55 bulges upward is formed at the bottom of the trench portion 61. The convex portion 110 is formed by the 1 st portion and the 2 nd portion located at a deeper position than the 1 st portion so that the 1 st portion protrudes.
Next, as shown in fig. 5C and 6C, the inside of the groove portion 61 is filled with NSG (Non-doped Silicate Glass) or the like to form an insulating layer 62.
Then, as shown in fig. 5 (D) and 6 (D), a resist 104 is formed on the outer edge portion of the insulating layer 62, ion implantation is performed, and an ionized substance (for example, BF) obtained by ionizing an impurity (for example, B) is performed 3 Gas, etc.) into the convex portion 110. In this case, the ion implantation is performed so that the impurity concentration of convex portion 110 is lower than the impurity concentration of N-type diffusion layer 56.
As a result of the above process, as shown in fig. 5 (E) and 6 (E), a resistive layer 63 having an impurity concentration lower than that of N-type diffusion layer 56 is formed at the bottom of trench portion 61.
After the insulating layer 62 and the resistive layer 63 are formed in this manner, a semiconductor layer 65 and a silicide layer 66 are formed by a suitable semiconductor manufacturing process, thereby forming the protective resistor 12. Then, the transistor 11 is formed using a suitable semiconductor manufacturing process. Transistor 11 may also be formed simultaneously with semiconductor layer 65 and silicide layer 66.
As described above, the manufacturing method of the present embodiment includes the steps of: forming a trench portion 61 in the N-type diffusion layer 56, the trench portion dividing the input portion 70 and the transistor 11; a convex portion 110 is formed at the bottom of the groove portion 61; and forming the resistive layer 63 by implanting ions into the convex portions 110. This enables the size of the protection resistor 12 to be controlled with high accuracy, and thus, an extra design margin can be reduced. Further, since the protective resistor 12 can be configured to include the resistor layer 63 having a lower impurity concentration than the N-type diffusion layer 56, the same resistance value as that of the conventional protective resistor 12 can be realized with a smaller capacitance (length in the X direction) than that of the conventional protective resistor. This makes it possible to reduce the size of the entire protection circuit 1.
Several embodiments of the present invention have been described, but these embodiments are only provided as examples and are not intended to limit the scope of the invention. These novel embodiments may be implemented in other various forms, and various omissions, substitutions, and changes may be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.
[ description of symbols ]
1. Protective circuit
10. Conducting wire
11. Transistor with a metal gate electrode
12. Protective resistor
21. 1 st contact
22. 2 nd contact
25. 1 st insulating part
26. 2 nd insulating part
31. Grid electrode
32. Oxide insulating film
33,34 insulating part
41. Drain electrode
42. Source electrode
55 P-type semiconductor layer
56, 57N type diffusion layer
61. Groove part
62. Insulating layer
63. Resistance layer
65. Semiconductor layer
66. Silicide layer
70. Input unit
71. Bottom part
72. Side surface part
101. Amorphous silicon layer
102. Corrosion-resistant
105 SiN layer
110. A convex part.
Claims (10)
1. A semiconductor device, comprising:
a 1 st semiconductor layer of a 1 st conductivity type having a 1 st impurity concentration;
a 2 nd semiconductor layer of a 2 nd conductivity type different from the 1 st conductivity type, provided on the 1 st semiconductor layer, having a 2 nd impurity concentration;
a 3 rd semiconductor layer of the 2 nd conductivity type provided on the 1 st semiconductor layer, and arranged side by side with the 2 nd semiconductor layer in a 1 st direction;
a gate electrode provided between the 2 nd semiconductor layer and the 3 rd semiconductor layer, and provided above the 1 st semiconductor layer with a gate insulating film interposed therebetween;
a 1 st layer of the 2 nd conductivity type provided on the 1 st semiconductor layer, having one end in contact with the 2 nd semiconductor layer, and having a 3 rd impurity concentration lower than the 2 nd impurity concentration of the 2 nd semiconductor layer; and
and an insulating layer provided on the 1 st layer and having one end in contact with the 2 nd semiconductor layer.
2. The semiconductor device according to claim 1, wherein: the gate electrode has a gate length extending in the 1 st direction and a gate width extending in the 2 nd direction intersecting the 1 st direction, and
the width of the insulating layer in the 2 nd direction is: the width of the layer is increased as the layer is separated in a 3 rd direction with respect to a side closer to the 1 st layer, and the 3 rd direction intersects with the 1 st direction and the 2 nd direction.
3. The semiconductor device according to claim 1, further comprising a 4 th semiconductor layer, wherein the 4 th semiconductor layer is in contact with the other end of the 1 st layer and is in contact with the other end of the insulating layer.
4. The semiconductor device according to claim 3, further comprising:
a 1 st region disposed on the 3 rd semiconductor layer;
the 1 st contact is connected with the 1 st area;
a 2 nd region disposed on the 4 th semiconductor layer; and
and the 2 nd contact is connected with the 2 nd area.
5. The semiconductor device according to claim 4, wherein: the other end of the insulating layer is connected with the No. 2 region.
6. The semiconductor device according to claim 1, wherein: the gate electrode has a gate length extending in the 1 st direction and a gate width extending in the 2 nd direction intersecting the 1 st direction, and
the semiconductor device includes: a 1 st surface including an interface between the 1 st semiconductor layer and the gate insulating film, wherein a 1 st distance from the 1 st layer to the 1 st surface in a 3 rd direction intersecting the 1 st direction and the 2 nd direction is longer than a 2 nd distance from the interface to the gate electrode in the 3 rd direction.
7. The semiconductor device according to claim 1, wherein:
the gate electrode has a gate length extending in the 1 st direction and a gate width extending in the 2 nd direction intersecting the 1 st direction, and
the insulating layer has: a 1 st portion contiguous with said 1 st layer; and a 2 nd portion, a 3 rd direction crossing the 1 st direction and the 2 nd direction being different from the 1 st layer;
the 2 nd direction width of the 1 st portion is smaller than the 2 nd direction width of the 2 nd portion.
8. The semiconductor device according to claim 7, wherein:
the distance from the 1 st portion to the 3 rd direction of the 1 st surface including the interface between the 1 st semiconductor layer and the gate insulating layer is larger than the distance from the 2 nd portion to the 3 rd direction of the 1 st surface.
9. A protection circuit, comprising:
a transistor having a source and a drain; and
a protection resistor connected between an input part for inputting an external current and the transistor; and is
The protection resistor includes:
a trench portion formed between the input portion and the transistor;
an insulating layer formed inside the groove portion; and
and a resistance layer formed inside the trench portion, having a resistance value higher than the drain and lower than the insulation layer.
10. A method for manufacturing a semiconductor device, comprising:
forming a 1 st mask layer on the 1 st semiconductor layer,
forming a 1 st resist on a portion of the 1 st mask layer,
etching a portion of the 1 st mask layer exposed from the 1 st resist,
forming a 2 nd mask layer on the 1 st semiconductor layer and on the 1 st mask layer,
forming a 2 nd resist on a portion of the 2 nd mask layer,
etching the 2 nd mask layer exposed from the 2 nd resist, the 1 st semiconductor layer exposed from the 2 nd mask layer by etching the 2 nd mask layer, and the 1 st mask layer, and further etching the 1 st semiconductor layer exposed from the 1 st mask layer by etching the 1 st mask layer, to form a 1 st portion and a 2 nd portion deeper than the 1 st portion in the 1 st semiconductor layer;
forming an insulating layer on the 1 st and 2 nd portions,
forming a 3 rd resist on a portion of the insulating layer,
ion implantation is performed on the 1 st portion from the insulating layer exposed from the 3 rd resist to form a 2 nd semiconductor layer.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2021-149536 | 2021-09-14 | ||
| JP2021149536 | 2021-09-14 | ||
| JP2021-201871 | 2021-12-13 | ||
| JP2021201871A JP2023042501A (en) | 2021-09-14 | 2021-12-13 | Semiconductor device, protection circuit and manufacturing method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115810652A true CN115810652A (en) | 2023-03-17 |
Family
ID=85482193
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210172025.4A Pending CN115810652A (en) | 2021-09-14 | 2022-02-24 | Semiconductor device, protection circuit, and method for manufacturing semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN115810652A (en) |
| TW (1) | TWI789257B (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8648419B2 (en) * | 2010-01-20 | 2014-02-11 | Freescale Semiconductor, Inc. | ESD protection device and method |
| JP5714280B2 (en) * | 2010-09-17 | 2015-05-07 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | Semiconductor device |
| US9356012B2 (en) * | 2011-09-23 | 2016-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | High voltage ESD protection apparatus |
| TWI521659B (en) * | 2013-05-02 | 2016-02-11 | 乾坤科技股份有限公司 | Current conducting element |
-
2022
- 2022-02-24 CN CN202210172025.4A patent/CN115810652A/en active Pending
- 2022-02-25 TW TW111107088A patent/TWI789257B/en active
Also Published As
| Publication number | Publication date |
|---|---|
| TWI789257B (en) | 2023-01-01 |
| TW202312417A (en) | 2023-03-16 |
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