TWI789257B - Semiconductor device, protection circuit, and manufacturing method of semiconductor device - Google Patents
Semiconductor device, protection circuit, and manufacturing method of semiconductor device Download PDFInfo
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Abstract
實施方式提供一種尺寸控制性較高之半導體裝置、保護電路及半導體裝置之製造方法。 實施方式之半導體裝置包含第1半導體層、第2半導體層、第3半導體層、閘極電極、第1層及絕緣層。第1半導體層具有第1導電型。第2半導體層設置於第1半導體層上,具有第2導電型。第3半導體層設置於第1半導體層上,與第2半導體層於第1方向上並排設置,具有第2導電型。閘極電極於第1半導體層上,設置於第2半導體層與第3半導體層之間。關於第1層,雜質濃度較第2半導體層低,設置於第1半導體層上,一端與第2半導體層相接。絕緣層設置於第1層上,一端與第2半導體層相接。 Embodiments provide a semiconductor device with high dimensional control, a protection circuit, and a method of manufacturing the semiconductor device. A semiconductor device according to an embodiment includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a gate electrode, a first layer, and an insulating layer. The first semiconductor layer has a first conductivity type. The second semiconductor layer is disposed on the first semiconductor layer and has a second conductivity type. The third semiconductor layer is provided on the first semiconductor layer, arranged side by side with the second semiconductor layer in the first direction, and has the second conductivity type. The gate electrode is disposed on the first semiconductor layer and between the second semiconductor layer and the third semiconductor layer. The first layer has a lower impurity concentration than the second semiconductor layer, is provided on the first semiconductor layer, and has one end in contact with the second semiconductor layer. The insulating layer is provided on the first layer, and one end is in contact with the second semiconductor layer.
Description
本發明之實施方式係關於一種半導體裝置、保護電路及半導體裝置之製造方法。Embodiments of the present invention relate to a semiconductor device, a protection circuit, and a method for manufacturing the semiconductor device.
於保護電子器件免受靜電放電等突波之損傷之保護電路中,有時會設置進行開關動作以免突波向電子器件輸入之電晶體、及用以保護該電晶體之保護電阻。作為形成此種保護電阻之方法,已知有利用矽化物塊之方法。然而,若採用先前之方法,則存在難以控制保護電阻之尺寸之問題。In the protection circuit for protecting electronic devices from damage caused by surges such as electrostatic discharge, transistors for switching to prevent surges from being input to electronic devices and protection resistors for protecting the transistors are sometimes installed. As a method of forming such a protective resistor, a method using a silicide block is known. However, if the previous method is adopted, there is a problem that it is difficult to control the size of the protection resistor.
本發明所欲解決之問題在於,提供一種尺寸控制性較高之保護電路及保護電路之製造方法。The problem to be solved by the present invention is to provide a protection circuit with high dimensional control and a method of manufacturing the protection circuit.
本發明之一個實施方式之半導體裝置包含第1半導體層、第2半導體層、第3半導體層、閘極電極、第1層及絕緣層。第1半導體層具有第1導電型。第2半導體層設置於第1半導體層上,具有第2導電型。第3半導體層設置於第1半導體層上,與第2半導體層於第1方向上並排設置,具有第2導電型。閘極電極於第1半導體層上,設置於第2半導體層與第3半導體層之間。關於第1層,雜質濃度較第2半導體層低,設置於第1半導體層上,一端與第2半導體層相接。絕緣層設置於第1層上,一端與第2半導體層相接。A semiconductor device according to one embodiment of the present invention includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a gate electrode, a first layer, and an insulating layer. The first semiconductor layer has a first conductivity type. The second semiconductor layer is disposed on the first semiconductor layer and has a second conductivity type. The third semiconductor layer is provided on the first semiconductor layer, arranged side by side with the second semiconductor layer in the first direction, and has the second conductivity type. The gate electrode is disposed on the first semiconductor layer and between the second semiconductor layer and the third semiconductor layer. The first layer has a lower impurity concentration than the second semiconductor layer, is provided on the first semiconductor layer, and has one end in contact with the second semiconductor layer. The insulating layer is provided on the first layer, and one end is in contact with the second semiconductor layer.
以下,參照圖式對本發明之實施方式進行說明。再者,並不由實施方式限定本發明。又,實施方式之構成要素中包含業者可容易地想到者或實質上相同者。Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, this invention is not limited by embodiment. In addition, the constituent elements of the embodiment include those that can be easily imagined by a person in the business or those that are substantially the same.
圖1係表示實施方式之保護電路1之利用形態的一例之圖。本實施方式之保護電路1係保護特定之電子器件(例如,處理器、記憶體等)免受靜電放電(ESD:Electro-Static Discharge)等突波之損傷者。於圖1所例示之構成中,與作為保護對象之電子器件連接而供外部電流流通之導線10與接地電極之間並聯連接有複數個(於本例中為4個)保護電路1。FIG. 1 is a diagram showing an example of the utilization form of the
各保護電路1包含電晶體11與保護電阻12。電晶體11係根據突波電壓或突波電流之大小而動作之開關元件,以於突波電流或突波電壓超過閾值之情形時將突波電流向接地電極傳導之方式動作。保護電阻12係連接於導線10與電晶體11之間之電阻,具有避免電晶體11因突波電流而受到損傷之效果。又,保護電阻12係針對複數個保護電路1分別設置,藉由各保護電阻12發揮使突波電流衰減之緩衝效果,能抑制突波電流集中於1個保護電路1(電晶體11)。Each
圖1中例示出了電晶體11為N通道型MOSFET(Metal-Oxide -Semiconductor Field Effect Transistor,金屬氧化物半導體場效應電晶體)之情形,但電晶體11之構成並不限定於此。於電晶體11為N通道型MOSFET之情形時,電晶體11之汲極與保護電阻12連接,源極與接地電極連接,閘極被輸入接地電壓。以下,以電晶體11為N通道型MOSFET之情形為例進行說明。FIG. 1 exemplifies the case where the
圖2係表示實施方式之保護電路1之構成的一例之俯視圖。圖3係實施方式之保護電路1之圖2中之A-A剖視圖。圖4係實施方式之保護電路1之圖2中之B-B剖視圖。圖中,X方向對應於紙面之左右方向(電晶體11與保護電阻12之排列方向),Y方向對應於與紙面正交之方向(電晶體11或保護電阻12之寬度方向),Z方向對應於與XY平面正交之方向(積層方向)。X方向係第1方向之一例,Y方向係第2方向之一例,Z方向係第3方向之一例。FIG. 2 is a plan view showing an example of the configuration of the
如圖2及圖3所示,保護電路1包含電晶體11、保護電阻12、第1接點21、第2接點22、第1絕緣部25及第2絕緣部26。第1接點21與上述導線10連接,第2接點22與接地電極連接。As shown in FIGS. 2 and 3 , the
此處所例示之電晶體11係N通道型MOSFET,如圖3所示,包含閘極電極31、氧化絕緣膜32、絕緣部33、34、汲極電極41、源極電極42(第1區域之一例)、P型半導體層55(第1半導體層之一例)、N型擴散層56(第2半導體層或擴散層之一例)、及N型擴散層57(第3半導體層之一例)。The
P型半導體層55係根據輸入至閘極電極31之電壓而成為反相層之區域,以特定之濃度包含B等雜質。與汲極電極41接觸之N型擴散層56和下述保護電阻12之電阻層63接觸。與源極電極42接觸之N型擴散層57經由第2接點22和接地電極連接。The P-
如圖2~圖4所示,保護電阻12包含溝槽部61、絕緣層62、電阻層63(第1層之一例)、半導體層65(第4半導體層之一例)及矽化物層66。矽化物層66(第2區域之一例)與第1接點21及半導體層65接觸。第1接點21、矽化物層66及半導體層65構成了將流經導線10(圖1)之外部電流向保護電路1之內部傳導之輸入部70。再者,半導體層65可為與N型擴散層57相同之半導體層,亦可為與N型擴散層57不同之半導體層。又,半導體層65亦可為具有較N型擴散層57高之電傳導率之導電層。As shown in FIGS. 2 to 4 , the
溝槽部61於N型擴散層56中以將輸入部70與電晶體11分開之方式形成。即,溝槽部61係形成與所謂之STI(Shallow Trench Isolation,淺溝槽隔離)類似之構造者。於本實施方式之溝槽部61之內部形成有絕緣層62及電阻層63。本實施方式之溝槽部61如圖4所示,沿著YZ平面之剖面形狀為倒梯形。即,溝槽部61之開口部之寬度Wt大於溝槽部61之底部71之寬度Wb。The
絕緣層62由絕緣性之材料構成,例如可將SiO
2、SiN等作為主成分而構成。
The
電阻層63係具有特定之電阻值(電傳導率)之區域。電阻層63之電阻值被設定為能保護電晶體11免受自輸入部70輸入之突波電流之損傷之值。本實施方式之電阻層63之電阻值較N型擴散層56高,較絕緣層62低。The
本實施方式之電阻層63及N型擴散層56含有P型半導體層55中包含之雜質(例如B等),電阻層63之雜質濃度低於N型擴散層56之雜質濃度。此種雜質濃度之調整可採用公知之離子注入法等相對較高精度地進行。再者,電阻層63中包含之雜質並不限定於上述者,會根據電晶體11之構成而變化。例如,於電晶體11為P通道型MOSFET之情形時,N型半導體層中包含之As、P等雜質會包含於電阻層及擴散層中。The
又,本實施方式之電阻層63形成於溝槽部61之底部71。藉由將電阻層63形成於如此位置,保護電阻12(保護電路1)之製造性提高,但電阻層63之形成位置並不限定於此。例如,電阻層63亦可形成於溝槽部61之側面部72或絕緣層62之中央部。In addition, the
藉由如上文所述般利用與STI類似之構造形成保護電阻12,與需要考慮液體之滲入量等之使用矽化物塊之方法等相比,能提高保護電阻12之尺寸控制性。又,藉由此種尺寸控制性之提高,能削減設計上之多餘裕度。又,藉由保護電阻12包含雜質濃度較N型擴散層56低之電阻層63之構造,能以較先前小之容量(X方向上之長度)之保護電阻12實現與先前同等之電阻值。藉此,能使保護電路1整體小型化。By forming the
以下,對如上所述之保護電路1之製造方法進行說明。Hereinafter, a method of manufacturing the
圖5係表示實施方式之保護電路1之製造方法的一例之圖2中之B-B剖視圖。圖6係表示實施方式之保護電路1之製造方法的一例之圖2中之C-C剖視圖。於圖5(A)~(E)中,例示出了隨著本實施方式之製造方法之進行,供形成保護電阻12之部分之YZ平面上之變化。於圖6(A)~(E)中,例示出了隨著本實施方式之製造方法之進行,供形成保護電阻12之部分之XZ平面上之變化。FIG. 5 is a cross-sectional view along B-B in FIG. 2 showing an example of a method of manufacturing the
首先,如圖5(A)及圖6(A)所示,於P型半導體層55之上表面形成非晶矽層101,於非晶矽層101上之特定部分(與電阻層63對應之部分)形成抗蝕(resist)102,然後進行RIE(Reactive Ion Etching,反應性離子蝕刻)。藉此,如圖5(B)及圖6(B)所示,P型半導體層55上殘留具有與圖5(A)及圖6(B)所示之抗蝕102之厚度相應之厚度之非晶矽層101。非晶矽層101例如為第1遮罩(mask)層。First, as shown in FIG. 5(A) and FIG. 6(A), an
然後,如圖5(B)及圖6(B)所示,於殘留有非晶矽層101之P型半導體層55上形成SiN層105,於SiN層105之外緣部形成抗蝕103,然後進行RIE。SiN層105例如係第2遮罩層。此時,圖5(B)所示之抗蝕102係與溝槽部61之Y方向上之外側之區域對應之部分,圖6(B)所示之抗蝕102係與溝槽部61之X方向上之外側之區域(N型擴散層56及半導體層65)對應之部分。藉此,如圖5(C)及圖6(C)所示,形成與圖5(B)及圖6(B)所示之抗蝕102之厚度相應之深度之溝槽部61。此時,自RIE處理之性質上而言,距上表面之距離(深度)越大,越難加以蝕刻,因此溝槽部61之形狀自然成為倒梯形。又,圖5(B)及圖6(B)所示之非晶矽層101之厚度量之P型半導體層55未被蝕刻,因此於溝槽部61之底部形成P型半導體層55向上方鼓出而成之凸狀部110。凸狀部110為由第1部與較第1部位於更深位置之第2部以第1部突出之方式形成之構造。Then, as shown in FIG. 5(B) and FIG. 6(B), a
然後,如圖5(C)及圖6(C)所示,向溝槽部61之內部填充NSG(Non-doped Silicate Glass,無摻雜矽玻璃)等而形成絕緣層62。Next, as shown in FIG. 5(C) and FIG. 6(C), NSG (Non-doped Silicate Glass) or the like is filled inside the
然後,如圖5(D)及圖6(D)所示,於絕緣層62之外緣部形成抗蝕104,並進行離子注入,將由雜質(例如B等)離子化而成之離子化物質(例如BF
3氣體等)注入至凸狀部110。此時,離子注入係以使凸狀部110之雜質濃度低於N型擴散層56之雜質濃度之方式進行。
Then, as shown in FIG. 5(D) and FIG. 6(D), a resist 104 is formed on the outer edge of the insulating
藉由上述處理,如圖5(E)及圖6(E)所示,於溝槽部61之底部形成雜質濃度較N型擴散層56低之電阻層63。Through the above processing, as shown in FIG. 5(E) and FIG. 6(E), a
以上述方式形成絕緣層62及電阻層63後,採用合適之半導體製造製程形成半導體層65及矽化物層66,藉此形成保護電阻12。然後,採用合適之半導體製造製程形成電晶體11。電晶體11亦可與半導體層65及矽化物層66同時地形成。After the insulating
如上所述,本實施方式之製造方法包含如下步驟:於N型擴散層56形成將輸入部70與電晶體11分斷之溝槽部61;於溝槽部61之底部形成凸狀部110;及藉由向凸狀部110注入離子而形成電阻層63。藉此,能高精度地控制保護電阻12之尺寸,從而能削減設計上之多餘裕度。又,能形成保護電阻12包含雜質濃度較N型擴散層56低之電阻層63之構造,因此能以較先前小之容量(X方向上之長度)之保護電阻12實現與先前同等之電阻值。藉此,能使保護電路1整體小型化。As mentioned above, the manufacturing method of this embodiment includes the following steps: forming the
已對本發明之若干實施方式進行了說明,但該等實施方式僅作為示例而提出,並未意圖限定發明之範圍。該等新穎之實施方式可採用其他各種形態加以實施,可於不脫離發明主旨之範圍內進行各種省略、替換或變更。該等實施方式及其變形包含於發明之範圍及主旨中,並且包含於申請專利範圍所記載之發明及其同等之範圍內。Several embodiments of the present invention have been described, but these embodiments have been presented as examples only, and are not intended to limit the scope of the invention. These novel embodiments can be implemented in other various forms, and various omissions, substitutions, or changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the inventions described in the claims and their equivalent scopes.
[相關申請之參照] 本申請享受以日本專利申請2021-149536號(申請日:2021年9月14日)及日本專利申請2021-201871號(申請日:2021年12月13日)為基礎申請之優先權。本申請藉由參照該基礎申請而包含基礎申請之全部內容。 [Reference to related applications] This application enjoys the priority of the basic application based on Japanese Patent Application No. 2021-149536 (filing date: September 14, 2021) and Japanese Patent Application No. 2021-201871 (filing date: December 13, 2021). This application incorporates the entire content of the basic application by referring to this basic application.
1:保護電路
10:導線
11:電晶體
12:保護電阻
21:第1接點
22:第2接點
25:第1絕緣部
26:第2絕緣部
31:閘極電極
32:氧化絕緣膜
33,34:絕緣部
41:汲極電極
42:源極電極
55:P型半導體層
56,57:N型擴散層
61:溝槽部
62:絕緣層
63:電阻層
65:半導體層
66:矽化物層
70:輸入部
71:底部
72:側面部
101:非晶矽層
102:抗蝕
105:SiN層
110:凸狀部1: Protection circuit
10: wire
11: Transistor
12: Protection resistor
21: The first contact
22: The second contact
25: The first insulation part
26: The second insulation part
31: Gate electrode
32:
圖1係表示實施方式之保護電路之利用形態的一例之圖。 圖2係表示實施方式之保護電路之構成的一例之俯視圖。 圖3係實施方式之保護電路之圖2中之A-A剖視圖。 圖4係實施方式之保護電路之圖2中之B-B剖視圖。 圖5(A)~(E)係表示實施方式之半導體裝置之製造方法的一例之圖2中之B-B剖視圖。 圖6(A)~(E)係表示實施方式之半導體裝置之製造方法的一例之圖2中之C-C剖視圖。 FIG. 1 is a diagram showing an example of a usage form of a protection circuit according to an embodiment. FIG. 2 is a plan view showing an example of the configuration of the protection circuit of the embodiment. Fig. 3 is a cross-sectional view along A-A in Fig. 2 of the protection circuit of the embodiment. Fig. 4 is a cross-sectional view along B-B in Fig. 2 of the protection circuit of the embodiment. 5(A) to (E) are sectional views taken along line B-B in FIG. 2 showing an example of the method of manufacturing the semiconductor device according to the embodiment. 6(A) to (E) are cross-sectional views taken along line C-C in FIG. 2 showing an example of the manufacturing method of the semiconductor device according to the embodiment.
1:保護電路 1: Protection circuit
11:電晶體 11: Transistor
12:保護電阻 12: Protection resistor
21:第1接點 21: The first contact
22:第2接點 22: The second contact
25:第1絕緣部 25: The first insulation part
26:第2絕緣部 26: The second insulation part
31:閘極電極 31: Gate electrode
32:氧化絕緣膜 32: oxide insulating film
33,34:絕緣部 33,34: insulation part
41:汲極電極 41: Drain electrode
42:源極電極 42: Source electrode
55:P型半導體層 55: P-type semiconductor layer
56,57:N型擴散層 56,57: N-type diffusion layer
61:溝槽部 61: groove part
62:絕緣層 62: Insulation layer
63:電阻層 63: Resistance layer
65:半導體層 65: Semiconductor layer
66:矽化物層 66: Silicide layer
70:輸入部 70: input part
Claims (10)
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JP2021201871A JP2023042501A (en) | 2021-09-14 | 2021-12-13 | Semiconductor device, protection circuit and manufacturing method of semiconductor device |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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CN102412226A (en) * | 2010-09-17 | 2012-04-11 | 安森美半导体贸易公司 | Semiconductor device |
US20140147983A1 (en) * | 2010-01-20 | 2014-05-29 | Amaury Gendron | Esd protection device and method |
TWI521659B (en) * | 2013-05-02 | 2016-02-11 | 乾坤科技股份有限公司 | Current conducting element |
US20190123038A1 (en) * | 2011-09-23 | 2019-04-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | High Voltage ESD Protection Apparatus |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140147983A1 (en) * | 2010-01-20 | 2014-05-29 | Amaury Gendron | Esd protection device and method |
CN102412226A (en) * | 2010-09-17 | 2012-04-11 | 安森美半导体贸易公司 | Semiconductor device |
US20190123038A1 (en) * | 2011-09-23 | 2019-04-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | High Voltage ESD Protection Apparatus |
TWI521659B (en) * | 2013-05-02 | 2016-02-11 | 乾坤科技股份有限公司 | Current conducting element |
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