CN115802758A - Method for manufacturing three-dimensional memory - Google Patents

Method for manufacturing three-dimensional memory Download PDF

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Publication number
CN115802758A
CN115802758A CN202211486100.0A CN202211486100A CN115802758A CN 115802758 A CN115802758 A CN 115802758A CN 202211486100 A CN202211486100 A CN 202211486100A CN 115802758 A CN115802758 A CN 115802758A
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layer
dielectric layer
sacrificial layer
dielectric
etching
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王启光
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

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Abstract

The invention provides a manufacturing method of a three-dimensional memory. In the process of forming the sacrificial layer, the top sacrificial layer has a first etching selection ratio A to the bottom sacrificial layer, the top sacrificial layer has a second etching selection ratio B to the middle sacrificial layer, wherein A is not less than B and not more than 1, and A is not equal to 1, so that the etching rate of the sacrificial layer is changed in the process of removing the sacrificial layer by wet etching by changing the material components in the deposition stage of the sacrificial layer, the etching rate of the sacrificial layer positioned at the lower layer is higher than that of the sacrificial layer positioned at the upper layer, the difference of the etching rates can balance the difference of the etching rates of the lower sacrificial layer and the upper sacrificial layer caused by the etching load effect in the process, the damage of part of the charge blocking layer in contact with the upper sacrificial layer is reduced, the problem of uneven damage of the charge blocking layer at the upper position and the lower position is effectively solved, and the step covering capability of the charge blocking layer at the upper position and the lower position is improved.

Description

Method for manufacturing three-dimensional memory
Description of the cases
The application is a divisional application of Chinese patent application with the application date of 2020, 05 and 21, and the application number of 202010438263.6, entitled "manufacturing method of three-dimensional memory".
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a three-dimensional memory.
Background
In the prior art, a Flash Memory (Flash Memory) has a main function of maintaining stored information for a long time without power up, and has the advantages of high integration level, high access speed, easy erasing and rewriting and the like, so that the Flash Memory is widely applied to electronic products. In order to further increase the Bit Density (Bit Density) of the flash memory and reduce the Bit Cost (Bit Cost), a three-dimensional NAND flash memory is further proposed.
The storage structure is a key structure of a three-dimensional memory, and the commonly used storage structure comprises a charge blocking layer, a charge trapping layer, a tunneling layer and a channel layer, and has a function of controlling the charge storage of the memory. At present, the fabrication process of the memory structure in the three-dimensional NAND flash memory is generally to form a channel via in the stacked structure, and then sequentially deposit and form along the sidewall of the channel via.
The charge blocking layer in the memory structure is generally silicon dioxide with a high forbidden band width, mainly plays a role in blocking charges on the side of a grid electrode, and specifically has the following functions:
1. preventing charge tunneling from occurring between the storage structure and the gate in a program or erase operation, resulting in a program failure or an erase failure;
2. electrons are prevented from tunneling through the charge blocking layer into the gate layer in the memory structure due to thermal motion or radiation in the static state, causing threshold voltage drift.
However, since the charge blocking layer is formed before the gate layer, when the sacrificial layer is removed after the trench via process is completed, the formed charge blocking layer may be damaged, and due to an etching load effect (loading effect), the upper sacrificial layer is etched first, a portion of the charge blocking layer in contact with the upper sacrificial layer is damaged first, and relatively a portion of the charge blocking layer in contact with the lower sacrificial layer is damaged slightly, so that the thicknesses of the charge blocking layers in contact with the upper sacrificial layer and the lower sacrificial layer are not uniform, and a leakage risk of the back gate of the upper Word Line (WL) is increased.
In addition, as the damage of a part of the charge blocking layer in contact with the upper sacrificial layer is more, the grid electrode deepens towards the channel direction, so that the programming coupling effect of the upper word line is enhanced, and for TLC (3 bit/cell) or QLC (4 bit/cell) programming, the distance among a plurality of programming states of the upper word line is insufficient, and the data reading failure is easily caused.
Disclosure of Invention
The invention mainly aims to provide a manufacturing method of a three-dimensional memory, which aims to solve the problem that the manufacturing process of the three-dimensional memory in the prior art is easy to cause a large risk of electric leakage of an upper layer Word Line (WL) back gate.
In order to achieve the above object, according to an aspect of the present invention, there is provided a method for fabricating a three-dimensional memory, including the steps of: s1, forming a stacked structure on a substrate, wherein the stacked structure comprises sacrificial layers and isolation layers which are alternately stacked along a direction far away from the substrate, the sacrificial layers comprise a top sacrificial layer, a bottom sacrificial layer and a middle sacrificial layer positioned between the top sacrificial layer and the bottom sacrificial layer, the top sacrificial layer has a first etching selection ratio A to the bottom sacrificial layer, the top sacrificial layer has a second etching selection ratio B to the middle sacrificial layer, A is not less than B and not more than 1, and A is not equal to 1; s2, forming a channel through hole penetrating to the substrate in the stacked structure, and forming a storage structure on the side wall of the channel through hole, wherein the storage structure is provided with a charge blocking layer covering the side wall; s3, forming a common source groove penetrating through the substrate in the stacked structure, and performing wet etching on the sacrificial layers to remove the sacrificial layers; and S4, forming a control gate structure at a position corresponding to the sacrificial layer so as to enable the control gate structure to be in contact with the charge blocking layer, and forming a conductive channel in the common source trench.
Furthermore, the middle sacrificial layers are multiple layers, and the second etching selection ratio B of the top sacrificial layer to each middle sacrificial layer is reduced in sequence from top to bottom according to the sequence of each middle sacrificial layer.
Furthermore, the middle sacrificial layers are multilayer, the multilayer middle sacrificial layers comprise at least one upper middle sacrificial layer and at least one lower middle sacrificial layer, the etching selection ratio of the top sacrificial layer to each upper middle sacrificial layer is equal to 1, and the etching selection ratio of the top sacrificial layer to each lower middle sacrificial layer is less than 1.
Further, siN is deposited to form a sacrificial layer, and O is doped in the deposition process of the top sacrificial layer and/or the upper middle sacrificial layer.
Further, siN is adopted for deposition to form a sacrificial layer, and Si content in the SiN is increased in a deposition process of the top sacrificial layer and/or the upper middle sacrificial layer.
Further, siN deposition is adopted to form a sacrificial layer, and Ge elements are doped in the deposition process of the bottom sacrificial layer and/or the lower middle sacrificial layer.
Further, in step S3, wet etching is performed on the sacrificial layer by using an etching solution, where the etching solution includes a phosphoric acid aqueous solution, and preferably, the etching solution further includes a regulator, and the regulator is ammonium salt and/or sulfuric acid.
Further, the step of forming the memory structure comprises: a charge blocking layer, a charge trapping layer, a tunneling layer, and a channel layer are sequentially formed on sidewalls of the trench via.
Further, after the step of forming the common source trench, the step S3 further includes the steps of: and forming a doped region in the substrate, wherein the region is communicated with the common source groove, and the doping type of the doped region is opposite to that of the substrate.
Further, after the step of removing the sacrificial layer, the step S3 further includes a step of forming a selection gate dielectric layer on the doped region.
The technical scheme of the invention is applied, a manufacturing method of a three-dimensional memory is provided, in the process of forming a sacrificial layer, the sacrificial layer comprises a top sacrificial layer, a bottom sacrificial layer and a middle sacrificial layer positioned between the top sacrificial layer and the bottom sacrificial layer, the top sacrificial layer has a first etching selection ratio A to the bottom sacrificial layer, the top sacrificial layer has a second etching selection ratio B to the middle sacrificial layer, wherein A is less than or equal to B and less than or equal to 1, and A is not equal to 1; and because the upper charge blocking layer has smaller loss, charges in the trapping layer are more difficult to tunnel into the grid layer, so that the data retention characteristic of the upper storage unit is improved, the sub-wire interlayer coupling effect is reduced, the distance between programmed states is improved, and programming or erasing failure caused by the tunneling of the charges between the blocking layer and the grid is reduced.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of the invention, and are included to illustrate an exemplary embodiment of the invention and not to limit the invention.
In the drawings:
fig. 1 is a schematic cross-sectional view illustrating a substrate after a stacked structure is formed on a surface of the substrate in a method for fabricating a three-dimensional memory according to an embodiment of the present disclosure;
FIG. 2 is a schematic cross-sectional view of a substrate after forming a memory structure in the stacked structure of FIG. 1;
FIG. 3 is a schematic diagram illustrating a cross-sectional structure of a substrate after forming a common source trench in the stacked structure shown in FIG. 2;
FIG. 4 is a schematic cross-sectional view of the substrate after removing the sacrificial layer shown in FIG. 3;
FIG. 5 is a schematic diagram showing a cross-sectional structure of the body after forming a lower select gate dielectric layer on the surface of the substrate in the common source trench shown in FIG. 4;
FIG. 6 is a cross-sectional view of the substrate after forming a gate layer at the location of the sacrificial layer removed shown in FIG. 5;
FIG. 7 is a schematic cross-sectional view of the substrate after forming a conductive channel in the common source trench of FIG. 6;
fig. 8 shows a schematic cross-sectional structure of a portion of the control gate structure and its vicinity shown in fig. 7.
Wherein the figures include the following reference numerals:
10. a substrate; 20. a sacrificial layer; 210. a top sacrificial layer; 220. a bottom sacrificial layer; 230. an intermediate sacrificial layer; 30. an isolation layer; 40. a storage structure; 410. a charge blocking layer; 420. a charge trapping layer; 430. a tunneling layer; 440. a channel layer; 450. filling an oxide layer; 50. a common source trench; 60. a doped region; 70. selecting a gate dielectric layer; 80. a control gate structure; 810. a gate layer; 820. a high-K dielectric layer; 90. a sidewall insulating layer; 100. a conductive path.
Detailed Description
It should be noted that the embodiments and features of the embodiments of the present invention may be combined with each other without conflict. The present invention will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the invention herein. Moreover, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As introduced in the background art, due to an etching load effect (loading effect), a manufacturer of the memory structure 40 in the 3D NAND in the prior art completes etching the upper sacrificial layer 20 first, and a portion of the charge blocking layer 410 in contact with the upper sacrificial layer 20 is damaged first, and relatively, a portion of the charge blocking layer 410 in contact with the lower sacrificial layer 20 is damaged slightly, so that the thickness of the charge blocking layer 410 in contact with the upper sacrificial layer 20 and the lower sacrificial layer 20 is not uniform, and a leakage risk of a back gate of an upper Word Line (WL) is increased; in addition, since the charge blocking layer 410 in contact with the upper sacrificial layer 20 is damaged more, the gate extends deep in the channel direction, which results in an enhanced upper WL programming coupling effect and a reduced upper WL programming state margin.
The inventor of the present invention has studied the above problem and proposed a method for manufacturing a three-dimensional memory, as shown in fig. 1 to 8, comprising the steps of: s1, forming a stack structure on a substrate 10, wherein the stack structure comprises sacrificial layers 20 and isolation layers 30 which are alternately stacked along a direction far away from the substrate 10, the sacrificial layers 20 comprise top sacrificial layers 210, bottom sacrificial layers 220 and middle sacrificial layers 230 positioned between the top sacrificial layers 210 and the bottom sacrificial layers 220, the top sacrificial layers 210 have a first etching selection ratio A to the bottom sacrificial layers 220, the top sacrificial layers 210 have a second etching selection ratio B to the middle sacrificial layers 230, A is less than or equal to B and less than or equal to 1, and A is not equal to 1; s2, forming a channel through hole in the stacked structure, and forming a storage structure 40 on the side wall of the channel through hole, wherein the storage structure 40 is provided with a charge blocking layer 410 covering the side wall; s3, forming common source trenches 40 penetrating to the substrate 10 in the stacked structure, and performing wet etching on the sacrificial layers 20 to remove the sacrificial layers 20; and S4, forming a control gate structure 80 gate layer 810 at a position corresponding to the sacrificial layer 20, so that the control gate structure 80 gate layer 810 is in contact with the charge blocking layer 410, and forming the conductive channel 100 in the common source trench 40.
The top sacrificial layer 210 has a first etching selection ratio a to the bottom sacrificial layer 220, which can be understood as that under the same wet etching condition, the same etching solution etches the top sacrificial layer 210 and the bottom sacrificial layer 220 respectively, so that the top sacrificial layer 210 has a first etching rate, the bottom sacrificial layer 220 has a second etching rate, and the first etching selection ratio a is a ratio of the first etching rate to the second etching rate; similarly, the top sacrificial layer 210 has a second etching selectivity B to the middle sacrificial layer 230, which is to be understood that under the same wet etching condition, the same etching solution etches the middle sacrificial layer 230, so that the middle sacrificial layer 230 has a third etching rate, and the second etching selectivity B is a ratio of the first etching rate to the third etching rate.
In the manufacturing method, the etching rate of the lower sacrificial layer 20 and/or the upper sacrificial layer 20 is changed by changing the material composition in the deposition stage of the sacrificial layer 20, so that the etching rate of the lower sacrificial layer 20 is higher than that of the upper sacrificial layer 20, and the first etching selection ratio A and the second etching selection ratio B are obtained, and in the process of removing the sacrificial layer 20 by wet etching, the difference of the etching rates can balance the difference of the etching rates of the lower sacrificial layer 20 and the upper sacrificial layer 20 caused by the etching load effect, so that the damage of a part of the charge blocking layer 410 in contact with the upper sacrificial layer 20 is reduced, the problem of uneven damage of the charge blocking layer 410 in the upper and lower positions is effectively solved, and the step coverage capability of the charge blocking layer 410 in the upper and lower positions is improved; moreover, because the upper charge blocking layer 410 has small loss, charges in the trapping layer are more difficult to tunnel into the gate layer 810, so that the data retention characteristic of the upper storage unit is improved, the sub-line interlayer coupling effect is reduced, the distance between programmed states is improved, and programming or erasing failure caused by the tunneling of charges between the blocking layer and the gate is reduced.
An exemplary embodiment of a method of fabricating a three-dimensional memory provided according to the present invention will be described in more detail below. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
First, step S1 is performed: a stacked structure is formed on a substrate 10, the stacked structure comprises sacrificial layers 20 and isolation layers 30 which are alternately stacked along a direction far away from the substrate 10, the sacrificial layers 20 comprise top sacrificial layers 210, bottom sacrificial layers 220 and one or more middle sacrificial layers 230 positioned between the top sacrificial layers 210 and the bottom sacrificial layers 220, as shown in FIG. 1, the top sacrificial layers 210 have a first etching selection ratio A to the bottom sacrificial layers 220, the top sacrificial layers 210 have a second etching selection ratio B to the middle sacrificial layers 230, wherein A is less than or equal to B less than or equal to 1, and A is not equal to 1.
The material of the substrate 10 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide. In the present embodiment, the semiconductor substrate 10 is a P-type Si substrate 10.
In the above step S1, the isolation layer 30 and the sacrificial layer 20 can be formed by a conventional deposition process in the prior art, such as a chemical vapor deposition process. The number of the sacrificial layer 20 and the isolation layer 30 can be set by those skilled in the art according to practical requirements, and the isolation layer 30 can be SiO 2 The sacrificial layer 20 may be SiN, but is not limited to the above type, and those skilled in the art can reasonably select the types of the isolation layer 30 and the sacrificial layer 20 according to the prior art.
The intermediate sacrificial layer 230 may be one or more layers, and the etching rate of each layer may be partially the same for the plurality of intermediate sacrificial layers 230. In a preferred embodiment, the middle sacrificial layer 230 includes at least one upper middle sacrificial layer and at least one lower middle sacrificial layer, the etching selection ratio of the top sacrificial layer 210 to each upper middle sacrificial layer is equal to 1, and the etching selection ratio of the top sacrificial layer 210 to each lower middle sacrificial layer is less than 1. As the name implies, the lower middle sacrificial layer refers to the lower middle sacrificial layer 230 in the multi-layer middle sacrificial layer 230, and the upper middle sacrificial layer refers to the upper middle sacrificial layer 230 in the multi-layer middle sacrificial layer 230, i.e. any one of the upper middle sacrificial layers is located on the side of the lower middle sacrificial layer away from the substrate 10.
In the above embodiment, the etching rates of the top sacrificial layer 210 and the n upper middle sacrificial layers are S under the same wet etching condition, wherein n upper middle sacrificial layers and m lower middle sacrificial layers (n + m sacrificial layers 20 in total) are used for illustration 1 At this time, the etching selection ratio of the top sacrificial layer 210 to the upper middle sacrificial layer is equal to 1 (i.e. the second etching selection ratio B = 1), and the etching rates of the m lower middle sacrificial layers and the bottom sacrificial layer 220 are both S 2 And S is 1 Less than S 2 At this time, the etching selection ratio of the top sacrificial layer 210 to the lower middle sacrificial layer is less than 1 (i.e. the second etching selection ratio B is less than 1); meanwhile, since the etching selection ratio of the top sacrificial layer 210 to the bottom sacrificial layer 220 is also less than 1 (i.e., the first etching selection ratio a < 1), and the etching rates of the lower middle sacrificial layer and the bottom sacrificial layer 220 are the same, a = B.
The etch rates of the intermediate sacrificial layers 230 may be different from each other, and in a preferred embodiment, the intermediate sacrificial layers 230 are multiple layers, and the second etch selectivity B decreases from top to bottom in the order of the intermediate sacrificial layers 230.
In the above embodiment, the etching rate of the top sacrificial layer 210 is S under the same wet etching condition as that of the m-layer middle sacrificial layer 230 1 The etching rate of the bottom sacrificial layer 220 is S 2 The etching rate of the middle sacrificial layer 230 of each layer is from S to S in the top-down direction 3 Gradually increase to S 4 And S is 1 ＜S 3 ，S 4 ＜S 2 。
It should be noted that, in the above step S1, the positions between the top sacrificial layer 210, the bottom sacrificial layer 220 and the middle sacrificial layer 230 are not limited to the above preferred embodiment, and n upper middle sacrificial layers and m lower middle sacrificial layers (n + m sacrificial layers 20 in total) are further used as the n lower middle sacrificial layersIn other alternative embodiments, the etching rates of the top sacrificial layer 210 and the middle sacrificial layer of the n upper layers are both S under the same wet etching condition 1 The etching rate of the bottom sacrificial layer 220 is S 2 The etching rate of the m lower middle sacrificial layers is from S to S from top to bottom 3 Gradually increase to S 4 And S is 1 ＜S 3 ，S 4 ＜S 2 (ii) a Alternatively, the top sacrificial layer 210 has an etching rate S 1 The etching rate of the n upper middle sacrificial layers is from S in the direction away from the substrate 10 5 Is reduced to S 6 The etching rates of the m lower middle sacrificial layer and the bottom sacrificial layer 220 are both S 2 And S is 1 ＜S 5 ，S 6 ＜S 2 。
In the step S1, the etching rate of the lower sacrificial layer 20 may be reduced while the etching rate of the lower sacrificial layer 20 is kept unchanged by only adjusting the deposition process of the top sacrificial layer 210 and/or the upper middle sacrificial layer, so that the first etching selectivity is less than 1. For example, when the sacrificial layer 20 is formed by SiN deposition, O element may be doped in the deposition process of the upper sacrificial layer 20, or Ge element may be doped in the deposition process of the lower sacrificial layer 20, so as to reduce the etching rate of the upper sacrificial layer 20 in an etching solution such as phosphoric acid.
In the step S1, the etching rate of the lower sacrificial layer 20 may be increased while the etching rate of the upper sacrificial layer 20 is kept unchanged by only adjusting the deposition process of the bottom sacrificial layer 220 and/or the lower intermediate sacrificial layer, so that the first etching selectivity is less than 1. For example, when the sacrificial layer 20 is formed by SiN deposition, ge may be doped in the deposition process of the lower sacrificial layer 20 to increase the etching rate of the lower sacrificial layer 20 in an etching solution such as phosphoric acid. In order to increase the etching rate of the sacrificial layer 20, in addition to doping with Ge, it is also possible to increase the N content.
Besides the manner of doping elements, the etching rate can be adjusted by changing the deposition process of the sacrificial layer 20, for example, compared with LPCVD, HCD (high plasma enhanced CVD) can form SiN with higher density, and compared with HCD, ALD (Atom level depletion) can form SiN with higher density, so that the etching rate of the sacrificial layer 20 can be adjusted by properly selecting the deposition process and the density of the sacrificial layer 20. In addition, since high temperature deposited SiN generally has a lower etch rate than low temperature deposited SiN, the etch rate can also be adjusted by adjusting the deposition temperature in the deposition process.
After the completion of the above step S1, step S2 is performed: a trench via is formed in the stacked structure and a memory structure 40 is formed on the sidewall of the trench via, the memory structure 40 having a charge blocking layer 410 covering the sidewall, as shown in fig. 2.
In step S2, before forming the memory structure 40, an epitaxial layer covering the substrate 10 may be formed at the bottom of the trench via, and the upper surface of the epitaxial layer exceeds the upper surface of the lowermost sacrificial layer 220. The memory structure 40 may be a charge trap type memory structure 40, and in this case, the step of forming the memory structure 40 includes: a charge blocking layer 410, a charge trapping layer 420, a tunneling layer 430 and a channel layer 440 are sequentially formed on the sidewall of the trench via, and the charge blocking layer 410 is covered on the sidewall of the trench via, as shown in fig. 2. The memory structure 40 may further include a filling oxide layer 450 covering the inner surface of the channel layer 440, as shown in fig. 2. The filling oxide layer 450 is typically SiO 2 It may be deposited using an ALC or CVD process in order to cover the channel layer 440.
The material of the functional layers in the memory structure 40 can be chosen reasonably by those skilled in the art, and for example, the material of the charge blocking layer 410 can be SiO 2 The charge trapping layer 420 may be formed of SiN and the tunneling layer 430 may be formed of SiO 2 The material of the channel layer 440 may be polysilicon. Moreover, the above-mentioned memory structure 40 can be formed by a deposition process conventional in the art by those skilled in the art, and will not be described herein.
After the completion of the above step S2, step S3 is executed: a common source trench 40 penetrating through the substrate 10 is formed in the stacked structure, and the sacrificial layer 20 is wet-etched to remove the sacrificial layer 20, as shown in fig. 3 and 4.
In the step S3, the Common Source trench 40 is formed for the purpose of forming an Array Common Source (ACS), a person skilled in the art may use a conventional etching process in the prior art to form the Common Source trench 40, and after forming the Common Source trench 40 communicated with the substrate 10, as shown in fig. 5, the step S3 may further include forming a doped region 60 in a region of the substrate 10 communicated with the Common Source trench 40, where the doped region 60 is opposite to a doping type of the substrate 10; after the step of forming the doped region 60, the step S3 may further include a step of forming a select gate dielectric layer 70 on the doped region 60, as shown in fig. 5.
In the step S3, the common source trench 40 is formed to enable the sacrificial layer 20 to have an exposed end surface, and then the sacrificial layer 20 is wet-etched by using an etching solution from the exposed end surface to remove the sacrificial layer 20. Since the first etching selection ratio is set between the upper sacrificial layer 20 and the lower sacrificial layer 20 formed by the deposition process in step S1, and the first etching selection ratio is smaller than 1, in step S2, the etching solution is used to perform wet etching on the sacrificial layer 20, so that the difference between the etching rates of the lower sacrificial layer 20 and the upper sacrificial layer 20 caused by the etching load effect in the process can be balanced by using the difference between the etching rates, and the problem that the damage of the charge blocking layer 410 is uneven at the upper and lower positions is effectively solved. The etching solution can comprise a phosphoric acid aqueous solution, and can also comprise regulators such as ammonium salt and sulfuric acid and the like, and is used for regulating the etching effect of the etching solution.
After the completion of the above step S3, step S4 is executed: a control gate structure 80 is formed at the position where the sacrificial layer 20 is removed, so that the control gate structure 80 contacts the charge blocking layer 410 and forms a conductive channel 100 in the common source trench 40, as shown in fig. 6 and 7.
After the step S3, by removing the sacrificial layer 20, a channel extending in the lateral direction can be formed at the position where the sacrificial layer 20 is removed, and in the step S4, a gate material is deposited by using the channel as a deposition channel to obtain the gate layer 810, wherein the deposition process can be Atomic Layer Deposition (ALD); the gate material is usually a metal, and may be one or more selected from W, al, cu, ti, ag, au, pt, and Ni.
Also, after the deposition process, the step S4 may further include an etch back (etch back) step to remove the excess gate material in the common-source trench 40, as shown in fig. 6.
The control gate structure 80 includes a gate layer 810, and a high-K dielectric layer 820 may be formed on the surface of the channel before the gate layer 810 is formed, as shown in fig. 8. The K dielectric layer and the gate layer 810 together form a control gate structure 80. The material forming the high-K dielectric layer 820 may be selected from HfO 2 、TiO 2 、HfZrO、HfSiNO、Ta 2 O 5 、ZrO 2 、ZrSiO 2 、Al 2 O 3 、SrTiO 3 And one or more of BaSrTiO.
In the step S4, the replacement of the sacrificial layer 20 and the gate layer 810 is completed by forming the gate layer 810, so as to form an alternate stacked structure of the gate layer 810 and the isolation layer 30, the gate layer 810 at the lowest layer is used as the source terminal select gate, and the epitaxial layer formed in the step S2 is used as the channel layer 440 of the source terminal select gate.
After the step of forming the gate layer 810, in the step S4, as shown in fig. 7, the sidewall insulating layer 90 may be deposited in the common source trench 40, and then the conductive channel 100 may be deposited in the common source trench 40 covered with the sidewall insulating layer 90. The conductive channel 100 is isolated from the gate layer 810 by the sidewall insulating layer 90, the memory structure 40 forms a common source connection via the substrate 10, and the conductive channel 100 provides a conductive path connecting the common source to the source line.
From the above description, it can be seen that the above-described embodiments of the present invention achieve the following technical effects:
the manufacturing method can balance the difference of the etching rates of the lower sacrificial layer and the upper sacrificial layer caused by the etching load effect, reduces the damage to the partial charge barrier layer in contact with the upper sacrificial layer, effectively solves the problem that the charge barrier layer is damaged unevenly at the upper position and the lower position, improves the step coverage capability of the charge barrier layer at the upper position and the lower position, and reduces the electric leakage risk of the back gate of the word line at the upper layer;
because the upper charge blocking layer has small loss, charges in the trapping layer are more difficult to tunnel into the grid layer, so that the data retention characteristic of the upper storage unit is improved, the sub-wire interlayer coupling effect is reduced, the distance between programmed states is improved, and programming or erasing failure caused by the tunneling of the charges between the blocking layer and the grid is reduced.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (16)

1. A semiconductor structure, comprising:
a first stacked structure including first dielectric layers and second dielectric layers alternately stacked, the first dielectric layers including an upper first dielectric layer and a lower first dielectric layer; wherein the upper first dielectric layer has a first etch selectivity A to the lower first dielectric layer, wherein A < 1;
a first channel structure extending through the first stacked structure in a direction in which the upper first dielectric layer points toward the lower first dielectric layer, the first channel structure including a memory structure in which a charge blocking layer is in contact with the first dielectric layer and the second dielectric layer.
2. The semiconductor structure of claim 1, wherein the storage structure comprises the charge blocking layer, charge trapping layer, tunneling layer, and channel layer in a direction radially inward of the first channel structure.
3. The semiconductor structure of claim 1, further comprising:
and a second stacked structure including conductive layers and second dielectric layers alternately stacked.
4. The semiconductor structure of claim 3, wherein the first stacked structure and the second stacked structure are disposed adjacent, wherein the first dielectric layer and the conductive layer are in contact.
5. The semiconductor structure of claim 3, further comprising:
a second channel structure extending through the second stack structure in a direction from the upper first dielectric layer toward the lower first dielectric layer, the second channel structure including a storage structure in which a charge blocking layer is in contact with the conductive layer and the second dielectric layer.
6. The semiconductor structure of claim 5, wherein the storage structure comprises the charge blocking layer, charge trapping layer, tunneling layer, and channel layer in a direction radially inward of the second channel structure.
7. The semiconductor structure of claim 1, wherein the material of the upper first dielectric layer is doped with an elemental O; and/or the material of the lower first dielectric layer is doped with Ge element.
8. The semiconductor structure of claim 1, wherein in the case where the material of the first dielectric layer is SiN, the Si content of the upper first dielectric layer is higher than the Si content of the lower first dielectric layer.
9. The semiconductor structure of claim 1, wherein the upper first dielectric layer has a density that is greater than a density of the lower first dielectric layer.
10. The semiconductor structure of claim 1, wherein a deposition temperature for forming the upper first dielectric layer is higher than a deposition temperature for forming the lower first dielectric layer.
11. The semiconductor structure of claim 1, wherein the first dielectric layer further comprises an intermediate first dielectric layer between the upper first dielectric layer and the lower first dielectric layer; the upper first dielectric layer has a second etching selection ratio B to the middle first dielectric layer, wherein A is more than B and less than or equal to 1.
12. The semiconductor structure of claim 11, wherein the intermediate first dielectric layers are multilayered, and the second etch selectivity B of the upper first dielectric layer to each of the intermediate first dielectric layers decreases sequentially in a direction in which the upper first dielectric layer points toward the lower first dielectric layer.
13. The semiconductor structure of claim 11, wherein the intermediate first dielectric layers are multilayered and the multilayered intermediate first dielectric layers comprise at least one upper intermediate first dielectric layer and at least one lower intermediate first dielectric layer, an etch selectivity of the upper first dielectric layer to each of the upper intermediate first dielectric layers is equal to 1, and an etch selectivity of the upper first dielectric layer to each of the lower intermediate first dielectric layers is less than 1.
14. The semiconductor structure of claim 11, wherein the intermediate first dielectric layers are multilayered and the multilayered intermediate first dielectric layers comprise at least one upper intermediate first dielectric layer and at least one lower intermediate first dielectric layer, an etch selectivity of each upper intermediate first dielectric layer to the lower first dielectric layer is less than 1, and an etch selectivity of each lower intermediate first dielectric layer to the lower first dielectric layer is equal to 1.
15. The semiconductor structure of claim 1, further comprising:
a semiconductor layer located below the first stacked structure; wherein a distance in the stacking direction between the lower first dielectric layer and the semiconductor layer is smaller than a distance in the stacking direction between the upper first dielectric layer and the semiconductor layer.
16. The semiconductor structure of claim 15, further comprising:
a common source structure extending through the first stack structure and to the semiconductor layer;
and the doped region is arranged in the semiconductor layer and is connected with the common source structure.
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