CN111430452A - Unit structure of multi-time programmable memory and manufacturing method thereof - Google Patents

Unit structure of multi-time programmable memory and manufacturing method thereof Download PDF

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CN111430452A
CN111430452A CN202010182566.6A CN202010182566A CN111430452A CN 111430452 A CN111430452 A CN 111430452A CN 202010182566 A CN202010182566 A CN 202010182566A CN 111430452 A CN111430452 A CN 111430452A
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gate
floating gate
layer
substrate
forming
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秋珉完
金起準
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Nexchip Semiconductor Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity

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Abstract

The invention provides a unit structure of a multi-time programmable memory and a manufacturing method thereof, wherein the unit structure comprises a substrate, a floating gate, a first side wall, an SAB film and a control gate, wherein the floating gate is positioned on the substrate, the first side wall is positioned on the side wall of the floating gate, and the SAB film and the control gate are sequentially positioned on the floating gate, and the control gate and the SAB film extend along the direction vertical to the thickness direction of the floating gate to cover part. The control grid in the unit structure of the multi-time programmable memory provided by the invention controls the floating grid to store and erase data through coupling, and an additional Tunneling area (Tunneling area) is not needed, so that the size of the unit structure of the multi-time programmable memory is reduced, and the requirement of a MTP (multiple time programmable) device on small size is met. Furthermore, the SAB film and the control gate extend along a direction perpendicular to the thickness direction of the floating gate to cover a part of the first side wall, so that damage to the first side wall when the SAB film is etched is weakened or avoided, and the performance of the multi-time programmable memory is improved.

Description

Unit structure of multi-time programmable memory and manufacturing method thereof
Technical Field
The invention relates to the field of integrated circuit manufacturing, in particular to a unit structure of a multi-time programmable (MTP) memory and a manufacturing method thereof.
Background
Memory is an important component of digital integrated circuits, and is an indispensable part for constructing microprocessor-based application systems. In recent years, various memories have been embedded inside processors to improve the integration and work efficiency of the processors.
Multi-Time Program Memory (MTP) has the advantages that, compared with One-Time programmable Memory (OTP), it can store, read, erase data many times, and the stored data will not disappear after power-off, and has gradually become a Memory device widely used in the fields of personal computers, electronic devices, mobile storage, etc.
However, the cell structure of the multi-time programmable memory formed by the conventional method has a large size and the performance is not ideal.
Disclosure of Invention
The invention aims to provide a unit structure of a multi-time programmable memory and a manufacturing method thereof, which can reduce the size of the unit structure of the multi-time programmable memory and improve the performance of the multi-time programmable memory.
To achieve the above object, the present invention provides a cell structure of a multi-time programmable memory, including:
a substrate, a first electrode and a second electrode,
the floating gate is positioned on the substrate, and the first side wall is positioned on the side wall of the floating gate; and the number of the first and second groups,
and the SAB film and the control gate are sequentially positioned on the floating gate, and the SAB film and the control gate extend along the direction vertical to the thickness direction of the floating gate to cover part of the first side wall.
Optionally, the device further comprises a select gate located on the substrate, and a second sidewall is formed on a sidewall of the select gate.
Optionally, an active region is formed in the substrate, and an active doped region and a drain doped region are formed in the active region.
Optionally, the floating gate and the select gate are located between the source doped region and the drain doped region.
Optionally, the device further comprises a salicide layer, wherein the salicide layer covers the select gate, the control gate, the source doped region and the drain doped region.
Optionally, the device further includes an interlayer dielectric layer located on the salicide layer and covering the substrate, a conductive plug located in the interlayer dielectric layer and connected to the salicide layer, and an electrode structure located on the interlayer dielectric layer and connected to the conductive plug.
Optionally, a gate oxide layer is formed between the floating gate and the substrate.
Optionally, the SAB film includes an oxide layer and a nitride layer sequentially stacked on the surface of the floating gate.
Optionally, the first side wall and the second side wall both have an ONO structure.
Correspondingly, the invention also provides a manufacturing method of the unit structure of the multi-time programmable memory, which comprises the following steps:
providing a substrate;
forming a floating gate on the substrate, and forming a first side wall on the side wall of the floating gate; and the number of the first and second groups,
and sequentially forming an SAB film and a control gate on the floating gate, wherein the SAB film and the control gate extend along a direction vertical to the thickness direction of the floating gate to cover part of the first side wall.
Optionally, the method further includes: forming a floating gate on the substrate and simultaneously forming a selection gate on the substrate; and forming a second side wall on the side wall of the selection gate while forming a first side wall on the side wall of the floating gate.
Optionally, before forming the floating gate on the substrate, the method further includes: and forming a gate oxide layer on the substrate.
Optionally, after forming the first sidewall on the sidewall of the floating gate, before sequentially forming the SAB thin film layer and the control gate layer on the substrate, the method further includes: and carrying out ion implantation on the substrate to form a source doping region and a drain doping region.
Optionally, the SAB film includes an oxide layer and a nitride layer sequentially stacked on the surface of the floating gate, and the first side wall and the second side wall both have an ONO structure.
Optionally, sequentially forming the SAB film and the control gate on the floating gate includes:
forming an SAB film material layer and a control gate material layer on the substrate;
forming a patterned photoresist layer on the control gate material layer by using an SAB mask;
and etching the control gate material layer and the SAB film material layer in sequence to form the SAB film and the control gate on the floating gate in sequence.
Optionally, after forming the SAB film and the control gate on the floating gate, the method further includes:
forming a self-aligned silicide layer on the substrate, wherein the self-aligned silicide layer covers the selection gate, the control gate, the source doped region and the drain doped region;
forming an interlayer dielectric layer on the substrate;
forming a contact hole exposing the selection gate, the control gate, the source doped region and the drain doped region in the interlayer dielectric layer;
filling a conductive material into the inner wall of the contact hole to form a conductive plug;
and forming a metal layer on the interlayer dielectric layer, and patterning the metal layer to form an electrode structure.
In summary, the present invention provides a cell structure of a multi-time programmable memory and a method for fabricating the same, including a substrate, a floating gate on the substrate, a first sidewall on a sidewall of the floating gate, and an SAB film and a control gate sequentially on the floating gate, wherein the control gate and the SAB film extend in a direction perpendicular to a thickness direction of the floating gate to cover a portion of the first sidewall. The control grid in the unit structure of the multi-time programmable memory provided by the invention controls the floating grid to store and erase data through coupling, and an additional Tunneling area (Tunneling area) is not needed, so that the size of the unit structure of the multi-time programmable memory is reduced, and the requirement of a MTP (multiple time programmable) device on small size is met. Furthermore, the SAB film and the control gate extend along a direction perpendicular to the thickness direction of the floating gate to cover a part of the first side wall, so that damage to the first side wall when the SAB film is etched is weakened or avoided, and the performance of the multi-time programmable memory is improved.
Drawings
FIG. 1A is a schematic diagram illustrating a top view of a cell structure of an OTP memory, and FIG. 1B is a schematic diagram illustrating a cross-sectional view of the OTP memory along line aa' of FIG. 1A;
FIG. 2 is a flow chart of a method for fabricating a cell structure of a multi-time programmable memory according to an embodiment of the invention;
fig. 3 to fig. 7B are schematic structural diagrams corresponding to corresponding steps of a method for manufacturing a cell structure of a multi-time programmable memory according to an embodiment of the invention;
FIG. 7C is a schematic diagram illustrating a top view of a cell structure of a multi-time programmable memory according to another embodiment of the present invention;
fig. 8A to 8B are schematic diagrams illustrating a cell structure of a multi-time programmable memory according to an embodiment of the present invention to implement data writing and erasing.
Wherein the reference numerals are:
10. 20-cell structure of multi-time programmable memory;
103. 104, 105, 203, 204, 205-N + doped regions;
100. 200-a substrate;
110. 210-a floating gate;
120. 220-a select gate;
130-tunneling region;
211-first side wall;
221-a second sidewall;
230' -SAB film material layer;
230-SAB film;
231', 231-oxide layer;
232', 232-nitride layer;
240' -a control gate material layer;
240-control gate;
250-a patterned photoresist;
101. 201-P well;
202-a gate oxide layer;
206-self-aligned metal silicide layer;
207-interlayer dielectric layer;
108. 208-a conductive plug;
113. 213-a source electrode;
114. 214-select signal electrodes;
115. 215-drain electrode;
116. 216-programming signal electrode.
Detailed Description
FIG. 1A is a top view of a cell structure of an OTP memory, and FIG. 1B is a cross-sectional view of the OTP memory along line aa' in FIG. 1A. As shown in fig. 1A and 1B, a cell structure 10 of an otp memory includes a P-Well region (P-Well)101 formed in a substrate 100, a floating gate 110(FG) and a select gate 120(SG) formed on the P-Well 101, N + doped regions 103, 104, 105 on both sides of the floating gate 110 and the select gate 120, and a program signal electrode 116, a select signal electrode 114, a source electrode 113, and a drain electrode 115 electrically connected to the floating gate 110, the select gate 120, the N + doped region 103, and the N + doped region 105, respectively, through a conductive plug 108. For a single-layer polysilicon gate (floating gate) structure, Programming (PGM) and Erasing (ERS) operations of MTP cells are realized by injecting electrons or holes into the floating gate 110 or erasing the electrons or holes, an additional Tunneling area (Tunneling area)130 is required to realize the above functions, which results in an increase in the size of the cell structure 10(1Bit-cell) of the multi-time programmable memory (about 10-90 um)2) This is not favorable for realizing the miniaturization of the MTP device.
The core idea of the invention is to provide a unit structure of a multi-time programmable memory and a manufacturing method thereof, wherein the unit structure comprises a substrate, a floating gate positioned on the substrate, a first side wall positioned on the side wall of the floating gate, and an SAB film and a control gate which are sequentially positioned on the floating gate, and extend along the direction vertical to the thickness direction of the floating gate to cover part of the first side wall. In the cell structure of the multi-time programmable memory provided by the invention, the control grid controls the floating gate to store and erase data through coupling, and an additional Tunneling area (Tunneling area) is not needed, so that the size of the cell structure of the multi-time programmable memory is reduced, and the requirement of a MTP (multiple time programmable) device on small size is met. Furthermore, the SAB film and the control gate extend along a direction perpendicular to the thickness direction of the floating gate to cover a part of the first side wall, so that damage to the first side wall when the SAB film is etched is reduced or avoided, and the performance of the multi-time programmable memory is improved.
The cell structure of the multi-time programmable memory and the manufacturing method thereof according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and drawings, it being understood, however, that the concepts of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. The drawings are in simplified form and are not to scale, but are provided for convenience and clarity in describing embodiments of the invention. Furthermore, it should be readily understood that the meaning of "on …" and "on …" herein should be interpreted in the broadest sense such that the meaning of "on …" and "on …" is not only "directly on something" without an intervening feature or layer, but also includes the meaning of "on something" with an intervening feature or layer. For the sake of clarity, the cell structure of the multi-time programmable memory provided by the present invention is provided, the interlayer dielectric layer is omitted in the top view schematic diagrams of the cell structure of the multi-time programmable memory shown in fig. 7A and 7C in the specification, and the floating gate to be covered by the control gate is shown by a dotted line.
The terms "first," "second," and the like in the description are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other sequences than described or illustrated herein. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method. Although elements in one drawing may be readily identified as such in other drawings, the present disclosure does not identify each element as being identical to each other in every drawing for clarity of description.
Fig. 7A is a schematic top view illustrating a cell structure of a multi-time programmable memory according to the present embodiment; fig. 7B is a cross-sectional view of the cell structure of the multi-time programmable memory along line bb' in fig. 7A. As shown in fig. 7A and 7B, the present embodiment provides a cell structure 20 of a multi-time programmable memory, which includes: the structure comprises a substrate 200, a floating gate 210 and a selection gate 220 which are positioned on the substrate 200, a first side wall 211 positioned on the side wall of the floating gate 210, a second side wall 221 positioned on the side wall of the selection gate 220, and an SAB film 230 and a control gate 240 which are positioned on the floating gate 210, wherein the SAB film 230 and the control gate 240 extend along the direction vertical to the thickness direction of the floating gate 210 to cover a part of the first side wall 211.
The substrate 200 may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC), or Silicon On Insulator (SOI), Germanium On Insulator (GOI); or may be other materials such as group III-V compounds such as gallium arsenide. In the present embodiment, the substrate 200 is a silicon substrate, which is only an example and the present invention is not limited thereto. Preferably, the substrate 200 has a deep well therein, for example, the doping type of the deep well is P-type (P-well 201), and in addition, a shallow trench isolation structure (not shown) is formed in the substrate 200, and an Active Area (AA) is defined by the shallow trench isolation structure. The floating gate 210 and the select gate 220 are located on the active area AA, and N + doped regions 203, 204, 205 are formed in the active area AA on both sides of the floating gate 210 and the select gate 220. The floating gate 210 and the select gate 220 share the N + doped region 204, which is defined as a source doped region 203 and a drain doped region 205, for convenience of description.
It should be noted that the substrate 200 includes a memory cell region and a peripheral circuit region, the floating gate 210 and the select gate 220 are located in the memory cell region and are used for forming a memory transistor and a high voltage transistor for controlling the memory transistor, and a structure such as a capacitor is formed on the peripheral circuit region. Since the present invention mainly introduces the structural features of the multiple time programmable memory cell region, in order to make the drawings clearly express the core idea of the present invention, the device and structure of a part of the multiple time programmable memory cell region are only shown in the drawings in the form of schematic diagrams, but this does not represent that the multiple time programmable memory cell structure of the present invention only includes these parts, and the well-known multiple time programmable memory cell structure can also be included therein. The structure and the forming method in the peripheral circuit region are the same as those in the prior art, and are not described herein again.
The interface of the floating gate 210 and the select gate 220 in contact with the substrate 200 is typically formed with a gate oxide layer 202, the gate oxide layer 202 being, for example, silicon dioxide (SiO)2). The first side wall (Spacer)211 and the second side wall 221 are made of silicon dioxide or silicon nitride, and the thickness of the first side wall (Spacer) is 3nm to 100 nm. For example, the first sidewall 211 and the second sidewall 221 both have an Oxide-Nitride-Oxide (ONO) structure, that is, an isolation Oxide layer, a sidewall Nitride layer, and a sidewall Oxide layer are sequentially stacked on the side surfaces of the floating gate 210 and the select gate 220, where the isolation Oxide layer is, for example, silicon dioxide (SiO)2) The side wall nitride layer is, for example, silicon nitride (Si)xN), the sidewall oxide layer being, for example, silicon oxynitride (SiO)xNy) Or silicon dioxide (SiO)2)。
A Salicide Area Block (SAB) film 230 is located between the floating gate 210 and the control gate 240, and serves as an inter-gate dielectric layer between the floating gate 210 and the control gate 240, the SAB film 230 may be a single layer structure composed of a single oxide or nitride or a multi-layer structure composed of an oxide or nitride, for example, the SAB film 230 includes a three-layer structure of an oxide layer-a nitride layer-an oxide layer sequentially stacked on the surface of the floating gate 210, or the SAB film 230 includes a two-layer structure of an oxide layer-a nitride layer sequentially stacked on the surface of the floating gate 210. Of oxide layers in the SAB film 230The material is silicon dioxide (SiO)2) The material of the nitride layer is silicon nitride (Si)xN). The SAB film 230 may be made of the same or similar materials and processes as the ONO triple layer structure in the first sidewall 211 and the second sidewall 221 (but excluding the portion etched to form the sidewall). In this embodiment, the SAB film 230 has a two-layer structure, and includes an oxide layer 231 and a nitride layer 232 sequentially stacked on the surface of the floating gate 210.
As shown in fig. 7B, the SAB film 230 and the control gate 240 cover a portion of the first sidewall 211 near one side of the floating gate 210, i.e. when the SAB film 230 and the control gate 240 are formed by etching, etching stops at the side (L etching on Spacer) of the first sidewall 211 near the floating gate 210. due to the similar structural composition of the SAB film 230 and the first sidewall 211, the structure of the first sidewall 211 is damaged during the etching process to form the SAB film 230 and the control gate 240, when the isolation oxide layer on the inner side of the first sidewall 211 is side-etched, the floating gate 210 may be in contact with the source/drain doped region to cause short circuit, therefore, when the SAB film 230 and the control gate 240 are formed by etching, the isolation oxide layer covers the surface of the floating gate 210 and extends in a direction perpendicular to the thickness direction of the floating gate to cover a portion of the first sidewall 211, so as to reduce or avoid damage to the first sidewall 211 when the SAB film 230 is etched, thereby avoiding the loss of the isolation oxide layer on the first sidewall 211 due to side etching, and improving the performance of the programmable memory.
As shown in fig. 7A and 7B, the cell structure 20 of the otp memory further includes a salicide layer 206, and the salicide layer 206 covers the select gate 220, the control gate 240, and the N + doped regions 203, 204, and 205. The salicide layer 206 is a metal Silicide having low resistance and good adhesion to a silicon material, such as cobalt Silicide (cobalt Silicide), Titanium Silicide (Titanium Silicide), or Nickel Silicide (Nickel Silicide). The salicide layer 206 may serve as a Contact structure (Contact) for the transistor to lead out the source, drain, and gate of the transistor.
The cell structure 20 of the multi-time programmable memory provided in this embodiment further includes an interlayer dielectric layer 207 located on the salicide layer 206 and covering the substrate 200, a conductive plug 208 located in the interlayer dielectric layer 207 and connected to the salicide layer 206, and an electrode structure located on the interlayer dielectric layer 207 and connected to the conductive plug 208, wherein the electrode structure includes a source electrode 213 (S/L), a drain electrode 215 (B/L), a selection signal electrode 214, and a programming signal electrode 216, and the source electrode 213 (S/L), the drain electrode 215 (B/L), the selection signal electrode 214, and the programming signal electrode 216 are respectively connected to the N + doped region 203, the N + doped region 205, the selection gate 220, and the salicide layer 206 on the control gate 240 through the conductive plug 208.
In the present embodiment, the memory cell region of the multi-time programmable memory includes a plurality of the cell structures 20 (shown by dashed line boxes), and the floating gate 210 and the controlled gate 240 in the cell structures 20 may be formed on an active region AA independently. As shown in fig. 7A. In other embodiments of the present invention, the control gate 240 of the adjacent cell structure 20 in the memory cell region of the otp memory can be shared, i.e., the floating gate 210 segment (Segmented) is located under the control gate 240, as shown in fig. 7C.
In the cell structure of the multi-time programmable memory provided by this embodiment, the floating gate 210 is used as an electron storage layer, through programming, when the voltage difference between the control gate 240 and the substrate 200 is large enough, electrons collected in a channel can enter the floating gate 210 through a tunneling effect, and a gate dielectric layer (SAB film 230) between the control gate 240 and the floating gate 210 prevents the electrons from being lost through the control gate 240, so that the electrons are stored in the floating gate 210. Specifically, referring to fig. 8A, when performing a data write (PGM) operation, a high positive bias is applied to the control gate 240, so that electrons are injected from the N + doped region 203 into the floating gate 210 through the gate dielectric layer 202; referring to fig. 8B, when performing an erase operation (ERS), a high negative bias is applied to the control gate 240, and the control gate 240 controls the release of electrons in the floating gate 210 through coupling, so that the electrons stored in the floating gate 210 are removed from the floating gate 210 by Fowler-Nordheim (FN) tunneling, i.e., the erase of the data stored in the cell structure of the MTP device is completed.
The cell structure 20 (shown by a dashed box) of the otp memory provided in this embodiment includes a select gate 220 and a floating gate 210 on the substrate 200, and the SAB film 230 and the control gate 240 on the floating gate 210, wherein the control gate 240 controls the floating gate 210 to store and erase data by coupling, and an additional Tunneling area (Tunneling area) is not required, so that the size of the cell structure 20(1Bit-cell) of the otp memory is reduced (about 1-10 um)2) And the requirement of the MTP device for small size is met. Further, the control gate 240 and the SAB film 230 extend in a direction perpendicular to the thickness direction of the floating gate to cover a portion of the first sidewall 211, so as to reduce or avoid damage to the first sidewall 211 when the SAB film is etched, thereby improving the performance of the multi-time programmable memory.
Accordingly, the present invention further provides a method for manufacturing a cell structure of a multi-time programmable memory, where fig. 2 is a flowchart of a method for manufacturing a cell structure of a multi-time programmable memory provided in this embodiment, and as shown in fig. 2, the method for manufacturing a cell structure of a multi-time programmable memory provided in this embodiment includes the following steps:
s01: providing a substrate;
s02: forming a floating gate on the substrate, and forming a first side wall on the side wall of the floating gate; and the number of the first and second groups,
s03: and sequentially forming an SAB film and a control gate on the floating gate, wherein the SAB film and the control gate extend along a direction vertical to the thickness direction of the floating gate to cover part of the first side wall.
Fig. 3 to fig. 7B are schematic structural diagrams corresponding to corresponding steps of the method for manufacturing the cell structure of the multi-time programmable memory according to the embodiment. The method for manufacturing the cell structure of the multi-time programmable memory provided in this embodiment will be described in detail below with reference to fig. 2 and fig. 3 to 7B.
First, as shown in fig. 3, step S01 is performed to provide the substrate 200. The substrate 200 may be made of monocrystalline silicon (Si), monocrystalline germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC), or Silicon On Insulator (SOI), Germanium On Insulator (GOI); or may be other materials such as group III-V compounds such as gallium arsenide. In the embodiment, the substrate 200 is only an example of a silicon substrate, and this is merely an example, and the invention is not limited thereto. In performing step S01, it is contemplated that process steps including, but not limited to, the following may also be completed on substrate 200: isolation trenches (e.g., Shallow Trench Isolation (STI)) are formed on the substrate 200, and well implantation (e.g., P-well 201), other ion implantation, and annealing are performed on the substrate 200.
Next, with continuing reference to fig. 3, step S02 is performed to form a floating gate 210 on the substrate 200, and form a first sidewall 211 on the sidewall of the floating gate 210. Before forming the floating gate 210, a gate oxide layer 202 is formed on the substrate 200, the gate oxide layer 202 may be formed on the global surface of the substrate 200 by using a thermal oxidation (wet oxidation or dry oxidation) process, an in-situ steam generation process (ISSG), a Chemical Vapor Deposition (CVD) process, or an atomic layer deposition process, and the gate oxide layer 202 may be made of silicon dioxide (SiO) material2) Silicon oxynitride (SiO)xNy) Or silicon nitride (Si)xN), etc., and the thickness may be 2nm to 30 nm.
It should be noted that the materials, thicknesses and formation manners of the above-mentioned and later-mentioned layers are only examples of the embodiments of the present invention, and different materials, thicknesses and formation manners may be adopted in different cases, which should not be construed as limiting the present invention.
After a gate oxide layer 202 is formed on the substrate 200, a floating gate 210 and a select gate 220 are formed on the gate oxide layer 202. Specifically, first, a gate material layer is formed on the substrate 200, where the gate material layer may be made of polysilicon, a metal material compound, or other suitable materials, then a patterned photoresist layer is formed on the gate material layer, and then the gate material layer is etched using the patterned photoresist layer as a mask to form the floating gate 210 and the select gate 220. In this embodiment, the floating gate 210 and the select gate 220 are made of polysilicon, and for example, the floating gate 210 and the select gate 220 may be formed by dry etching. In other embodiments of the present invention, the floating gate 210 and the select gate 220 may also be made of different materials, or the floating gate 210 and the select gate 220 may also be formed by different methods, which is not limited herein.
After forming the floating gate 210 and the select gate 220 on the gate oxide layer 202, a first sidewall 211 and a second sidewall 221 are formed on the sidewalls of the floating gate 210 and the select gate 220, respectively. The first side wall 211 and the second side wall 221 are made of one or a combination of silicon oxide and silicon nitride, and the thickness is 3nm to 100 nm. For example, each of the first sidewall 211 and the second sidewall 221 has an Oxide-Nitride-Oxide (ONO) structure, that is, an isolation Oxide layer, a sidewall Nitride layer, and a sidewall Oxide layer (not shown in the figure) are sequentially formed by overlapping side surfaces of the floating gate 210 and the select gate 220, the isolation Oxide layer is close to the floating gate 210 and the select gate 220 and is an inner layer of the first sidewall 211 and the second sidewall 221, and the isolation Oxide layer is, for example, silicon dioxide (SiO) for example2) The side wall nitride layer is, for example, silicon nitride (Si)xN), the sidewall oxide layer being, for example, silicon oxynitride (SiO)xNy) Or silicon dioxide (SiO)2) Illustratively, the isolation oxide layer may be deposited using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, the sidewall nitride layer may be deposited using a low pressure chemical vapor deposition (L PCVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, or the like, and the sidewall oxide layer may be deposited using an Atmospheric Pressure Chemical Vapor Deposition (APCVD) process, a low pressure chemical vapor deposition (L PCVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, or the like, the forming of the first sidewall 211 and the second sidewall 221 may further include anisotropically etching the isolation oxide layer, the sidewall nitride layer, and the sidewall oxide layer.
After the first sidewall 211 and the second sidewall 221 are formed, ion implantation is performed on the substrate 200, and N + doped regions 203, 204, 205 are formed on two sides of the floating gate 210 and the select gate 220. For example, an existing source-drain implantation process may be used to implant, for example, at least one of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions, and a high temperature anneal may be performed after the implantation. The floating gate 210 and the select gate 220 share the N + doped region 204, which is defined as a source doped region 203 and a drain doped region 205, for convenience of description.
Next, as shown in fig. 4 to 6, step S03 is performed to sequentially form an SAB film 230 and a control gate 240 on the floating gate 210, wherein the SAB film 230 and the control gate 240 cover a portion of the first sidewall 211 close to one side of the floating gate 230. Specifically, first, as shown in fig. 4, an SAB thin film material layer 230 'and a control gate material layer 240' are sequentially formed on the substrate 200. In this embodiment, the SAB thin film material layer 230 'has a double-layer structure composed of an oxide layer 231' and a nitride layer 232 ', for example, the material of the oxide layer 231' is silicon dioxide (SiO)2) The material of the nitride layer 232' is silicon nitride (Si)xN), the oxide layer 231 ' may be formed by using a low pressure chemical vapor deposition method (L PCVD), and then the nitride layer 232 ' is formed on the oxide layer 231 ' by using a low pressure chemical vapor deposition method, in other embodiments of the present invention, the SAB thin material layer 230 ' may also be a three-layer structure composed of an oxide layer, a nitride layer and an oxide layer, and then, a control gate material layer 240 ' is formed on the SAB thin material layer 230 ', and the control gate material layer 240 ' may be made of polysilicon, a metal material compound or other suitable materials.
Then, as shown in fig. 5, an SAB mask (SAB Photo) is used to form a patterned photoresist layer 250 on the surface of the control gate material layer 240 ', wherein the patterned photoresist layer 250 covers the control gate material layer 240' on the floating gate 210 and extends to the first sidewalls 210 on both sides of the floating gate 210, so as to prevent the ONO structure of the first sidewalls 211 from being damaged when the SAB thin film material layer is subsequently etched, and particularly prevent the isolation oxide layer on the inner side of the first sidewalls 211 from being damaged by side etching. Next, using the patterned photoresist layer 250 as a mask, the control gate material layer 240 'and the SAB film material layer 230' are sequentially etched, the SAB film 230 and the control gate 240 are formed on the floating gate 210, and the SAB film 230 and the control gate 240 extend in a direction perpendicular to the thickness direction of the floating gate 210 to cover a portion of the first sidewall 211, as shown in fig. 6. For example, the control gate material layer 240 'may be removed by dry etching, the control gate 240 is formed, and the nitride layer 232' and the oxide layer 231 'in the SAB thin film material layer 230' are sequentially removed by wet etching. For example, the nitride layer 232 'may be removed by a wet process using a phosphoric acid solution, the oxide layer 231' may be removed by a wet process using a hydrofluoric acid solution, and the wet etching is stopped on the first sidewall 211, so that the SAB film 230 and the control gate 240 formed after the etching cover a portion of the first sidewall 211, and protect the isolation oxide layer in the first sidewall 211 near the floating gate 210. In this embodiment, the thickness of the nitride layer 232 in the SAB thin film layer 230 is 5nm to 10nm, and the thickness of the oxide layer 231 is 5nm to 10 nm. As shown in fig. 6, the thickness d of the SAB film 230 and the control gate 240 covering the first side wall 210 is 20nm to 30nm, and the thickness d of the SAB film 230 and the control gate 240 covering portions is different according to the structure of the first side wall 211.
The method for manufacturing the cell structure of the multi-time programmable memory provided by the embodiment further comprises the following steps: a salicide layer 206 is formed, and the salicide layer 206 is a Metal Silicide (Metal Silicide), such as Cobalt Silicide (Cobalt Silicide), Titanium Silicide (Titanium Silicide), and Nickel Silicide (Nickel Silicide). Specifically, referring to fig. 7B, a salicide process may be used to form a salicide 206 on the select gate 220, the control gate 240, and the N + doped regions 203, 204, 205, which includes the following steps: first, a metal layer (e.g., at least one metal selected from Ni, Co, W, Pt, Mn, Ti, Ta, etc.) is formed on the linerOn the bottom 200, the metal layer covers the surfaces of the select gate 220, the control gate 240 and the N + doped regions 203, 204, 205; then, a thermal annealing process is performed to react the metal particles (M) in the metal layer with silicon (Si) on the surfaces of the select gate 220, the control gate 240 and the N + doped regions 203, 204, 205 to form self-aligned Metal Silicide (MSi)x) Layer 206. The salicide layer 206 can reduce the Contact resistance between the select gate 220, the control gate 240, and the N + doped regions 203, 204, 205 and the subsequently formed conductive plug (Contact), thereby improving the device performance. It should be noted that, before forming the salicide layer 206, patterning the gate oxide layer 202 to expose the N + doped regions 203, 204, 205 is further included.
Then, with continued reference to fig. 7A and 7B, the method for manufacturing the cell structure of the multi-time programmable memory further includes forming an interlayer dielectric layer 207 on the substrate 200, where the interlayer dielectric layer 207 is, for example, a silicon dioxide layer, forming a contact hole in the interlayer dielectric layer 207, for example, etching the interlayer dielectric layer 207 by dry etching to form a contact hole exposing the N + doped region 203, the N + doped region 205, the select gate 220, and the control gate 240, filling a conductive material, such as metal tungsten, into an inner wall of the contact hole to form a conductive plug 208, forming a metal layer on the interlayer dielectric layer 207, and patterning the metal layer to form an electrode structure, where the electrode structure includes a source electrode 213 (S/L), a drain electrode 215 (B/L), a select signal electrode 214, and a program signal electrode 216, where the source electrode 213 (S/L), the drain electrode 215 (B/L), the select signal electrode 214, and the program signal electrode 216 are respectively connected to the N + doped region 203, the N + doped region 205, the select gate 220, and the self-aligned metal layer 206 on the control gate 240 through the conductive plug.
In the method for manufacturing the cell structure of the multi-time programmable memory, provided by the invention, the SAB film is used as an inter-gate dielectric layer between the control gate and the floating gate, when the control gate 240 and the SAB film 230 are formed by etching, a pattern for defining the control gate 240 can be embedded into an SAB mask for defining the SAB film, and the control gate 240 and the SAB film 230 can be simultaneously defined by using one SAB mask. Moreover, the SAB film and the control gate extend along the direction perpendicular to the thickness direction of the floating gate to cover a part of the first side wall, so that damage to the first side wall when the SAB film is etched is weakened or avoided, and the performance of the multi-time programmable memory is improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (16)

1. A cell structure for a multiple-time programmable memory, comprising:
a substrate, a first electrode and a second electrode,
the floating gate is positioned on the substrate, and the first side wall is positioned on the side wall of the floating gate; and the number of the first and second groups,
and the SAB film and the control gate are sequentially positioned on the floating gate, and the SAB film and the control gate extend along the direction vertical to the thickness direction of the floating gate to cover part of the first side wall.
2. The cell structure of the otp memory of claim 1, further comprising a select gate on the substrate, wherein a second spacer is formed on a sidewall of the select gate.
3. The cell structure of the multi-time programmable memory of claim 2, wherein an active region is formed in the substrate, and an active doped region and a drain doped region are formed in the active region.
4. The cell structure of the otp memory of claim 3, wherein the floating gate and the select gate are located between the source dopant region and the drain dopant region.
5. The cell structure of the otp memory of claim 3, further comprising a salicide layer covering the select gate, the control gate, and the source and drain dopant regions.
6. The cell structure of the OTP memory of claim 5, further comprising an interlevel dielectric layer overlying the salicide layer and covering the substrate,
a conductive plug located in the interlayer dielectric layer and connected with the self-aligned silicide layer,
and the electrode structure is positioned on the interlayer dielectric layer and is connected with the conductive plug.
7. The cell structure of the multi-time programmable memory according to claim 1, wherein a gate oxide layer is formed between the floating gate and the substrate.
8. The cell structure of the otp memory of claim 1, wherein the SAB film comprises an oxide layer and a nitride layer sequentially stacked on the surface of the floating gate.
9. The cell structure of the multi-time programmable memory according to claim 2, wherein the first sidewall spacer and the second sidewall spacer each have an ONO structure.
10. A method for manufacturing a unit structure of a multi-time programmable memory is characterized by comprising the following steps:
providing a substrate;
forming a floating gate on the substrate, and forming a first side wall on the side wall of the floating gate; and the number of the first and second groups,
and sequentially forming an SAB film and a control gate on the floating gate, wherein the SAB film and the control gate extend along a direction vertical to the thickness direction of the floating gate to cover part of the first side wall.
11. The method of claim 10, further comprising: forming a floating gate on the substrate and simultaneously forming a selection gate on the substrate; and forming a second side wall on the side wall of the selection gate while forming a first side wall on the side wall of the floating gate.
12. The method of claim 10, further comprising, prior to forming the floating gate on the substrate: and forming a gate oxide layer on the substrate.
13. The method of claim 10, wherein after forming the first sidewall on the sidewall of the floating gate, and before sequentially forming an SAB thin film layer and a control gate layer on the substrate, the method further comprises: and carrying out ion implantation on the substrate to form a source doping region and a drain doping region.
14. The method as claimed in claim 11, wherein the SAB film includes an oxide layer and a nitride layer sequentially stacked on the surface of the floating gate, and the first sidewall and the second sidewall both have an ONO structure.
15. The method of claim 12, wherein the sequentially forming of the SAB film and the control gate on the floating gate comprises the steps of:
forming an SAB film material layer and a control gate material layer on the substrate;
forming a patterned photoresist layer on the control gate material layer by using an SAB mask;
and etching the control gate material layer and the SAB film material layer in sequence to form an SAB film and the control gate on the floating gate in sequence.
16. The method of claim 13, further comprising, after forming the SAB film and the control gate on the floating gate:
forming a self-aligned silicide layer on the substrate, wherein the self-aligned silicide layer covers the selection gate, the control gate, the source doped region and the drain doped region;
forming an interlayer dielectric layer on the substrate;
forming a contact hole exposing the selection gate, the control gate, the source doped region and the drain doped region in the interlayer dielectric layer;
filling a conductive material into the inner wall of the contact hole to form a conductive plug;
and forming a metal layer on the interlayer dielectric layer, and patterning the metal layer to form an electrode structure.
CN202010182566.6A 2020-03-16 2020-03-16 Unit structure of multi-time programmable memory and manufacturing method thereof Pending CN111430452A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113471206A (en) * 2021-09-06 2021-10-01 晶芯成(北京)科技有限公司 Multi-time programmable memory structure and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113471206A (en) * 2021-09-06 2021-10-01 晶芯成(北京)科技有限公司 Multi-time programmable memory structure and manufacturing method thereof

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