CN112310111B - Three-dimensional memory and manufacturing method thereof - Google Patents

Three-dimensional memory and manufacturing method thereof Download PDF

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CN112310111B
CN112310111B CN202011186454.4A CN202011186454A CN112310111B CN 112310111 B CN112310111 B CN 112310111B CN 202011186454 A CN202011186454 A CN 202011186454A CN 112310111 B CN112310111 B CN 112310111B
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马红霞
侯潇
陈德建
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

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Abstract

The invention provides a three-dimensional memory and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate with a stacking structure on the surface, wherein the stacking structure comprises a sacrificial layer and an isolation layer which are alternately stacked along the direction far away from the substrate, and a channel structure penetrating through the substrate is formed in the stacking structure; removing the sacrificial layer to form a plurality of first channels at positions corresponding to the sacrificial layer, wherein each first channel is communicated with the channel structure; sequentially forming a barrier layer and a gate layer on an inner surface of the first channel such that the barrier layer isolates the gate layer from the channel structure, the barrier layer comprising a plurality of high-K dielectric layers stacked sequentially on the inner surface, at least one of the high-K dielectric layers having a dielectric constant K1Satisfy 3.9-12, the dielectric constant of the rest high-K dielectric layers is larger than K1The barrier layer and the gate layer serve as components of a control gate structure. The method ensures that the device can have the advantages of reduced read-write erasing speed and effectively avoids the enhancement of the coupling effect of the device.

Description

Three-dimensional memory and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a three-dimensional memory and a manufacturing method thereof.
Background
In the prior art, a Flash Memory (Flash Memory) has a main function of maintaining stored information for a long time without power up, and has the advantages of high integration level, high access speed, easy erasing and rewriting and the like, so that the Flash Memory is widely applied to electronic products. In order to further improve the Bit Density (Bit Density) of the flash memory and at the same time reduce the Bit Cost (Bit Cost), a 3D NAND memory is further proposed.
In the current 3D NAND memory, a stacked 3D NAND memory structure is generally implemented by vertically stacking multiple layers of data storage units. In order to obtain the stacked 3D NAND memory structure, after a channel structure is formed, a stacked structure composed of a sacrificial layer and an isolation layer alternately needs to be formed on a silicon substrate, and a trench penetrating through the stacked structure is formed to expose a part of the sacrificial layer, so that the sacrificial layer is removed by wet etching, and then a control gate structure is formed at a position corresponding to the sacrificial layer.
Limited by the device size, as the aspect ratio of the channel formed at the corresponding position after the sacrificial layer is removed gradually increases, in order to make the deposited high-K dielectric layer have higher step coverage (S/C > 95%), it is inevitably necessary to reduce the dielectric constant of the high-K dielectric layer, however, the following relationship exists between the dielectric constant K, the physical thickness THK and the equivalent oxide layer thickness EOT:
K＝3.9×THK/EOT，
based on the above relationship, the decrease of the dielectric constant of the high-k dielectric layer may result in the increase of the equivalent oxide layer thickness, and the increase of the equivalent oxide layer thickness may result in the decrease of the read/write erasing speed of the device, thereby resulting in the enhancement of the device coupling effect.
Disclosure of Invention
The invention mainly aims to provide a three-dimensional memory and a manufacturing method thereof, and aims to solve the problem that the thickness of an equivalent oxide layer is increased due to the fact that the dielectric constant of a high-k dielectric layer in the three-dimensional memory is reduced in the prior art.
In order to achieve the above object, according to an aspect of the present invention, there is provided a method for fabricating a three-dimensional memory, including the steps of: providing a substrate with a stacking structure on the surface, wherein the stacking structure comprises a sacrificial layer and an isolation layer which are alternately stacked along the direction far away from the substrate, and a channel structure penetrating through the substrate is formed in the stacking structure; removing the sacrificial layer to form a plurality of first channels at positions corresponding to the sacrificial layer, wherein each first channel is communicated with the channel structure; sequentially forming a barrier layer and a gate layer on an inner surface of the first channel such that the barrier layer isolates the gate layer from the channel structure, the barrier layer comprising a plurality of high-K dielectric layers stacked sequentially on the inner surface, at least one of the high-K dielectric layers having a dielectric constant K1Satisfy 3.9-12, the dielectric constant of the rest high-K dielectric layers is larger than K1The barrier layer and the gate layer serve as components of a control gate structure.
Further, the barrier layer includes at least one first high-K dielectric layer and at least one second high-K dielectric layer, eachThe dielectric constant of the first high-K dielectric layer is selected from 3.9-121The dielectric constant of the second high-K dielectric layers is larger than that of the first high-K dielectric layers, and the dielectric constant of each second high-K dielectric layer is the same or different.
Furthermore, the first high-K dielectric layers and the second high-K dielectric layers are alternately arranged.
Further, the ratio of the sum of the thicknesses of the first high-K dielectric layers to the sum of the thicknesses of the second high-K dielectric layers is (1/2-1): 1.
further, the barrier layer is composed of a first high-K dielectric layer and a second high-K dielectric layer which are stacked; or the barrier layer consists of a first high-K dielectric layer and second high-K dielectric layers positioned on two sides of the first high-K dielectric layer; or the barrier layer consists of a second high-K dielectric layer and first high-K dielectric layers positioned on two sides of the second high-K dielectric layer.
Further, the material for forming each high-K dielectric layer is selected from HfO2、TiO2、HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3And BaSrTiO.
Further, the step of removing the sacrificial layer includes the following processes: forming gate isolation grooves penetrating to the substrate in the stacked structure; and removing the exposed sacrificial layer.
Further, after the step of forming the control gate structure, the manufacturing method further comprises the step of forming a conductive channel in the gate spacer.
According to another aspect of the present invention, there is also provided a three-dimensional memory including a substrate having a gate stack structure including control gate structures and isolation layers alternately stacked in a direction away from the substrate, the gate stack structure having a channel structure formed therein to penetrate the substrate, the control gate structure including: a gate layer; a barrier layer at least partially disposed between the gate layer and the channel structure, the barrier layer comprising a plurality of stacked high-K dielectric layers, at least one of the high-K dielectric layers having a dielectric constant K1Satisfy 3.9-12, the dielectric constant of the rest high-K dielectric layers is larger than K1。
Further, the barrier layer comprises at least one first high-K dielectric layer and at least one second high-K dielectric layer, and the dielectric constant of each first high-K dielectric layer is selected from 3.9-121The dielectric constant of the second high-K dielectric layers is larger than that of the first high-K dielectric layers, and the dielectric constant of each second high-K dielectric layer is the same or different.
Furthermore, the first high-K dielectric layers and the second high-K dielectric layers are alternately arranged.
Further, the ratio of the sum of the thicknesses of the first high-K dielectric layers to the sum of the thicknesses of the second high-K dielectric layers is (1/2-1): 1.
further, the barrier layer is composed of a first high-K dielectric layer and a second high-K dielectric layer which are stacked; or the barrier layer consists of a first high-K dielectric layer and second high-K dielectric layers positioned on two sides of the first high-K dielectric layer; or the barrier layer consists of a second high-K dielectric layer and first high-K dielectric layers positioned on two sides of the second high-K dielectric layer.
Further, each high-K dielectric layer is selected from HfO2、TiO2、HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3And BaSrTiO.
The manufacturing method comprises the steps of firstly providing a substrate with a stacking structure on the surface, wherein the stacking structure comprises sacrificial layers and isolating layers which are alternately stacked along the direction far away from the substrate, then removing the sacrificial layers, and sequentially forming a barrier layer and a gate layer on the inner surface of a first channel formed after the sacrificial layers are removed so that the barrier layer isolates the gate layer from a channel structure, wherein the barrier layer comprises a plurality of stacked high-K dielectric layers sequentially formed on the inner surface, and the dielectric constant K of at least one high-K dielectric layer1Satisfy 3.9-12, the dielectric constant of the rest high-K dielectric layers is larger than K1. The adjustment of the equivalent oxide layer thickness of the barrier layer can be realized by forming the composite multilayer high-K dielectric layer, so that the equivalent oxide layer thickness cannot be increased along with the reduction of the dielectric constant while the barrier layer reaches the required physical thickness, and the read-write erasing speed of the device can be reducedThe enhancement of the coupling effect of the device is slowly and effectively avoided.
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The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic cross-sectional view illustrating a substrate after a stacked structure is formed on a surface of the substrate in a method for fabricating a three-dimensional memory according to an embodiment of the present disclosure;
FIG. 2 is a schematic cross-sectional view of a substrate after forming a channel structure in the stacked structure shown in FIG. 1;
FIG. 3 is a cross-sectional view of the substrate after forming gate spacers in the stacked structure of FIG. 2;
FIG. 4 is a schematic cross-sectional view of the substrate after removing the sacrificial layer shown in FIG. 3;
FIG. 5 is a schematic cross-sectional view of the body after forming a select gate dielectric layer on the surface of the substrate in the gate spacer shown in FIG. 4;
FIG. 6 is a schematic cross-sectional view of the substrate after forming a control gate structure at the position of the sacrificial layer removed in FIG. 5;
FIG. 7 is a schematic cross-sectional view of a portion of the control gate structure and its vicinity shown in FIG. 6, wherein the control gate structure includes a barrier layer and a gate layer, and the barrier layer is composed of a first high-K dielectric layer and a second high-K dielectric layer which are stacked;
FIG. 8 is a schematic cross-sectional view of another portion of the control gate structure and its vicinity shown in FIG. 6, wherein the control gate structure includes a barrier layer and a gate layer, and the barrier layer is composed of a first high-K dielectric layer and a second high-K dielectric layer which are stacked;
FIG. 9 is a schematic cross-sectional view of a portion of the control gate structure and its vicinity shown in FIG. 6, wherein the control gate structure includes a blocking layer and a gate layer, the blocking layer is composed of a first high-K dielectric layer and a second high-K dielectric layer located on both sides of the first high-K dielectric layer;
FIG. 10 is a schematic cross-sectional view of a portion of the control gate structure and its vicinity shown in FIG. 6, wherein the control gate structure includes a blocking layer and a gate layer, the blocking layer is composed of a second high-K dielectric layer and first high-K dielectric layers on both sides of the second high-K dielectric layer;
FIG. 11 is a schematic cross-sectional view of the body after etching back the control gate structure of FIG. 7 to form an etch-back channel in communication with the gate spacer;
FIG. 12 is a schematic cross-sectional view of the body after forming a conductive via in the gate spacer of FIG. 11;
FIG. 13 is a schematic diagram illustrating a partial cross-sectional structure of a three-dimensional memory provided in an embodiment of the present application;
fig. 14 is a schematic cross-sectional view of a portion of the control gate structure and its vicinity of fig. 13, wherein the control gate structure includes a blocking layer and a gate layer, and the blocking layer is composed of a first high-K dielectric layer and a second high-K dielectric layer which are stacked;
FIG. 15 is a schematic cross-sectional view of another portion of the control gate structure and its vicinity shown in FIG. 13, wherein the control gate structure includes a barrier layer and a gate layer, the barrier layer being formed of a first high-K dielectric layer and a second high-K dielectric layer which are stacked;
FIG. 16 is a schematic cross-sectional view of the portion of the control gate structure and its vicinity shown in FIG. 13, wherein the control gate structure includes a blocking layer and a gate layer, the blocking layer is composed of a first high-K dielectric layer and a second high-K dielectric layer on both sides of the first high-K dielectric layer;
fig. 17 is a schematic cross-sectional view of a portion of the control gate structure and its vicinity shown in fig. 13, wherein the control gate structure includes a blocking layer and a gate layer, and the blocking layer is composed of a second high-K dielectric layer and first high-K dielectric layers on both sides of the second high-K dielectric layer.
Wherein the figures include the following reference numerals:
10. a substrate; 20. a sacrificial layer; 210. a first channel; 30. an isolation layer; 40. a channel structure; 410. a charge blocking layer; 420. a charge trapping layer; 430. a tunneling layer; 440. a channel layer; 450. filling an oxide layer; 50. a gate spacer; 60. a doped region; 70. selecting a gate dielectric layer; 80. a control gate structure; 810. a gate layer; 821. a first high-K dielectric layer; 822. a second high-K dielectric layer; 90. a sidewall insulating layer; 100. a conductive path.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As described in the background, the dielectric constant of the high-k dielectric layer in the prior art three-dimensional memory is reduced, resulting in an increased equivalent oxide thickness. The inventor of the present invention has made a study in view of the above problems, and proposes a method for manufacturing a three-dimensional memory, including the steps of:
s1, providing a substrate with a stacking structure on the surface, wherein the stacking structure comprises a sacrificial layer and an isolation layer which are alternately stacked along the direction far away from the substrate, and a channel structure penetrating through the substrate is formed in the stacking structure;
s2, removing the sacrificial layer to form a plurality of first channels at the positions corresponding to the sacrificial layer, wherein each first channel is communicated with the channel structure;
s3, sequentially forming a barrier layer and a gate layer on the inner surface of the first channel to isolate the gate layer from the channel structure, the barrier layer comprising a plurality of high-K dielectric layers sequentially stacked on the inner surface, at least one of the high-K dielectric layers having a dielectric constant K1Satisfy 3.9-12, the dielectric constant of the rest high-K dielectric layers is larger than K1The barrier layer and the gate layer serve as components of a control gate structure.
By adopting the manufacturing method of the three-dimensional memory, the adjustment of the equivalent oxide layer thickness of the barrier layer can be realized by forming the composite multilayer high-K dielectric layer, so that the equivalent oxide layer thickness of the barrier layer can not be increased along with the reduction of the dielectric constant when the barrier layer reaches the required physical thickness, thereby ensuring that the device can have the advantages of reduced read-write erasing speed and effectively avoiding the enhancement of the coupling effect of the device.
Exemplary embodiments of a method for fabricating a three-dimensional memory according to the present invention will be described in more detail with reference to the accompanying drawings. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
First, step S1 is executed: a substrate having a stacked structure including sacrificial layers 20 and isolation layers 30 alternately stacked in a direction away from the substrate is provided, and a channel structure 40 penetrating through to the substrate 10 is formed in the stacked structure, as shown in fig. 1 and 2.
The material of the substrate 10 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide.
In the step S1, the isolation layer 30 and the sacrificial layer 20 can be formed by a conventional deposition process in the prior art, such as a chemical vapor deposition process. The number of the sacrificial layer 20 and the isolation layer 30 can be set by those skilled in the art according to actual requirements, and those skilled in the art can also select the type of the isolation layer 30 and the sacrificial layer 20 according to the prior art, where the isolation layer 30 can be SiO2The sacrificial layer 20 may be SiN.
In the above step S1, the step of forming the channel structure may include the following processes: a channel via is formed in the stacked structure and a channel structure 40 is formed in the channel via as shown in fig. 2.
The channel structure 40 may be a charge trap type channel structure 40, and in this case, the step of forming the channel structure 40 includes: a charge blocking layer 410, a charge trapping layer 420, a tunneling layer 430 and a channel layer 440 are sequentially formed on the sidewall of the trench via, and the charge blocking layer 410 is covered on the sidewall of the trench via, as shown in fig. 2. The channel structure 40 may further include a filling oxide layer 450 covering an inner surface of the channel layer 440, as shown in fig. 2. The filling oxide layer 450 is typically SiO2It may be deposited using an ALC or CVD process in order to cover the channel layer 440.
The material of each functional layer in the channel structure 40 can be reasonably selected by one skilled in the art, for example, the material of the charge blocking layer 410 can be SiO2The charge trapping layer 420 may be SiN and the tunneling layer 430 may be SiO2The material of the channel layer 440 may be polysilicon. Moreover, a person skilled in the art may form the channel structure 40 by a conventional deposition process in the prior art, which is not described herein again.
After the above step S1 is completed, step S2 is performed: the sacrificial layer 20 is removed to form a plurality of first channels 210 at positions corresponding to the sacrificial layer 20, and each of the first channels 210 is in communication with the channel structure 40.
The above step S2 may include the following processes: forming gate spacers 50 through the substrate in the stacked structure to enable the sacrificial layer 20 to have exposed end faces; the sacrificial layer 20 is then wet etched with an etching solution starting from the above-mentioned exposed end face to remove the sacrificial layer 20, as shown in fig. 3 and 4.
After forming the gate spacer 50 in communication with the substrate 10, as shown in fig. 5, the above step S2 may further include forming a doped region 60 in a region of the substrate 10 in communication with the gate spacer 50, wherein the doped region 60 is of an opposite doping type to the substrate 10; after the step of forming the doped region 60, the step S3 may further include a step of forming a select gate dielectric layer 70 on the doped region 60, as shown in fig. 5.
After the above step S2 is completed, step S3 is performed: sequentially forming a barrier layer and a gate layer on an inner surface of the first channel such that the barrier layer isolates the gate layer from the channel structure, the barrier layer comprising a plurality of high-K dielectric layers stacked sequentially on the inner surface, at least one of the high-K dielectric layers having a dielectric constant K1Satisfy 3.9-12, the dielectric constant of the rest high-K dielectric layers is larger than K1The barrier layer and the gate layer serve as components of a control gate structure.
After the step S2, a first channel extending in the lateral direction can be formed at the position where the sacrificial layer 20 is removed by removing the sacrificial layer 20, and in the step S3, a high-K dielectric material and a gate material are sequentially deposited with the first channel as a deposition region to obtain the control gate structure 80 including the barrier layer and the gate layer 810, wherein the deposition process may be Atomic Layer Deposition (ALD).
The barrier layer can comprise at least one first high-K dielectric layer and at least one second high-K dielectric layer, and the dielectric constant of each first high-K dielectric layer is independently selected from 3.9-121The dielectric constant of the second high-K dielectric layer is greater than that of the first high-K dielectric layer, and eachThe dielectric constants of the second high-K dielectric layers are the same or different.
In order to better realize the adjustment of the equivalent oxide layer thickness of the barrier layer, preferably, the first high-K dielectric layers and the second high-K dielectric layers are alternately arranged; preferably, the ratio of the sum of the thicknesses of the first high-K dielectric layers to the sum of the thicknesses of the second high-K dielectric layers is (1/2-1): 1.
in a preferred embodiment, the barrier layer is composed of a first high-K dielectric layer 821 and a second high-K dielectric layer 822 stacked, and the first high-K dielectric layer 821 wraps the surface of the gate layer 810, as shown in fig. 7.
In another preferred embodiment, the barrier layer is composed of a first high-K dielectric layer 821 and a second high-K dielectric layer 822 stacked, and the second high-K dielectric layer 822 wraps the surface of the gate layer 810, as shown in fig. 8.
In another preferred embodiment, the barrier layer is composed of a first high-K dielectric layer 821 and a second high-K dielectric layer 822 disposed on both sides of the first high-K dielectric layer 821, as shown in fig. 9.
In another preferred embodiment, the barrier layer is composed of a second high-K dielectric layer 822 and a first high-K dielectric layer 821 on both sides of the second high-K dielectric layer 822, as shown in fig. 10.
The high-K dielectric materials forming the high-K dielectric layer can be respectively and independently selected from HfO2、TiO2、HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3And one or more of BaSrTiO; the gate material is usually a metal, and may be one or more selected from W, Al, Cu, Ti, Ag, Au, Pt, and Ni.
After the step of forming the control gate structure 80, the step S3 further includes a step of forming a conductive via 100 in the gate spacer 50, as shown in fig. 11 and 12.
In the above step of forming the conductive via 100, the sidewall insulating layer 90 may be deposited in the gate isolation trench 50, and then the conductive via 100 may be deposited in the gate isolation trench 50 covered with the sidewall insulating layer 90. The conductive channel 100 is isolated from the gate layer 810 by the sidewall insulating layer 90, the channel structure 40 forms a common source connection via the substrate 10, and the conductive channel 100 provides a conductive path connecting the common source to the source line.
In a preferred embodiment, the step of forming the conductive via 100 includes the steps of: etching back the control gate structure 80 to form an etch back channel in communication with the gate spacer 50, as shown in fig. 11; filling the etching-back channel and the gate isolation groove 50 with insulating materials, etching the insulating materials in the gate isolation groove 50 to form a side wall insulating layer 90, and forming an etching channel in the remaining area in the gate isolation groove 50; conductive vias 100 are formed in the etched channels as shown in fig. 12.
According to another aspect of the present invention, there is also provided a three-dimensional memory, as shown in fig. 13 to 17, including a substrate 10 having a gate stack structure including a control gate structure 80 and isolation layers 30, the control gate structure 80 and the isolation layers 30 being alternately stacked in a direction away from the substrate 10, a channel structure 40 formed in the gate stack structure and penetrating through the substrate 10, the control gate structure 80 including a gate layer 810 and a blocking layer, at least a portion of the blocking layer being disposed between the gate layer and the channel structure, the blocking layer including a plurality of stacked high-K dielectric layers, at least one of the high-K dielectric layers having a dielectric constant K1Satisfy 3.9-12, the dielectric constant of the rest high-K dielectric layers is larger than K1。
The adjustment of the equivalent oxide layer thickness of the barrier layer can be realized through the composite multilayer high-K dielectric layer, so that the equivalent oxide layer thickness of the barrier layer can not be increased along with the reduction of the dielectric constant when the barrier layer reaches the required physical thickness, and the device can be ensured to have the advantages of reduced read-write erasing speed and effectively avoided the enhancement of the coupling effect of the device.
The barrier layer can comprise at least one first high-K dielectric layer and at least one second high-K dielectric layer, and the dielectric constant of each first high-K dielectric layer is independently selected from 3.9-121The dielectric constant of the second high-K dielectric layers is larger than that of the first high-K dielectric layers, and the dielectric constant of each second high-K dielectric layer is the same or different.
In order to better realize the adjustment of the equivalent oxide layer thickness of the barrier layer, preferably, the first high-K dielectric layers and the second high-K dielectric layers are alternately arranged; preferably, the ratio of the sum of the thicknesses of the first high-K dielectric layers to the sum of the thicknesses of the second high-K dielectric layers is (1/2-1): 1.
in a preferred embodiment, the barrier layer is composed of a first high-K dielectric layer 821 and a second high-K dielectric layer 822 stacked, and the first high-K dielectric layer 821 wraps the surface of the gate layer 810, as shown in fig. 14.
In the first embodiment of the present invention, the barrier layer is composed of a first high-K dielectric layer 821 and a second high-K dielectric layer 822 stacked, the first high-K dielectric layer 821 wraps the surface of the gate layer 810, and the first high-K dielectric layer 821 has a thickness
Figure BDA0002751562970000081
Of the HfO, the second high-K dielectric layer 822 is thick
Figure BDA0002751562970000082
Al of (2)2O3. Only Al in the prior art2O3The equivalent oxide thickness of the formed barrier layer with equal thickness, EOT ≈ 1.136, whereas the equivalent oxide thickness of the barrier layer in the above-mentioned embodiment, EOT ≈ 0.913, can have a lower equivalent oxide.
In another preferred embodiment, the barrier layer is composed of a first high-K dielectric layer 821 and a second high-K dielectric layer 822 stacked, and the second high-K dielectric layer 822 wraps the surface of the gate layer 810, as shown in fig. 15.
In the second embodiment of the present invention, the barrier layer is composed of a first high-K dielectric layer 821 and a second high-K dielectric layer 822 stacked, the second high-K dielectric layer 822 wraps the surface of the gate layer 810, and the first high-K dielectric layer 821 has a thickness
Figure BDA0002751562970000083
Of the HfO, the second high-K dielectric layer 822 is thick
Figure BDA0002751562970000084
Al of (2)2O3. Only Al in the prior art2O3The formed barrier layer with the same thickness, in the above embodiment, the equivalent oxide thickness EOT of the barrier layer is about equal to 0.913, so that the barrier layer can have a lower equivalent oxide.
In another preferred embodiment, the barrier layer is formed by a first high-K dielectric layer 821 and a second high-K dielectric layer 822 on both sides of the first high-K dielectric layer 821, as shown in fig. 16.
In the third embodiment of the present invention, the blocking layer is composed of a first high-K dielectric layer 821 and a second high-K dielectric layer 822 disposed on two sides of the first high-K dielectric layer 821, wherein the first high-K dielectric layer 821 has a thickness
Figure BDA0002751562970000085
Of HfO, each second high-K dielectric layer 822 having a thickness
Figure BDA0002751562970000086
Al of (2)2O3. Only Al in the prior art2O3The formed barrier layer with the same thickness, in the above embodiment, the equivalent oxide thickness EOT of the barrier layer is about equal to 0.913, so that the barrier layer can have a lower equivalent oxide.
In another preferred embodiment, the barrier layer is formed by a second high-K dielectric layer 822 and a first high-K dielectric layer 821 on both sides of the second high-K dielectric layer 822, as shown in fig. 17.
In the fourth embodiment of the present invention, the blocking layer is composed of a second high-K dielectric layer 822 and first high-K dielectric layers 821 located at two sides of the second high-K dielectric layer 822, wherein the first high-K dielectric layers 821 have a thickness
Figure BDA0002751562970000087
Of HfO, each second high-K dielectric layer 822 having a thickness
Figure BDA0002751562970000088
Al of (2)2O3. Only Al in the prior art2O3Barrier layers of equal thickness formed as in the previous examplesThe equivalent oxide thickness EOT of the barrier layer is approximately equal to 0.913, so that the barrier layer can have a lower equivalent oxide.
The high-K dielectric materials forming the high-K dielectric layer can be respectively and independently selected from HfO2、TiO2、HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3And one or more of BaSrTiO; the gate material is usually a metal, and may be one or more selected from W, Al, Cu, Ti, Ag, Au, Pt, and Ni.
The channel structure 40 may be a charge trap type channel structure, and specifically may include a charge blocking layer 410, a charge trapping layer 420, a tunneling layer 430, and a channel layer 440, which are stacked, where the charge blocking layer 410 is in contact with the control gate structure, as shown in fig. 14 to 17. The channel structure 40 may further include a filling oxide layer 450 covering an inner surface of the channel layer 440, as shown in fig. 2. The filling oxide layer 450 is typically SiO2In order to cover the channel layer 440.
From the above description, it can be seen that the above-described embodiments of the present invention achieve the following technical effects:
the adjustment of the equivalent oxide layer thickness of the barrier layer can be realized by forming the composite multilayer high-K dielectric layer, so that the equivalent oxide layer thickness of the barrier layer can not be increased along with the reduction of the dielectric constant when the barrier layer reaches the required physical thickness, thereby ensuring that the device can have the advantages of reducing the read-write erasing speed and effectively avoiding the enhancement of the coupling effect of the device.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A method for manufacturing a three-dimensional memory is characterized by comprising the following steps:
providing a substrate having a stacked structure on a surface thereof, the stacked structure including a sacrificial layer and an isolation layer alternately stacked in a direction away from the substrate, forming a channel structure penetrating through to the substrate in the stacked structure;
removing the sacrificial layer to form a plurality of first channels at positions corresponding to the sacrificial layer, wherein each first channel is communicated with the channel structure;
sequentially forming a barrier layer and a gate layer on an inner surface of the first channel such that the barrier layer isolates the gate layer from the channel structure, the barrier layer comprising a plurality of high-K dielectric layers stacked sequentially on the inner surface, at least one of the high-K dielectric layers having a dielectric constant K1Satisfy 3.9-12, the dielectric constant of the rest high-K dielectric layers is larger than K1Said barrier layer and said gate layer being integral parts of a control gate structure,
the barrier layer comprises at least one first high-K dielectric layer and at least one second high-K dielectric layer, the dielectric constant of each first high-K dielectric layer is selected from 3.9-12, the dielectric constant of each second high-K dielectric layer is larger than that of each first high-K dielectric layer, the dielectric constants of the second high-K dielectric layers are the same or different,
the ratio of the sum of the thicknesses of the first high-K dielectric layers to the sum of the thicknesses of the second high-K dielectric layers is (1/2-1): 1.
2. the method of claim 1, wherein the first high-K dielectric layers and the second high-K dielectric layers are alternately disposed.
3. The method of manufacturing according to claim 1,
the barrier layer is composed of the first high-K dielectric layer and the second high-K dielectric layer which are stacked; or
The barrier layer consists of the first high-K dielectric layer and second high-K dielectric layers positioned on two sides of the first high-K dielectric layer; or
The barrier layer is composed of the second high-K dielectric layer and the first high-K dielectric layers positioned on two sides of the second high-K dielectric layer.
4. The method as claimed in any one of claims 1 to 3, wherein the material forming each high-K dielectric layer is selected from HfO2、TiO2、HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3And BaSrTiO.
5. A method of manufacturing according to any one of claims 1 to 3, wherein the step of removing the sacrificial layer comprises the process of:
forming gate spacers penetrating to the substrate in the stacked structure;
and removing the exposed sacrificial layer.
6. The method of manufacturing according to claim 5, wherein after the step of forming the control gate structure, the method of manufacturing further comprises a step of forming a conductive channel in the gate spacer.
7. A three-dimensional memory comprising a substrate having a gate stack structure, the gate stack structure including a control gate structure and isolation layers, the control gate structure and the isolation layers being alternately stacked in a direction away from the substrate, the gate stack structure having a channel structure formed therein through to the substrate, the control gate structure comprising:
a gate layer;
a barrier layer, at least a portion of the barrier layer being disposed between the gate layer and the channel structure, the barrier layer comprising a plurality of stacked high-K dielectric layers, at least one of the high-K dielectric layers having a dielectric constant K1Satisfy 3.9-12, the dielectric constant of the rest high-K dielectric layers is larger than K1，
The barrier layer comprises at least one first high-K dielectric layer and at least one second high-K dielectric layer, the dielectric constant of each first high-K dielectric layer is selected from 3.9-12, the dielectric constant of each second high-K dielectric layer is larger than that of each first high-K dielectric layer, the dielectric constants of the second high-K dielectric layers are the same or different,
the ratio of the sum of the thicknesses of the first high-K dielectric layers to the sum of the thicknesses of the second high-K dielectric layers is (1/2-1): 1.
8. the three-dimensional memory according to claim 7, wherein the first high-K dielectric layers and the second high-K dielectric layers are alternately arranged.
9. The three-dimensional memory according to claim 7,
the barrier layer is composed of the first high-K dielectric layer and the second high-K dielectric layer which are stacked; or
The barrier layer consists of the first high-K dielectric layer and second high-K dielectric layers positioned on two sides of the first high-K dielectric layer; or
The barrier layer is composed of the second high-K dielectric layer and the first high-K dielectric layers positioned on two sides of the second high-K dielectric layer.
10. The three-dimensional memory according to any one of claims 7 to 9, wherein each high-K dielectric layer is selected from HfO2、TiO2、HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3And BaSrTiO.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9812462B1 (en) * 2016-06-07 2017-11-07 Sandisk Technologies Llc Memory hole size variation in a 3D stacked memory
CN107533978A (en) * 2015-06-04 2018-01-02 东芝存储器株式会社 Semiconductor storage and its manufacture method
CN109887926A (en) * 2019-02-01 2019-06-14 长江存储科技有限责任公司 A kind of three-dimensional storage and preparation method thereof
CN111415943A (en) * 2020-05-21 2020-07-14 长江存储科技有限责任公司 Method for manufacturing three-dimensional memory
CN112259542A (en) * 2020-10-14 2021-01-22 长江存储科技有限责任公司 Three-dimensional memory and manufacturing method thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110135692A (en) * 2010-06-11 2011-12-19 삼성전자주식회사 Three dimensional semiconductor memory device and method for manufacturing the same
US9997535B2 (en) * 2016-03-18 2018-06-12 Toshiba Memory Corporation Semiconductor memory device and method of manufacturing the same
CN111244096B (en) * 2020-03-27 2022-11-25 长江存储科技有限责任公司 3D NAND memory device and method of manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107533978A (en) * 2015-06-04 2018-01-02 东芝存储器株式会社 Semiconductor storage and its manufacture method
US9812462B1 (en) * 2016-06-07 2017-11-07 Sandisk Technologies Llc Memory hole size variation in a 3D stacked memory
CN109887926A (en) * 2019-02-01 2019-06-14 长江存储科技有限责任公司 A kind of three-dimensional storage and preparation method thereof
CN111415943A (en) * 2020-05-21 2020-07-14 长江存储科技有限责任公司 Method for manufacturing three-dimensional memory
CN112259542A (en) * 2020-10-14 2021-01-22 长江存储科技有限责任公司 Three-dimensional memory and manufacturing method thereof

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