CN115664427A - Communication system and method based on serial and deserialized SerDes models - Google Patents
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Abstract
The invention belongs to the technical field of data information transmission and electric data processing, and particularly relates to a communication system and a method based on a serial and deserialized SerDes model.
Description
Technical Field
The invention belongs to the technical field of data information transmission and electric data processing, and particularly relates to a communication system and method based on a serial and deserializing SerDes model.
Background
With the continuous increase of the demand for information flow, the traditional parallel interface technology becomes the bottleneck of further improving the data transmission rate, in the past, the serial communication technology mainly used for optical fiber communication, SERDES, is replacing the traditional parallel bus to become the mainstream of the high-speed interface technology, SERDES is the abbreviation of english SERializer/DESerializer, wherein the SERializer and DESerializer are responsible for the conversion from parallel to serial and from serial to parallel, the SERializer needs a clock generation circuit, and the clock generation circuit is usually realized by a phase-locked loop (PLL); deserializers require clock and data recovery Circuits (CDRs); however, in the verification process, the model of the real servers is located later, which affects the verification progress;
the prior art has the problems that the reset time is long due to the fact that clock circuits for serial connection and deserialization are complex, and the verification speed is further influenced.
Disclosure of Invention
The invention provides a communication system and a method based on serial and deserializing SerDes models, which aim to solve the problems that in the prior art, due to the fact that a clock circuit for serial and deserializing is complex, the reset time is long, and the verification speed is affected.
The technical problem solved by the invention is realized by adopting the following technical scheme: the communication system based on the serial and deserializing SerDes model comprises a serial deserializer and a deserializer, wherein the serial deserializer comprises a serial unit and a deserializing unit, the serial unit is connected with a parallel transmitting input end group and a serial transmitting output end, and the deserializing unit is connected with a serial receiving input end group and a parallel receiving output end group;
under the control of a sending clock, parallel sending data is converted into serial sending data through parallel-to-serial conversion of a serial unit;
under the control of the receiving clock, serial receiving data is converted into parallel receiving data through serial-to-parallel conversion by the deserializing unit.
Further, the serializer and deserializer further comprises:
the parallel transmitting input end group comprises parallel input ends DPIT 0 Input end DPIT n-1 The serial transmission output end DPOT;
the parallel receiving output end group comprises parallel output ends DPOR 0 Output end DPOR n-1 The serial receive input terminal DPIR;
where n is the data word length.
Further, the serializer and deserializer further comprises: the transmit clock is divided by a divider to a receive clock.
Further, the serializer and deserializer further comprises:
under the control of a sending clock, parallel sending data is converted into serial sending data through a sending shift register of a serial unit;
under the control of the reception clock, the serial reception data is converted into parallel reception data by the reception shift register of the deserializing unit.
Further, the serializer and deserializer further comprises:
the shifting sequence of the sending shift register is from low bit shifting to high bit shifting;
the shift order of the receiving shift register is from high to low.
Meanwhile, the invention also provides a communication method based on the serial and deserialized SerDes models, which comprises the following steps: a parallel-to-serial method and a serial-to-parallel method;
communication system based on the above-mentioned SerDes model:
the parallel-serial method comprises the following steps: the serial unit read input terminal DPIT 0 Input end DPIT n-1 Input parallel transmission input data DT n-1 ~DT 0 The serial unit sends input data DT in parallel through the sending shift register n-1 ~DT 0 Converting the serial transmission output data DTX into serial transmission output data DTX, and sequentially transmitting the serial transmission output data DTX from a low bit to a high bit by the serial unit through the serial transmission output end DPOT under the control of a transmission clock time sequence;
the serial-to-parallel method comprises the following steps: under the control of the receiving clock time sequence, the deserializing unit reads the serial receiving input data DRX in sequence from low bit to high bit, and converts the serial receiving input data DRX into parallel receiving output data DR through the receiving shift register n-1 ~DR 0 The deserializing unit passes through the parallel output terminal DPOR 0 To output end DPOR n-1 Output parallel reception output data DR n-1 ~DR 0 ；
Where n is the data word length.
Further, the communication method of the SerDes model further includes:
the sending clock is output to the receiving clock by frequency division of a frequency divider N, wherein N is a positive integer.
Further, the parallel-to-serial method further comprises the following steps:
the serial unit transmits the serial transmission output data DTX according to the bit DTX through the serial transmission output end DPOT 0 Bit DTX 1 Bit DTX 2 Bit DTX of changing into n-1 And sequentially sending.
Further, the serial-parallel conversion method further comprises the following steps:
the deserializing unit DRX according to bit 0 Bit DRX 1 Bit DRX 2 A n-1 Sequentially reading the serial reception input data DRX.
Further, the method of communication of the SerDes model further comprises:
the deserializing unit serially receives the input data DRX by receiving sequential left shifts of the shift register.
The beneficial technical effects are as follows:
the scheme adopts that the serializer and deserializer comprises a serial unit and a deserializing unit, wherein the serial unit is connected with a parallel transmitting input end group and a serial transmitting output end, and the deserializing unit is connected with a serial receiving input end group and a parallel receiving output end group; under the control of a sending clock, parallel sending data is converted into serial sending data through parallel-to-serial conversion of a serial unit; under the control of a receiving clock, serial receiving data are converted into parallel receiving data through serial-parallel conversion of a deserializing unit, and the system comprises a data sending end and a data receiving end, wherein the data sending end converts the parallel data into serial data under the control of a system clock sclk and then sends the serial data to the data receiving end; the data receiving end converts received serial data into parallel data under the control of a system clock sclk, the method is used before real servers are not in place, a single bit high-speed channel line on a high-speed interface can be converted into the parallel data by using the ideal servers model, then the parallel data are in butt joint with the dut, and then next debugging work is carried out.
Drawings
FIG. 1 is a schematic diagram of the architecture of a communication system of the SerDes model of the present invention;
FIG. 2 is a general flow chart of a method of communication for the SerDes model of the present invention;
FIG. 3 is a detailed flow chart of a method of communication of the SerDes model of the present invention;
fig. 4 is a schematic structural diagram of a first embodiment of a communication method of the SerDes model according to the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings:
in the figure:
the device comprises a 1-serial deserializer, a 2-serial unit, a 3-deserializer, a 4-parallel sending input end group, a 5-serial sending output end, a 6-serial receiving input end, a 7-parallel receiving output end group, an 8-sending clock, a 9-receiving clock, a 10-frequency divider, an 11-sending shift register and a 12-receiving shift register.
S101-parallel-serial method;
s102-serial-parallel conversion method;
S1000-SerDes model-based communication systems;
s1001-the serial cell read input DPIT 0 Input end DPIT n-1 Input parallel transmission input data DT n-1 ~DT 0 ；
S1002-Serial Unit will parallel-Send input data DT through Send Shift register n-1 ~DT 0 Converting into serial sending output data DTX;
s1003-under the control of the sending clock time sequence, the serial unit sends serial sending output data DTX in sequence from low bit to high bit through the serial sending output end DPOT;
s2001-under the control of the receiving clock time sequence, the deserializing unit reads the serial receiving input data DRX in sequence from low bit shift to high bit shift;
s2002-deserializing Unit converts Serial receive input data DRX to parallel receive output data DR through receive Shift register n-1 ~DR 0 ；
S2003-deserializing unit through parallel output terminal DPOR 0 To output end DPOR n-1 Output parallel reception output data DR n-1 ~DR 0 ；
Example (b):
in this embodiment:
the communication system based on the serial and deserializing SerDes model comprises a serializer and deserializer 1, wherein the serializer and deserializer 1 comprises a serial unit 2 and a deserializing unit 3, the serial unit 2 is connected with a serial transmitting input end group 4 and a serial transmitting output end group 5, and the deserializing unit 3 is connected with a serial receiving input end group 6 and a parallel receiving output end group 7;
under the control of the transmission clock 8, parallel transmission data is converted into serial transmission data through parallel-to-serial conversion by the serial unit 2;
under the control of the reception clock 9, the serial reception data is serial-to-parallel converted into parallel reception data by the deserializing unit 3.
As shown in fig. 1, the serializer and deserializer includes a serial unit and a deserializer unit, the serial unit connects the parallel transmitting input end group and the serial transmitting output end, and the deserializer unit connects the serial receiving input end group and the parallel receiving output end group; under the control of a sending clock, parallel sending data is converted into serial sending data through parallel-to-serial conversion of a serial unit; under the control of a receiving clock, serial receiving data are converted into parallel receiving data through serial-parallel conversion of a deserializing unit, and the system comprises a data sending end and a data receiving end, wherein the data sending end converts the parallel data into serial data under the control of a system clock sclk and then sends the serial data to the data receiving end; the data receiving end converts received serial data into parallel data under the control of a system clock sclk, the method is used before real servers are not in place, a single-bit high-speed channel line on a high-speed interface can be converted into the parallel data by using the ideal servers model, then the parallel data are in butt joint with the dut, and then next debugging work is carried out.
The serializer and deserializer 1 further includes:
the parallel sending input end group 4 comprises parallel input ends DPIT 0-DPITn-1 and a serial sending output end 5DPOT;
the parallel receiving output end group 7 comprises a parallel output end DPOR 0-an output end DPORn-1, and the serial receiving input end 6DPIR;
where n is the data word length.
Due to the adoption of the serial deserializer, the method further comprises the following steps: the parallel transmitting input end group comprises parallel input ends DPIT 0 Input end DPIT n-1 The serial transmission output end DPOT; the parallel receiving output end group comprises parallel output ends DPOR 0 To output end DPOR n-1 The serial receive input terminal DPIR; wherein, n is the data word length, because the scheme adopts parallel input for transmission, the parallel port is DPIT 0 、DPIT 1 、DPIT 2 、DPIT 3 、DPIT 4 、DPIT 5 、DPIT 6 .......DPIT n-2 、DPIT n-1 The serial transmission output end DPOT is asynchronous serial output, the scheme adopts serial input, the serial port is DPIR, and the parallel receiving port isIs DPOR 0 、DPOR 1 、DPOR 2 、DPOR 3 、DPOR 4 、DPOR 5 、DPOR 6 .......DPOR n-2 、DPOR n-1 The output end is synchronous parallel output, the parallel transmission has the characteristics of high speed and accurate transmission, the serial transmission has the advantages of long transmission distance and strong loading capacity, and the serial-parallel conversion or the parallel-serial conversion has strong adaptability and high transmission rate.
The serializer and deserializer 1 further includes: the transmit clock 8 is divided by a divider 10 in frequency to the receive clock 9.
The sending clock is divided by the frequency divider from the receiving clock, and one clock is reduced by the frequency divider, so that the cost is reduced, the structure is simplified, the synchronization effect is good, and the expansion and the debugging are easy.
The serializer and deserializer 1 further comprises:
the parallel transmission data is converted into serial transmission data by the transmission shift register 11 of the serial unit 2 under the control of the transmission clock 8;
under the control of the reception clock 9, the serial reception data is converted into parallel reception data by the reception shift register 12 of the deserializing unit 3.
Due to the adoption of the serial deserializer, the method further comprises the following steps: under the control of a sending clock, parallel sending data is converted into serial sending data through a sending shift register of a serial unit; under the control of a receiving clock, serial receiving data is converted into parallel receiving data through a receiving shift register of a deserializing unit, and the shift operation realized by hardware has the advantages of high speed and high efficiency because the parallel data is converted into the serial data through the shift register.
The serializer and deserializer 1 further includes:
the shift order of the transmission shift register 11 is from low to high;
the shift order of the receiving shift register 12 is from high to low.
Due to the adoption of the serial deserializer, the method further comprises the following steps: the shifting sequence of the sending shift register is from low bit to high bit; the shift sequence of the receiving shift register is from high bit to low bit, and the shift sequence is convenient for transmission and reception because the transmitting shift sequence is from low bit to high bit and the receiving shift sequence is from high bit to low bit.
A method of communication based on a serial and deserialized SerDes model, comprising: a parallel-to-serial method S101 and a serial-to-parallel method S102;
communication system S1000 based on the SerDes model described above:
parallel-serial method S101: the serial unit 2 reads parallel sending input data DTn-1 to DT0S 1001 input from an input end DPIT0 to an input end DPITn-1, the serial unit 2 converts the parallel sending input data DTn-1 to DT0 into serial sending output data DTX S1002 through a sending shift register 11, and under the time sequence control of a sending clock 8, the serial unit 2 sends the serial sending output data DTX in sequence from a low bit to a high bit through a serial sending output end 5DPOT S1003;
serial-parallel method S102: under the time sequence control of a receiving clock 9, the deserializing unit 3 sequentially reads serial receiving input data DRX S2001 from a low bit to a high bit, the deserializing unit 3 converts the serial receiving input data DRX into parallel receiving output data DRn-1 to DR0 S2002 through a receiving shift register 12, and the serial unit 2 outputs the parallel receiving output data DRn-1 to DR0 S2003 through parallel output ends DPOR0 to DPORn-1;
where n is the data word length.
As shown in fig. 2 and 3, the present invention also provides a serial and deserialized SerDes model-based communication method, which is characterized by comprising: a parallel-to-serial method and a serial-to-parallel method; communication system based on the above-mentioned SerDes model: the parallel-serial method comprises the following steps: the serial unit read input terminal DPIT 0 Input end DPIT n-1 Input parallel transmission input data DT n-1 ~DT 0 The serial unit transmits input data DT in parallel through the transmission shift register n-1 ~DT 0 Converting into serial transmission output data DTX, and shifting the serial transmission output data DTX from low bit to low bit by the serial unit through the serial transmission output end DPOT under the control of transmission clock time sequenceSequentially sending high-order bits; the serial-to-parallel method comprises the following steps: under the control of a receiving clock time sequence, the deserializing unit sequentially reads serial receiving input data DRX from a low bit to a high bit, the deserializing unit converts the serial receiving input data DRX into parallel receiving output data DRn-1 to DR0 through a receiving shift register, and the serial unit outputs the parallel receiving output data DRn-1 to DR0 through parallel output ends DPOR0 to an output end DPORn-1; wherein, n is the data word length, and the data transmitting end converts the parallel data into serial data under the control of the system transmitting clock; then, the data receiving end converts the received serial data into parallel data under the control of the receiving clock, the receiving end and the transmitting end structure of the ideal SerDes model of the invention comprises: the data sending end completes parallel-serial connection of data; the data receiving end completes serial-parallel conversion of data; the serial-parallel clock generator comprises a data sending end, a data receiving end and a data receiving end, wherein the data sending end converts input 32-bit parallel data d31-d0 into serial data d0, d1, d31 under the control of a sending clock, the serial data d0, d1 and d31 are sent out, the data sending end firstly sends the d0, d1 and d31, the data receiving end puts bit data on the 0 th bit of a 32-bit shift register under the control of a receiving clock and then continuously moves left to obtain 32-bit parallel data, the period of psclk is incomplete, and therefore the 32-bit parallel data needs to be obtained by carrying out corresponding frequency division through the receiving clock.
The communication method of the SerDes model further comprises the following steps:
the transmission clock 8 is divided by a divider 10N, where N is a positive integer, and output to the reception clock 9.
The communication method adopting the SerDes model further comprises the following steps: the sending clock is output to the receiving clock through N frequency division of the frequency divider, wherein N is a positive integer, the N frequency division of the frequency divider can be set and adjusted, the flexibility is high, and the practicability is high.
The parallel-to-serial method S101 further includes:
the serial unit 2 sequentially transmits serial transmission output data DTX according to bit DTX0, bit DTX1 and bit DTX2.
The serial-to-parallel method S102 further includes:
the deserializing unit 3 sequentially reads the serial receiving input data DRX according to the bit DRX0, the bit DRX1, the bit DRX2 and the.
The parallel-serial method further comprises the following steps: the serial unit sequentially sends serial sending output data DTX according to bit DTX0, bit DTX1 and bit DTX2. The SerDes model communication method, wherein the serial-to-parallel method further comprises: the deserializing unit sequentially reads the serial receiving input data DRX according to the bit DRX0, the bit DRX1, the bit DRX2 and the.
The method of communication of the SerDes model further comprises:
the deserializing unit 3 serially receives the input data DRX by sequential left shifting of the receive shift register 12.
The communication method adopting the SerDes model further comprises the following steps: the deserializing unit receives input data DRX in series through sequential left shifting of a receiving shift register, the shift register sends the received serial data to parallel data, and a sending clock is adopted as a working clock; and the received shift register is used for converting the parallel data into single Bit serial data, and the working clock adopts a receiving clock.
The first embodiment is as follows:
as shown in fig. 4, a schematic diagram of a receiving end and a transmitting end of an ideal SerDes model according to the present invention includes: the data sending end completes parallel-serial connection of data; the data receiving end completes serial-parallel conversion of data; a serial-parallel clock generator, wherein the data transmitting end converts the input 32-bit parallel data d31-d0 into serial data d0, d 1.. And d31 under the control of a clock psclk (322.265625 MHz), and transmits the serial data; firstly transmitting d0, then transmitting d1, and finally transmitting d31, wherein the data receiving end firstly puts single-bit data on the 0 th bit of the 32-bit shift register under the control of a system clock spclk (10.3125 GHz), and then continuously shifts left to obtain 32-bit parallel data, wherein the periods of the psclk (322.265625 MHz) and the 322.265625MHz are inexhaustible, so that the data are obtained by carrying out frequency division of 40 through the spclk (10.3125 GHz).
The working principle is as follows:
the scheme adopts the technical scheme that the serializer and deserializer comprises a serial unit and a deserializing unit, wherein the serial unit is connected with a parallel sending input end group and a serial sending output end, and the deserializing unit is connected with a serial receiving input end and a parallel receiving output end group; under the control of a sending clock, parallel sending data is converted into serial sending data through parallel-to-serial conversion of a serial unit; under the control of a receiving clock, serial receiving data are converted into parallel receiving data through serial-parallel conversion of a deserializing unit, and the system comprises a data sending end and a data receiving end, wherein the data sending end converts the parallel data into serial data under the control of a system clock sclk and then sends the serial data to the data receiving end; the invention is used before the real servers are not in place, the ideal servers model can be used for converting a single-bit high-speed channel line on a high-speed interface into parallel data, then the parallel data is butted with the dut, and then the next debugging work is carried out.
The technical solutions of the present invention or those skilled in the art, based on the inspiration of the technical solutions of the present invention, may design similar technical solutions to achieve the above technical effects, which are all considered to fall within the protection scope of the present invention.
Claims (10)
1. The communication system based on the serial and deserialized SerDes model is characterized by comprising a serial deserializer and a deserializer, wherein the serial deserializer comprises a serial unit and a deserializing unit, the serial unit is connected with a parallel transmitting input end group and a serial transmitting output end, and the deserializing unit is connected with a serial receiving input end group and a parallel receiving output end group;
under the control of a sending clock, parallel sending data is converted into serial sending data through parallel-to-serial conversion of a serial unit;
under the control of the receiving clock, serial receiving data is converted into parallel receiving data through serial-to-parallel conversion by the deserializing unit.
2. The SerDes model communication system of claim 1, wherein the serializer and deserializer further comprises:
the parallel transmitting input end group comprises parallel input ends DPIT 0 Input end DPIT n-1 The serial transmission output end DPOT;
the parallel receiving output end group comprises parallel output ends DPOR 0 To output end DPOR n-1 -said serial reception input terminal DPIR;
where n is the data word length.
3. The SerDes model communication system of claim 1, wherein the serializer and deserializer further comprises: the transmit clock is divided by a divider to a receive clock.
4. The SerDes model communication system according to claim 1, wherein the serializer and deserializer further comprises:
under the control of a sending clock, parallel sending data is converted into serial sending data through a sending shift register of a serial unit;
under the control of the receiving clock, the serial receiving data is converted into parallel receiving data through the receiving shift register of the deserializing unit.
5. The SerDes model communication system of claim 1, wherein the serializer and deserializer further comprises:
the shifting sequence of the sending shift register is from low bit to high bit;
the shift order of the receiving shift register is from high to low.
6. A communication method based on serial and deserialized SerDes models is characterized by comprising the following steps: a parallel-to-serial method and a serial-to-parallel method;
communication system based on the above-mentioned SerDes model:
the parallel-serial method comprises the following steps: the serial unit read input terminal DPIT 0 Input end DPIT n-1 Input parallel transmission input data DT n-1 ~DT 0 The serial unit transmits input data DT in parallel through the transmission shift register n-1 ~DT 0 Converting the serial transmission output data DTX into serial transmission output data DTX, and sequentially transmitting the serial transmission output data DTX from a low bit to a high bit by the serial unit through the serial transmission output end DPOT under the control of a transmission clock time sequence;
the serial-to-parallel method comprises the following steps: under the control of the receiving clock time sequence, the deserializing unit reads the serial receiving input data DRX in sequence from low bit to high bit, and converts the serial receiving input data DRX into parallel receiving output data DR through the receiving shift register n-1 ~DR 0 The deserializing unit passes through the parallel output terminal DPOR 0 To output end DPOR n-1 Output parallel reception output data DR n-1 ~DR 0 ；
Where n is the data word length.
7. The method of communicating of the SerDes model of claim 6, further comprising:
the sending clock is output to a receiving clock by frequency division of a frequency divider N, wherein N is a positive integer.
8. The SerDes model communication method of claim 6, wherein the parallel-to-serial method further comprises:
the serial sheetThe element transmits the DTX of the serial transmission output data according to the bit DTX through the serial transmission output end DPOT 0 Bit DTX 1 Bit DTX 2 Bit DTX of changing into n-1 And sequentially sending.
9. The method of communicating in a SerDes model according to claim 6, wherein the serial-parallel method further comprises:
the deserializing unit DRX according to bit 0 Bit DRX 1 Bit DRX 2 A n-1 Sequentially reading the serial reception input data DRX.
10. The method of communicating of the SerDes model of claim 6, further comprising:
the deserializing unit serially receives the input data DRX by receiving sequential left shifts of the shift register.
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| US7010612B1 (en) * | 2000-06-22 | 2006-03-07 | Ubicom, Inc. | Universal serializer/deserializer |
| CN103592598A (en) * | 2013-10-31 | 2014-02-19 | 江苏绿扬电子仪器集团有限公司 | Sampling device for timing analysis of logic analyzer |
| CN106464267A (en) * | 2014-05-21 | 2017-02-22 | 高通股份有限公司 | Serializer and deserializer for odd ratio parallel data bus |
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Application publication date: 20230131 |