CN108736897B - Parallel-serial conversion circuit and device applied to high-speed interface physical layer chip - Google Patents
Parallel-serial conversion circuit and device applied to high-speed interface physical layer chip Download PDFInfo
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- CN108736897B CN108736897B CN201810385685.4A CN201810385685A CN108736897B CN 108736897 B CN108736897 B CN 108736897B CN 201810385685 A CN201810385685 A CN 201810385685A CN 108736897 B CN108736897 B CN 108736897B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention belongs to the technical field of high-speed parallel-serial conversion design, and provides a parallel-serial conversion circuit applied to a high-speed interface physical layer chip, which comprises: the phase-locked loop comprises a phase-locked loop, a parallel data sampling unit, a data selection and dispatch control unit, a first serial register, a second serial register and a differential serial data generation unit. According to the first clock and the second clock, the parallel data are sampled by the parallel data sampling unit to generate odd-numbered parallel data and even-numbered parallel data, the odd-numbered parallel data and the even-numbered parallel data are converted into odd-numbered serial data and even-numbered serial data by the data selection and distribution control unit, the odd-numbered parallel data and the even-numbered parallel data are processed by the differential serial data generating unit, and finally the output differential serial data are output. By using the design method of the pure digital circuit and the circuit structure design of the odd-even path, the internal use frequency of the chip is reduced, and the IP multiplexing of the parallel-serial conversion circuit of the high-speed interface physical layer under different processes can be better realized.
Description
Technical Field
The invention belongs to the technical field of high-speed parallel-serial conversion design, and particularly relates to a parallel-serial conversion circuit and a parallel-serial conversion device applied to a high-speed interface physical layer chip.
Background
At present, high-speed interfaces are more and more widely used, and physical layer interfaces of many protocols (such as PCIe, USB, SATA, SRIO, etc.) are all implemented by serial Deserializer (SerDes) technology. However, the physical layer implementation of the high-speed interface is a difficult problem in design in the industry because the digital-analog hybrid circuit design is required. The parallel-serial conversion circuit is used as an important link of SerDes circuit design and is used for sending serialized differential data. Its design advantages and disadvantages will directly affect the performance of the SerDes transmit port. The existing parallel-serial conversion circuit is mostly designed by analog circuit customization, the design of the analog circuit cannot be reused under the manufacturing process, so that a plurality of limitations are brought to the use of the circuit, the circuit is complex, delay difference is easy to occur in output differential signals, and the influence on the normal work of the whole SerDes circuit is large.
Disclosure of Invention
The invention aims to provide a parallel-serial conversion circuit and a parallel-serial conversion device applied to a high-speed interface physical layer chip, and aims to solve the problems that a circuit is complex, internal noise is easy to generate, and delay difference is easy to occur in output differential signals in the traditional technical scheme.
A parallel-serial conversion circuit applied to a high-speed interface physical layer chip comprises:
the phase-locked loop is used for generating a first clock and a second clock, wherein the first clock and the second clock have the same frequency and opposite phases;
the parallel data sampling unit is used for sampling the parallel data, generating and storing odd-numbered parallel data and even-numbered parallel data;
the data selection and distribution control unit is respectively connected with the parallel data sampling unit and used for converting the odd-numbered path parallel data and the even-numbered path parallel data into odd-numbered path serial data and even-numbered path serial data according to the first clock and the second clock;
the first serial register and the second serial register are connected with the data selection and distribution control unit and are respectively used for storing the odd-numbered serial data and the even-numbered serial data;
and the differential serial data generation unit is respectively connected with the first serial register and the second serial register and used for processing the odd-numbered serial data and the even-numbered serial data according to a first clock and a second clock and generating differential serial data.
In addition, a parallel-serial conversion device applied to a high-speed interface physical layer chip is also provided, which includes: the parallel-serial conversion circuit applied to the high-speed interface physical layer chip is disclosed.
The parallel-serial conversion circuit applied to the high-speed interface physical layer chip generates a first clock and a second clock through a phase-locked loop, samples parallel data through a parallel data sampling unit according to the first clock and the second clock to generate odd-numbered parallel data and even-numbered parallel data, converts the odd-numbered parallel data and the even-numbered parallel data into odd-numbered serial data and even-numbered serial data through a data selection and distribution control unit, and finally processes the odd-numbered serial data and the even-numbered serial data through a differential serial data generating unit to generate differential serial data, uses a pure digital circuit design, has simple circuits, realizes a high-speed parallel-serial conversion function, can be used for realizing different manufacturing processes, expands the use range of the circuits, and combines a phase clock to select and output the differential serial data generating unit, the problem of delay difference of differential serial data is effectively solved.
Drawings
Fig. 1 is a schematic structural diagram of a parallel-to-serial conversion circuit applied to a high-speed interface physical layer chip according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a parallel-to-serial conversion circuit applied to a high-speed interface physical layer chip according to another embodiment of the present invention;
FIG. 3 is a schematic diagram of an exemplary circuit of the parallel-to-serial conversion circuit applied to the physical layer chip with a high speed interface and including a parallel data sampling unit and a data selection and dispatch control unit shown in FIG. 1;
FIG. 4 is a schematic diagram of an exemplary circuit for the select signal generating circuit of FIG. 1 applied to a high speed physical layer chip;
fig. 5 is a schematic circuit diagram of an example of a differential serial data generating unit in the parallel-to-serial conversion circuit applied to the high-speed interface physical layer chip shown in fig. 1.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1 to 5, an embodiment of the present invention provides a parallel-to-serial conversion circuit applied to a high-speed interface physical layer chip, for converting parallel data into differential serial data, the parallel-to-serial conversion circuit including: the phase-locked loop 10, the parallel data sampling unit 20, the data selection and dispatch control unit 30, the first serial register 40, the second serial register 50, and the differential serial data generation unit 60.
It should be noted that, as shown in fig. 1, in the embodiment of the present invention, a phase-locked loop PLL is used to generate a first clock CLK _0 and a second clock CLK _180 that have a same frequency and a phase difference of 180 degrees: according to the serial baud rate requirement of the output, two identical frequencies are generated, the frequency is half of the serial baud rate, and the first clock CLK _0 and the second clock CLK _180 are opposite in phase. These two clocks are used for illustration, and in practice, CLK _0 and CLK _180 may be interchanged.
Referring to fig. 1, 2 and 3, the input parallel data is sampled by a parallel data sampling unit 20 to obtain and store odd-numbered parallel data and even-numbered parallel data, and the parallel data sampling unit 20 includes a first parallel register group 21 and a second parallel register group 22, which are respectively used for storing the odd-numbered parallel data and the even-numbered parallel data. In a specific embodiment, the frequency of the parallel data is 2CLK _0/N, the total bit width is N bits, and the parallel data is divided into odd-numbered parallel data and even-numbered parallel data by the parallel data sampling unit 20, and the odd-numbered parallel data and the even-numbered parallel data are respectively buffered in the first parallel register group 21 with N bits and the second parallel register group 22 with N bits, where the clock of the odd-numbered parallel data is CLK _0/N, and the clock of the even-numbered parallel data is-CLK _ 0/N. In a practical circuit, in particular, parallel data is stored in an initial parallel register set of N bits, the input clock to the trigger terminal of the initial parallel register set is 2CLK _0/N, the input terminal of the first parallel register set 21 is connected to the output terminal of the initial parallel register set, and the trigger input clock of the registers in the first set of parallel registers 21 is CLK _0/N, so that the odd-numbered parallel data with N bits clocked CLK _0/N is obtained at the first parallel register bank 21, and similarly, the input of the second parallel register bank 22 is connected to the output of the initial parallel register bank, and the trigger input clocks of the registers in the second parallel register bank 22 are CLK _0/N, thus, an even number of lanes of parallel data clocked by N bits of CLK _0/N are obtained at the second set of parallel registers 22.
Referring to fig. 1, 2 and 3, in order to convert the parallel data into the serial data, the odd-numbered lanes of parallel data and the even-numbered lanes of parallel data are first converted into the odd-numbered lanes of serial data and the even-numbered lanes of serial data according to the embodiment of the present invention, and the data selection and dispatch control unit 30 achieves this function. Specifically, the data selection and dispatch control unit 30 is respectively connected to the parallel data sampling unit 20, specifically to the first parallel register group 21 and the second parallel register group 22, and is configured to convert the odd-numbered parallel data and the even-numbered parallel data into the odd-numbered serial data and the even-numbered serial data; the data selection and dispatch control unit 30 includes a selection signal generation circuit 31, a first selector MUX1, and a first selector MUX 2; a first input end of the first selector MUX1 is connected to the first parallel register group 21, a second input end of the first selector MUX1 is connected to the second parallel register group 22, a selection signal end of the first selector MUX1 is connected to the selection signal generating circuit, and an output end of the first selector MUX1 is connected to the first serial register 40; a first input terminal of the first selector MUX2 is connected to the first parallel register group 21, a second input terminal of the first selector MUX2 is connected to the second parallel register group 22, a selection signal terminal of the first selector MUX2 is connected to the selection signal generating circuit, and an output terminal of the first selector MUX2 is connected to the second serial register 50.
Referring to fig. 2 and 3, the selection signal generating circuit 31 includes a shift register 311, a plurality of and gates 312 and or gates 313; the number of the and gates is the same as the number of the registers in the shift register 311, the first clock CLK _0 is input to the trigger terminal of the register in the shift register 311, the input terminal of the register in each stage of the shift register 311 is connected to the output terminal of one and gate 312, the first input terminal of each and gate 312 is input with the data enable signal, the second input terminal of each and gate 312 is connected to the output terminal of the last stage of the shift register, the first input terminal of the last and gate 312 is connected to the output terminal of the or gate 313, the first input terminal of the or gate 313 is input with the data enable signal, the second input terminal of the or gate 313 is input with the reset signal, the output terminal of the shift register is connected to the selection signal terminal of the first selector and the selection signal terminal of the second selector, the cyclic shift valid selection signal SEL with the second clock CLK _180 is output, and the odd-path enable control signal and the even-path enable control signal are respectively input, and respectively sending the parallel data of each path into an odd path serial register group and an even path serial register group according to the odd bit and even bit modes, thereby converting the odd path parallel data and the even path parallel data into odd path serial data and even path serial data.
Referring to fig. 1, 2 and 3, the first serial register 40 and the second serial register 50 are connected to the data selection and dispatch control unit 30, and are respectively used for temporarily storing a bit of odd-numbered serial data and a bit of even-numbered serial data; the input terminal of the first serial register 40 is connected to the output terminal of the first selector MUX1, temporarily stores one bit of odd serial data, the output terminal of the first serial register 40 is connected to the differential serial data generating unit 60, when the next odd-numbered serial data enters the first serial register 40, the one-odd-numbered serial data currently stored in the first serial register 40 is output to the differential serial data generating unit 60, similarly, the input terminal of the second serial register 50 is connected to the output terminal of the first selector MUX2, temporarily stores one-even-numbered serial data, the output terminal of the second serial register 50 is connected to the differential serial data generating unit 60, when the next even-bit lane serial data enters the second serial register 50, the one-bit even-bit lane serial data currently stored in the second serial register 50 is output to the differential serial data generation unit 60.
Referring to fig. 4 and 5, the differential serial data generating unit 60 is respectively connected to the first serial register 40 and the second serial register 50, and is configured to process the odd serial data and the even serial data and generate the differential serial data. The differential serial data generation unit 60 includes a third selector MUX3, a fourth selector MUX4, a first inverter N1, a second inverter N2, a first pre-register 61, a first post-register 62, a second pre-register 63, and a second post-register 64; the input end of the first pre-register 61 is connected with the first serial register 40, the output end of the first pre-register 61 is connected with the input end of the first post-register 62, the input end of the second pre-register 63 is connected with the second serial register 50, the output end of the second pre-register 63 is connected with the input end of the second post-register 64, the clock is input at the trigger end of the first pre-register 61, the first clock CLK _0 is input at the first post-register 62, and the second clock CLK _180 is input at the trigger end of the second pre-register 63 and the trigger end of the second post-register 64; a first input terminal of the third selector MUX3 is connected to the output terminal of the first post register 62, a second input terminal of the third selector MUX3 is connected to the output terminal of the second post register 64, a control terminal of the third selector MUX3 inputs the first clock CLK _0, an output terminal of the third selector MUX3 outputs the first serial differential data, a first input terminal of the fourth selector MUX4 is connected to the output terminal of the first post register 62 through the first inverter N1, a second input terminal of the fourth selector MUX4 is connected to the output terminal of the second post register 64 through the second inverter N2, a control terminal of the fourth selector MUX4 inputs the first clock CLK _0, and an output terminal of the fourth selector 38mux 58 outputs the second serial differential data; wherein the first serial differential data and the second serial differential data constitute serial differential data.
Processing odd-numbered paths of serial data: the input clock of the trigger terminal of the first preregister 61 is the second clock CLK _180, the input clock of the trigger terminal of the first postregister 62 is the first clock CLK _0, one group of data of the odd-numbered serial data passes through the two stages of registers and then enters the first input terminal of the third selector MUX3, and the other group of data of the odd-numbered serial data passes through the first inverter N1 and then enters the first input terminal of the fourth selector MUX 4.
Processing the even-path serial data: the input clocks of the trigger terminal of the second preregister 63 and the trigger terminal of the second postregister 64 are both the second clock CLK _180, one group of data after even-numbered data pass through the two stages of registers enters the second input terminal of the third selector MUX3, and the other group of data pass through the second inverter N2 and enter the second input terminal of the fourth selector MUX 4; the output of the output terminal of the third selector MUX3 is the final serial data TX, and the output of the output terminal of the fourth selector MUX4 is the final serial data NTX, which constitute serial differential data. The output of MUX0 is the final serial data TX and the output of MUX1 is the final serial data NTX. The phase complementary characteristics of the first clock CLK _0 and the second clock CLK _180 are skillfully applied, and the serial data of the odd-even path is effectively selected so as to realize alternate transmission and achieve the aim of high-frequency output. The first clock CLK _0 and the second clock CLK _180 are combined to carry out selection output, so that the problem of delay difference of differential signals is effectively solved.
As shown in fig. 5, the first clock CLK _0 and the second clock CLK _180 are generated by using the phase-locked loop 10, the first clock CLK _0 and the second clock CLK _180 have the same frequency and opposite phases, and the frequency of the first clock CLK _0 and the frequency of the second clock CLK _180 are half of the frequency of the serial differential data, specifically, the phase-locked loop 10 obtains the first clock CLK _0 and the second clock CLK _180 according to the output signal of the differential serial data generating unit 60, and the phase-locked loop 10 is used to generate two output clocks with the same frequency and a phase difference of 180 degrees: according to the output differential serial data, two identical frequencies are generated, the frequency is half of the frequency of the output differential serial data, the first clock CLK _0 and the second clock CLK _180 with opposite phases are generated, the circuit structure is simple, the implementation is easy, the used highest frequency is half of the frequency of the differential serial data, the frequency of the internal design of the differential serial data is effectively reduced, and therefore the internal noise of the whole chip is reduced.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (9)
1. A parallel-serial conversion circuit applied to a high-speed interface physical layer chip is characterized by comprising:
the phase-locked loop is used for generating a first clock and a second clock, wherein the first clock and the second clock have the same frequency and opposite phases;
the parallel data sampling unit is used for sampling the parallel data to generate odd-numbered parallel data and even-numbered parallel data;
the data selection and distribution control unit is respectively connected with the parallel data sampling unit and used for converting the odd-numbered path parallel data and the even-numbered path parallel data into odd-numbered path serial data and even-numbered path serial data according to the first clock and the second clock;
the first serial register and the second serial register are connected with the data selection and distribution control unit and are respectively used for storing the odd-numbered serial data and the even-numbered serial data;
the differential serial data generation unit is respectively connected with the first serial register and the second serial register and used for processing the odd-numbered serial data and the even-numbered serial data according to a first clock and a second clock and generating differential serial data;
the parallel data sampling unit comprises a first parallel register group and a second parallel register group, and the first parallel register group and the second parallel register group are connected with the parallel data sampling unit and are respectively used for storing the odd-numbered path parallel data and the even-numbered path parallel data.
2. The parallel-to-serial conversion circuit applied to a high-speed interface physical layer chip of claim 1, wherein the trigger input clock of the register in the first parallel register set is half of the parallel data, and the trigger input clock of the register in the second parallel register set is inverted from the trigger input clock of the register in the first parallel register set.
3. The parallel-to-serial conversion circuit applied to a high speed interface physical layer chip according to claim 1, wherein the data selection and dispatch control unit includes a selection signal generation circuit, a first selector and a second selector;
a first input end of the first selector is connected with the first parallel register group, a second input end of the first selector is connected with the second parallel register group, a selection signal end of the first selector is connected with the selection signal generating circuit, and an output end of the first selector is connected with the first serial register;
the first input end of the second selector is connected with the first parallel register group, the second input end of the second selector is connected with the second parallel register group, the selection signal end of the second selector is connected with the selection signal generating circuit, and the output end of the second selector is connected with the second serial register.
4. The parallel-to-serial conversion circuit applied to a high-speed interface physical layer chip of claim 3, wherein the selection signal generating circuit comprises a shift register, a plurality of AND gates and OR gates;
the number of the AND gates is the same as that of the registers in the shift register, a first clock is input to a trigger end of the registers in the shift register, an input end of each stage of the registers in the shift register is connected with an output end of one AND gate, a first input end of each AND gate inputs a data enable signal, a second input end of each AND gate is connected with an output end of a previous stage of the registers in the shift register, a first input end of the last AND gate is connected with an output end of the OR gate, a first input end of the OR gate inputs a data enable signal, a second input end of the OR gate inputs a reset signal, and an output end of the registers in the shift register is connected with a selection signal end of the first selector and a selection signal end of the second selector.
5. The parallel-to-serial conversion circuit applied to a high speed interface physical layer chip according to claim 1, wherein the differential serial data generating unit includes a third selector, a fourth selector, a first inverter, a second inverter, a first pre-register, a first post-register, a second pre-register, and a second post-register;
the input end of the first pre-register is connected with the first serial register, the output end of the first pre-register is connected with the input end of the first post-register, the input end of the second pre-register is connected with the second serial register, the output end of the second pre-register is connected with the input end of the second post-register, the clock is input into the trigger end of the first pre-register, the first clock is input into the first post-register, and the second clock is input into the trigger end of the second pre-register and the trigger end of the second post-register;
a first input end of the third selector is connected with an output end of the first post register, a second input end of the third selector is connected with an output end of the second post register, a control end of the third selector inputs the first clock, an output end of the third selector outputs first serial differential data, a first input end of the fourth selector is connected with an output end of the first post register through a first inverter, a second input end of the fourth selector is connected with an output end of the second post register through a second inverter, a control end of the fourth selector inputs the first clock, and an output end of the fourth selector outputs second serial differential data;
wherein the first serial differential data and the second serial differential data constitute the serial differential data.
6. The parallel-to-serial conversion circuit as claimed in claim 1, wherein an input terminal of the first serial register is connected to an output terminal of the first selector for temporarily storing one odd serial data, an output terminal of the first serial register is connected to the differential serial data generating unit, an input terminal of the second serial register is connected to an output terminal of the second selector for temporarily storing one even serial data, and an output terminal of the second serial register is connected to the differential serial data generating unit.
7. The parallel-to-serial conversion circuit applied to a high speed interface physical layer chip according to claim 1, wherein the number of the first parallel register sets is the same as the number of the second parallel register sets.
8. The parallel-to-serial conversion circuit applied to a high speed interface physical layer chip of claim 1, wherein the frequency of the first clock and the frequency of the second clock are both half of the frequency of the differential serial data.
9. A parallel-serial conversion device applied to a high-speed interface physical layer chip is characterized by comprising: the parallel-to-serial conversion circuit of any one of claims 1 to 8.
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| TWI747128B (en) * | 2019-01-31 | 2021-11-21 | 日商村田製作所股份有限公司 | Digital output monitor circuit and high frequency front-end circuit |
| CN110061738B (en) * | 2019-04-26 | 2023-05-23 | 海光信息技术股份有限公司 | All-digital phase-locked loop circuit |
| CN111157881B (en) * | 2020-01-03 | 2022-05-31 | 深圳市紫光同创电子有限公司 | Test circuit and circuit test method |
| CN111290987B (en) * | 2020-03-04 | 2021-04-02 | 武汉精立电子技术有限公司 | Device and method for realizing ultra-high-speed SPI (Serial peripheral interface) |
| CN111865330B (en) * | 2020-08-05 | 2023-08-08 | 中国电子科技集团公司第二十四研究所 | High-speed parallel-serial conversion circuit suitable for JESD204B protocol standard |
| CN115982078A (en) * | 2023-01-19 | 2023-04-18 | 北京超弦存储器研究院 | CXL memory module and memory storage system |
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| CN106464267A (en) * | 2014-05-21 | 2017-02-22 | 高通股份有限公司 | Serializer and deserializer for odd ratio parallel data bus |
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| JP2007036869A (en) * | 2005-07-28 | 2007-02-08 | Nec Electronics Corp | Serial/parallel conversion, parallel/serial conversion, and fifo integrated circuit |
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| CN1610891A (en) * | 2001-11-21 | 2005-04-27 | 美商内数位科技公司 | Base station having a hybrid parallel/serial bus interface |
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| CN106464267A (en) * | 2014-05-21 | 2017-02-22 | 高通股份有限公司 | Serializer and deserializer for odd ratio parallel data bus |
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