CN115641905A

CN115641905A - Power failure testing device and method for data storage chip

Info

Publication number: CN115641905A
Application number: CN202211629170.7A
Authority: CN
Inventors: 陈剑锋
Original assignee: Hefei Kangxinwei Storage Technology Co Ltd
Current assignee: Hefei Kangxinwei Storage Technology Co Ltd
Priority date: 2022-12-19
Filing date: 2022-12-19
Publication date: 2023-01-24
Anticipated expiration: 2042-12-19
Also published as: CN115641905B

Abstract

The invention discloses a power failure testing device and a power failure testing method for a data storage chip, and belongs to the technical field of electronic circuits. The power failure testing device comprises: a host computer in which test software is stored; the protocol conversion device is electrically connected to the host and is used for converting the first type signals output by the host into second type signals received by the data storage chip; and the detection device is electrically connected with the protocol conversion device and comprises an installation module and a detection module, the data storage chip is installed on the detection device through the installation module, and the detection module detects the input and output signals of the data storage chip. The power failure testing device and the testing method of the data storage chip can improve the efficiency of power failure testing.

Description

Power failure testing device and method for data storage chip

Technical Field

The invention belongs to the technical field of electronic circuits, and particularly relates to a power failure testing device and a power failure testing method for a data storage chip.

Background

A firmware mapping table is stored in the data storage chip to maintain the conversion between the logical address and the physical address, and after the data storage chip is prepared, the power failure test needs to be carried out on the data storage chip. The method is used for observing faults of the data storage chip when the firmware mapping table is read, written and deleted. However, in the process of performing the power-down test on the data storage chip, when the data storage chip fails, a tester cannot acquire the reason of the failure, so that the debugging difficulty of the tester is increased, and the test efficiency is low. And the power-on and power-off of the data storage chip cannot be flexibly realized.

Disclosure of Invention

The invention aims to provide a power failure testing device and a testing method of a data storage chip, which solve the problems that the failure reason of the data storage chip cannot be obtained and the power-on and power-off of the data storage chip cannot be flexibly realized.

In order to solve the technical problems, the invention is realized by the following technical scheme:

the invention provides a power failure testing device of a data storage chip, which at least comprises:

a host computer in which test software is stored;

the protocol conversion device is electrically connected to the host and is used for converting the first type signal output by the host into a second type signal received by the data storage chip; and

the detection device is electrically connected with the protocol conversion device and comprises an installation module and a detection module, the data storage chip is installed on the detection device through the installation module, and the detection module detects input and output signals of the data storage chip.

In an embodiment of the present invention, the protocol conversion apparatus includes a protocol conversion chip, and the protocol conversion chip converts the first type signal into the second type signal.

In an embodiment of the present invention, the protocol conversion apparatus includes a voltage conversion module, and the voltage conversion module includes a voltage conversion circuit and a backflow prevention circuit.

In an embodiment of the present invention, the backflow prevention circuit includes:

the base electrode of the first transistor is electrically connected to the protocol conversion chip, the collector electrode of the first transistor is electrically connected to the voltage output end of the voltage conversion circuit, and the emitter electrode of the first transistor is electrically connected to the grounding end.

and the source electrode of the second transistor is electrically connected to the voltage output end of the voltage conversion circuit, and the grid electrode of the second transistor is electrically connected to the collector electrode of the first transistor.

and the drain electrode of the third transistor is electrically connected to the drain electrode of the second transistor, the grid electrode of the third transistor is electrically connected to the collector electrode of the first transistor, and the source electrode of the third transistor is the output end of the backflow prevention circuit.

In an embodiment of the present invention, the power-down testing apparatus further includes a switch module, where the switch module includes one end electrically connected to the host through the first type interface, and another end electrically connected to the protocol conversion chip.

In an embodiment of the present invention, the power down apparatus further includes a number module, where the number module includes six-bit dial switches, and one end of each of the six-bit dial switches is electrically connected to the protocol conversion chip, and the other end of each of the six-bit dial switches is electrically connected to a ground terminal through a resistor.

In an embodiment of the present invention, the power down apparatus further includes a reset module, where the reset module includes:

one end of the pull-up resistor is electrically connected to a power end, and the other end of the pull-up resistor is electrically connected to the protocol conversion chip through a resistor; and

and one end of the capacitor is electrically connected with the protocol conversion chip through the resistor, and the other end of the capacitor is electrically connected with the grounding end.

The invention also provides a power failure test method of the data storage chip, which uses the power failure test device of the data storage chip and comprises the following steps:

installing the data storage chip to be tested on the detection device, and starting the test software on the host;

setting expected parameters during power failure test, and starting the test;

sending test information to the data storage chip through the test software, receiving information fed back by the data storage chip, and judging whether complete communication is established or not; and

and after the complete communication is established, starting the test, repeating the power failure behavior in the test process, and testing the feedback information of the data storage chip until the power failure times reach the preset times.

According to the power-down test device and the test method of the data storage chip, provided by the invention, the workload and the test cost of a tester are reduced to a great extent, and when a problem occurs in the test, the power-down test device can print the internal abnormality of the data storage chip to be tested on the test software and form a record, so that the failure types can be classified conveniently, the failure reason is the problem of the test environment or the data storage chip to be tested, and the analysis efficiency is improved.

Of course, it is not necessary for any product to practice the invention to achieve all of the above-described advantages at the same time.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a power down testing apparatus of a data storage chip in the present application.

Fig. 2 is a schematic circuit diagram of a first type of interface module according to the present application.

Fig. 3 is a schematic circuit diagram of a second type of interface module in the present application.

Fig. 4 is a circuit schematic of a pull-up circuit for a second type of interface in the present application.

Fig. 5 is a circuit schematic of a pull-up circuit for a second type of interface in the present application.

Fig. 6 is a schematic circuit diagram of a backflow prevention circuit according to the present application.

Fig. 7 is a schematic circuit diagram of a protocol conversion chip according to the present application.

Fig. 8 is a circuit schematic of a filter circuit around a conversion circuit as described in the present application.

Fig. 9 is a schematic circuit diagram of a switch module according to the present application.

Fig. 10 is a schematic circuit diagram of the crystal oscillator module of the present application.

Fig. 11 is a schematic circuit diagram of a display module according to the present application.

FIG. 12 is a schematic circuit diagram of a memory module according to the present application.

FIG. 13 is a circuit diagram of a portion of the pins of the ROM of FIG. 12.

FIG. 14 is a circuit diagram of a portion of the ROM pins of FIG. 12.

FIG. 15 is a circuit schematic of the numbering block of the present application.

Fig. 16 is a schematic circuit diagram of a reset module according to the present application.

Fig. 17 is a schematic circuit diagram of the detection device of the present application.

Fig. 18 is a flowchart of a power down testing method for a data storage chip in the present application.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, the present application provides a power down testing apparatus for a data storage chip, which includes a host 10 and a power down apparatus 20. Wherein, the data storage chip is installed on the power down device 20 to perform power down processing on the data storage chip. And the reason of the data storage chip when power is down can be detected by the power down device 20.

As shown in fig. 1, in an embodiment of the present invention, the host 10 may be, for example, a personal computer, a CPU core, or a server connected to a network, and the data storage Chip is, for example, a commonly used data storage device such as an Embedded multimedia memory Card (eMMC), an Embedded Multi-Chip Package (eMCP), and the like. The data storage chip comprises a storage unit and a control unit, wherein the storage unit is a flash memory array for example, and the control unit is a flash memory array controller for example. The host 10 can perform data access control on the data storage chip, for example, by sending a write request, a read request, a delete request, etc. to the data storage chip, the data storage chip will feed back relevant information to the host 10 after completing relevant commands.

Referring to fig. 1, in an embodiment of the invention, the output interface of the host 10 is, for example, a Universal Serial Bus (USB) interface or a Type-C interface, and the input interface of the data storage chip is determined according to the Type of the data storage chip, for example, the embedded multimedia memory card has an eMMC interface, and the embedded multi-chip package has an eMCP interface.

Referring to fig. 1, in an embodiment of the present invention, a host 10 is provided with a test software, which can integrate software and hardware, and perform a plurality of power-down behaviors and long-time inspection on a data storage chip by simulating the formation and duplication of operations on the data storage chip by various terminal platforms. The test software runs on the host computer 10 and is connected with the data storage chip on the power down device 20 through the output interface of the host computer 10 to test the data storage chip.

Referring to fig. 1, in an embodiment of the present invention, the power down device 20 includes a protocol conversion device 201 and a detection device 202. One end of the protocol conversion device 201 is electrically connected to the host 10, the other end is electrically connected to the detection device 202, and the data storage chip is mounted on the detection device 202. The protocol conversion device 201 can convert the first type signal output by the host 10 into the second type signal input by the data storage chip, and adjust the input electrical signal input to the data storage chip, the bus width of the data storage chip, the clock frequency, and the like according to the test requirement.

Referring to fig. 1, in the present application, the protocol conversion apparatus 201 and the detection apparatus 202 are respectively integrated on a Printed Circuit Board (PCB). In other embodiments, the protocol conversion device 201 and the detection device 202 may be integrated on a printed circuit board at the same time. The protocol conversion device 201 is provided with a plurality of functional modules, including an interface module, a voltage conversion module 2014, a protocol conversion module 2015, a switch module 2013, a crystal oscillator module 2016, a display module 2017, a storage module 2018 and a numbering module 2019.

Referring to fig. 1 to 4, in an embodiment of the invention, the host 10 is connected to a first type interface 2011, and the detection device 202 is connected to a second type interface 2012. Correspondingly, the interface modules include a first type interface module and a second type interface module. The first type interface module includes a first type interface 2011 and a connection circuit disposed around the first type interface 2011. The second type interface module includes a second type interface 2012 and connection circuitry disposed around the second type interface 2012.

Specifically, as shown in fig. 1 and fig. 2, the first type interface 2011 is, for example, a USB interface, and the first type interface 2011 is provided with ground terminals G1, G2, and GND, a power terminal VBUS, and data terminals D-, D +, SSRX-, and SSRX +. The ground terminals G1, G2 and GND are electrically connected to the ground terminal. The power supply terminal VBUS is electrically connected to the output voltage source VBUS, and a magnetic bead LB1 is connected in series between the power supply terminal VBUS and the output voltage source VBUS. And one side close to the output voltage source VBUS is also provided with filter capacitors C3 and C4, one ends of the filter capacitors C3 and C4 are electrically connected to the output voltage source VBUS, and the other ends are electrically connected to the grounding end. The data terminals D-, D +, SSRX-and SSRX + are electrically connected to the protocol conversion chip, and can realize full-duplex communication and bidirectional data transmission.

Referring to fig. 1 and 3, the second type interface 2012 is, for example, an eMMC interface, and the second type interface 2012 is provided with a plurality of ground terminals, power terminals, and data terminals. The ground terminal is electrically connected to the ground terminal, the power terminal is electrically connected to the output terminal of the voltage conversion module 2014 through the fuses F1 and F2, and the data terminal is electrically connected to the protocol conversion chip in the protocol conversion module 2015. The data terminal of the second type interface 2012 is the same as the data terminal of the data conversion chip, and has more data terminals and ground terminals, as shown in fig. 3. As shown in fig. 4, each data terminal is also connected to a voltage source through a resistor pull-up to ensure data stability.

Referring to fig. 1, fig. 5 and fig. 6, in an embodiment of the invention, the voltage conversion module 2014 includes a voltage conversion circuit and a backflow prevention circuit. As shown in fig. 5, the voltage conversion circuit includes two DC-DC voltage reduction circuits and performs voltage conversion using a voltage conversion chip, and is, for example, a TLV62569 voltage conversion chip. One of the voltage conversion circuits converts a voltage input from the first type interface 2011 into a first voltage, and the other voltage conversion circuit converts a voltage input from the first type interface 2011 into a second voltage. The first voltage is 3.3V, for example, and supplies power to peripheral circuits of the protocol conversion chip. The second voltage is 1.8V for example, and supplies power to the core circuit of the protocol conversion chip. The input end VIN of the voltage conversion chip is electrically connected to the output voltage source VBUS in the first type interface module, and is connected to the ground terminal through the capacitor C27/C31. The enable terminal EN of the voltage conversion chip is electrically connected to the protocol conversion chip, so that the protocol conversion chip can control the output of the voltage conversion module 2014. The enable terminal EN of the voltage conversion chip is electrically connected to the output voltage source in the first type interface module through two voltage dividing resistors, two ends of one voltage dividing resistor R44/R53 are electrically connected to the output voltage source VBUS in the first type interface module and the enable terminal EN of the voltage conversion chip, and two ends of the other voltage dividing resistor R49/R56 are electrically connected to the enable terminal EN and the ground terminal of the voltage conversion chip. The input voltage and the input current of the enable end can be adjusted according to the sizes of the two divider resistors. The output end SW of the voltage conversion chip outputs the first voltage or the second voltage, and the output end SW of the voltage conversion chip is also electrically connected with an inductor L2, so that the voltage output can be stabilized. The feedback terminal FB of the voltage conversion chip is electrically connected to the output terminal of the first voltage or the second voltage through two feedback resistors, two ends of one feedback resistor R47/R55 are electrically connected to the feedback terminal FB and the output terminal of the first voltage or the second voltage, and two ends of the other feedback resistor R50/R57 are electrically connected to the feedback terminal FB and the ground terminal. Capacitors are electrically connected between the feedback terminal FB and the output terminal of the first voltage or the second voltage, and between the ground terminal FB and the output terminal of the first voltage or the second voltage.

Referring to fig. 1 and 6, the anti-backflow circuit includes three transistors, wherein the first transistor Q3/Q6 is an NPN small-signal transistor, and the second transistor Q1/Q4 and the third transistor Q2/Q5 are P-type mosfet transistors. The base of the first transistor Q3/Q6 and the enable terminal EN of the voltage conversion chip are electrically connected to the same pin of the protocol conversion chip, the collector of the first transistor Q3/Q6 is electrically connected to the voltage output terminal of the voltage conversion circuit through a resistor R45/R54, and the emitter of the first transistor Q3/Q6 is electrically connected to the ground terminal. The source of the second transistor Q1/Q4 is electrically connected to the voltage output terminal of the voltage conversion circuit, the gate of the second transistor Q1/Q4 is electrically connected to the collector of the first transistor Q3/Q6, and the drain of the second transistor Q1/Q4 is electrically connected to the drain of the third transistor Q2/Q5. The gate of the third transistor Q2/Q5 is electrically connected to the collector of the first transistor Q3/Q6, and the source of the third transistor Q2/Q5 is the output terminal of the anti-backflow circuit, i.e., the final voltage output terminal of the voltage conversion module 2014. The source of the third transistor Q2/Q5 is also electrically connected to a capacitor C28/C32 to stabilize the output voltage.

Referring to fig. 1, fig. 7 and fig. 8, in an embodiment of the invention, the protocol conversion module 2015 includes a protocol conversion chip and a filter circuit disposed around the protocol conversion circuit. The protocol conversion chip is, for example, a GL3227K chip, and can convert a USB signal output by the host 10 into an eMMC signal used by the data storage chip. And a plurality of filter circuits are arranged at one side or a plurality of sides of the protocol conversion chip, and each filter circuit is arranged close to the corresponding voltage input pin on the protocol conversion chip. The filter circuit may include a plurality of filter capacitors, one end of each filter capacitor is electrically connected to the ground terminal, and the other end of each filter capacitor is electrically connected to the power input terminal of the protocol conversion chip. The filter circuit may further include a plurality of magnetic beads, one end of each magnetic bead is electrically connected to the power input end of the protocol conversion chip, and the other end of each magnetic bead is electrically connected to the output end of the voltage conversion module 2014. The voltage required by the protocol conversion chip is small, for example, 3.3V, 1.8V or less, and when the wiring is performed on the circuit board, the voltage output by the voltage conversion module 2014 reaches the protocol conversion chip, the voltage may have burrs, and the use of the filter circuit can ensure that the voltage input to the protocol conversion chip is a stable high-quality voltage. In this embodiment, the specifications of the filter capacitor and the magnetic bead may be specifically set according to the voltage size and the routing condition, and the filter capacitor of 4.7uF, 2.2uF or 0.1uF, for example, and 1kohm @100mhz, for example, may be selected.

Referring to fig. 1 and 9, in an embodiment of the invention, the switch module 2013 is disposed between the first type interface 2011 and the protocol conversion module 2015. The switch module 2013 includes a switch, and is, for example, a single pole double throw switch SW2. One end of the single-pole double-throw switch SW2 is electrically connected to the output voltage source VBUS connected to the voltage terminal of the first type interface 2011, and the other end is electrically connected to the protocol conversion chip. By setting a program, the on-off of the single-pole double-throw switch SW2 can be controlled by the protocol conversion chip.

Referring to fig. 1 and 10, in an embodiment of the invention, the crystal module 2016 includes a crystal oscillator X1. Two ends of the crystal oscillator X1 are electrically connected to the protocol conversion chip. Two ends of the crystal oscillator X1 are respectively provided with a matching capacitor C1 and a matching capacitor C2 which are grounded, and a resistor R1 which is bridged at two ends of the crystal oscillator. The resistor R1 connected across cooperates with the matching capacitors C1 and C2 connected to ground to adjust the frequency of the crystal oscillator X1.

Referring to fig. 1 and 11, in an embodiment of the invention, the display module 2017 includes a plurality of light emitting diodes LED1, LED2, LED3, and LED4, cathodes of the light emitting diodes LED1, LED2, LED3, and LED4 are electrically connected to a ground terminal, and anodes thereof are electrically connected to the protocol conversion chip through resistors R43, R46, R48, and R52. When the power failure test is performed on the data storage chip, if the test is abnormal or the test is passed, the state of the data storage chip can be displayed through the light emitting diodes LED1, LED2, LED3 and LED4 in the display module 2017. In the present application, the light emitting diodes LED1, LED2, LED3 and LED4 have different colors to represent a plurality of test states.

Referring to fig. 1, 12, 13 and 14, in an embodiment of the invention, the storage module 2018 includes a Read-Only Memory (ROM) U2. The data transmission terminals SO and SI of the rom U2 are electrically connected to the protocol conversion chip for data transmission. The storage module 2018 stores firmware codes, and when the protocol conversion module 2015 receives data sent by the host 10 or the data storage chip, the protocol conversion module 2015 calls the firmware codes in the storage device to process the data and transmit the processed data out. Other terminals of the rom are directly electrically connected to the ground terminal or the power terminal according to the requirement.

Referring to fig. 1 and 15, in an embodiment of the invention, the number module 2019 includes a six-bit toggle switch SW1, one end of each of which is electrically connected to the protocol conversion chip, and the other end of each of which is electrically connected to the ground terminal through a resistor. When power failure verification is performed, a plurality of power failure test devices can be connected in parallel under one host 10, and each power failure test device is connected with at least one data storage chip. When the data storage chip connected with one or more of the power-down test devices needs to be operated, the power-down test device can be identified through the sequence number of the numbering module 2019, and an execution command is sent to one or more of the power-down test devices independently.

Referring to fig. 16, in an embodiment of the present invention, a reset module is further disposed. The reset module comprises a pull-up resistor R7 and a capacitor C6, wherein one end of the pull-up resistor R7 is electrically connected with a power supply end, and the other end of the pull-up resistor R7 is electrically connected with the protocol conversion chip through a resistor R13. One end of the capacitor C6 is electrically connected to the protocol conversion chip through the resistor R13, and the other end is electrically connected to the ground.

Referring to fig. 1 and 17, in an embodiment of the invention, the detecting device 202 may be integrated on a Printed Circuit Board (PCB). The detecting device 202 includes an installing module 2023, a connecting module 2021, and a detecting module 2022. A socket board is provided on the printed circuit board as a mounting module 2023. When the power-off detection is required to be carried out on the data storage chip, the data storage chip is installed on the socket board. The connection module 2021 includes a connection interface, which is the same as the second type interface 2012, and the pins of the connection interface are disposed corresponding to the pins of the data storage chip. As shown in fig. 1, in the present application, a detection module 2022 is disposed between the connection interface and the data storage chip, and the detection module 2022 includes a plurality of jumpers. During the detection, the data change of each pin of the data storage chip can be detected.

Referring to fig. 1 and 18, when the power down test apparatus provided by the present application is used for testing, the power down test method includes steps S101 to S105.

S101, installing a data storage chip to be tested on the power failure device, and starting test software on the host.

S102, setting expected parameters during power failure test, and starting the test.

S103, sending test information to the data storage chip to be tested through the test software, receiving information fed back by the data storage chip, and judging whether complete communication is established.

And S104, after the complete communication is established, starting the test, repeating the power failure behavior in the test process, and testing the feedback information of the data storage chip until the power failure times reach the preset times.

In the application, in the test process, the data storage chip needs to upload the feedback information to the test software interface in real time. So as to observe the action of the data storage chip in the power-down process.

In summary, the present invention provides a power down testing apparatus for a data storage chip, which includes a host and a power down apparatus, wherein the host is installed with testing software, and the power down apparatus includes a protocol conversion apparatus and a detection apparatus. One end of the protocol conversion device is electrically connected to the host, the other end of the protocol conversion device is electrically connected to the detection device, and the data storage chip is installed on the detection device. The protocol conversion device can convert a first type signal output by the host computer into a second type signal input by the data storage chip, and adjust an input electric signal input into the data storage chip, the bus width of the data storage chip, the clock frequency and the like according to test requirements. The data of each pin of the data storage chip can be detected by the detection device.

The embodiments of the invention disclosed above are intended to be merely illustrative. The examples are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand the invention for and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A power failure testing device of a data storage chip is characterized by at least comprising:

a host computer, in which test software is stored;

2. The device for testing power down of a data storage chip of claim 1, wherein the protocol conversion device comprises a protocol conversion chip, and the protocol conversion chip converts the first type signal into the second type signal.

3. The device of claim 2, wherein the protocol conversion unit comprises a voltage conversion module, and the voltage conversion module comprises a voltage conversion circuit and a backflow prevention circuit.

4. The device for testing power failure of a data storage chip of claim 3, wherein the back-flow prevention circuit comprises:

5. The device for testing power failure of a data storage chip of claim 4, wherein the back-flow prevention circuit comprises:

6. The device for testing power failure of a data storage chip of claim 5, wherein the back-flow prevention circuit comprises:

and the drain electrode of the third transistor is electrically connected with the drain electrode of the second transistor, the grid electrode of the third transistor is electrically connected with the collector electrode of the first transistor, and the source electrode of the third transistor is the output end of the backflow prevention circuit.

7. The device for testing power failure of a data storage chip of claim 2, further comprising a switch module, wherein the switch module comprises one end electrically connected to the host through the first type interface, and the other end electrically connected to the protocol conversion chip.

8. The device for testing power failure of a data storage chip of claim 2, further comprising a number module, wherein the number module comprises six-bit dial switches, one end of each of the six-bit dial switches is electrically connected to the protocol conversion chip, and the other end of each of the six-bit dial switches is electrically connected to a ground terminal through a resistor.

9. The power down test device of a data storage chip of claim 2, further comprising a reset module, the reset module comprising:

10. A power-down test method of a data storage chip, characterized in that the power-down test apparatus of a data storage chip according to claim 1 is used, and the power-down test method comprises:

installing the data storage chip to be tested on the detection device, and starting test software on the host;

setting expected parameters during power failure test, and starting the test;