CN219737587U

CN219737587U - Chip test board and equipment thereof

Info

Publication number: CN219737587U
Application number: CN202321088755.2U
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Shanghai Mindmotion Microelectronics Co ltd
Current assignee: Shanghai Mindmotion Microelectronics Co ltd
Priority date: 2023-05-08
Filing date: 2023-05-08
Publication date: 2023-09-22
Anticipated expiration: 2033-05-08

Abstract

The utility model relates to the field of semiconductors, and discloses a chip test board and equipment thereof, which can test various chips by using one set of chip test board without an upper computer. The chip test board comprises an FPGA, a high-speed connector, n sub-boards and a storage module. The first end of the FPGA is coupled to the first end of the high-speed connector and the second end of the FPGA is coupled to the memory module. The second end of the high-speed connector is coupled to the first end of the daughter board. The second end of the daughter board is coupled to the chip under test.

Description

Chip test board and equipment thereof

Technical Field

The utility model relates to the field of semiconductors, in particular to a chip test board and equipment thereof.

Background

In the chip testing process, a detection manufacturer tests the semi-finished product of the chip in production through a professional instrument, so that the link of yield is improved. Each chip that enters the market must be tested to be eventually marketed. Different kinds of chips, test flows and required test templates are different, so that a lot of time and labor are often consumed for chip testing.

The prior art has the following disadvantages: 1. two devices, namely an upper computer and an FPGA test board, are needed, wherein the two devices comprise a connecting wire, and the upper computer is used as a main control; 2. except that the I/O test is automatic, the peripheral functions still need to be manually connected with the DuPont wire; 3. the different package size type chips require re-development of the FPGA test board.

Disclosure of Invention

The utility model aims to provide a chip test board and a device thereof, which can test various chips by using one set of chip test board without an upper computer.

The utility model discloses a chip test board, comprising: an FPGA (1), a high-speed connector (2) and n daughter boards (3);

the FPGA (1) is coupled to a first end of the high-speed connector (2);

a second end of the high-speed connector (2) is coupled to a first end of the daughter board (3);

the second end of the daughter board (3) is coupled to the chip (4) to be tested;

the daughter board (3) is a connecting board matched with the chips (4) to be tested of different types;

and output pins of the FPGA (1) are connected with input pins of the chip (4) to be tested in a one-to-one correspondence manner.

In a preferred embodiment, the device further comprises a debug interface (5), a first end of the debug interface (5) being coupled to the FPGA (1), and a second end of the debug interface (5) being coupled to the device.

In a preferred embodiment, a communication interface (6) is further comprised, a first end of the communication interface (6) being coupled to the FPGA (1), a second end of the communication interface (6) being coupled to the device.

In a preferred embodiment, a download interface (7) is further included, a first end of the download interface (7) being coupled to the FPGA (1), and a second end of the download interface (7) being coupled to the device.

In a preferred embodiment, a display interface (8) is also included, the display interface (8) being configured to couple a display to the FPGA (1).

In a preferred embodiment, a key control module (9) is further included, the key control module (9) being coupled to the FPGA (1).

In a preferred embodiment, a peripheral unit (10) is further included, a first end of the peripheral unit (10) being coupled to the FPGA (1), and a second end of the peripheral unit (10) being coupled to the high-speed connector (2).

In a preferred embodiment, the chip test board further comprises a power supply (11), and the power supply (11) is mounted on the chip test board and supplies power to the chip test board.

In a preferred embodiment, a memory module (12) is also included, the memory module (12) being coupled to the FPGA (1).

The utility model also discloses a chip testing device comprising the chip testing board as described above.

In the embodiment of the utility model, the interface connection of one high-speed connector can be matched with the connecting plates of a plurality of different types of chips to be tested, so that the chips to be tested with multiple sizes or packaging types can be tested by only one test plate.

The numerous technical features described in the description of the present utility model are distributed among the various technical solutions, which can make the description too lengthy if all possible combinations of technical features of the present utility model (i.e., technical solutions) are to be listed. In order to avoid this problem, the technical features disclosed in the above summary of the utility model, the technical features disclosed in the following embodiments and examples, and the technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (these technical solutions are regarded as already described in the present specification) unless such a combination of technical features is technically impossible. For example, in one example, feature a+b+c is disclosed, in another example, feature a+b+d+e is disclosed, and features C and D are equivalent technical means that perform the same function, technically only by alternative use, and may not be adopted simultaneously, feature E may be technically combined with feature C, and then the solution of a+b+c+d should not be considered as already described because of technical impossibility, and the solution of a+b+c+e should be considered as already described.

Drawings

FIG. 1 is a schematic diagram of a structure according to one embodiment of the utility model;

fig. 2 is a schematic diagram of a connection according to one embodiment of the utility model.

Reference numerals illustrate:

1-FPGA; 2-high speed connectors; 3-daughter boards; 4-a memory module; 5-a chip to be tested; 6-a debugging interface; 7-a communication interface; 8-downloading interface; 9-a display interface; 10-a key control module; 11-a peripheral unit; 12-power supply; t-chip test board.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present utility model. However, it will be understood by those skilled in the art that the claimed utility model may be practiced without these specific details and with various changes and modifications from the embodiments that follow.

Specific implementations of the utility model are described in detail below with reference to specific embodiments and the accompanying drawings:

a first embodiment of the present utility model relates to a chip test board, as shown in fig. 1, comprising: FPGA (1), high-speed connector (2) and n daughter boards (3) (3_1, 3_2, … … 3 _n). The FPGA (1) is coupled to a first end of the high-speed connector (2). The second end of the high-speed connector (2) is coupled to the first end of the daughter board (3). The second end of the daughter board (3) is coupled to the chip under test (4). The daughter board (3) is a connecting board matched with chips (4) to be tested of different types. The output pins of the FPGA (1) are connected with the input pins of the chip (4) to be tested in a one-to-one correspondence.

As shown in fig. 2, inputs s1 to sn of the FPGA (1) are all connected to a plurality of output pins AF1, AF2 and AF3, AF1 is connected to input pin PA1 of the chip under test (4), AF2 is connected to input pin PA2 of the chip under test (4), and AF3 is connected to input pin PA3 of the chip under test (4).

Optionally, a debug interface (5) may be included, a first end of the debug interface (5) being coupled to the FPGA (1), and a second end of the debug interface (5) being coupled to the device.

Optionally, a communication interface (6) may be further included, a first end of the communication interface (6) being coupled to the FPGA (1), and a second end of the communication interface (6) being coupled to the device.

Alternatively, the communication interface (6) may be configured as a key trigger.

Optionally, a download interface (7) may be further included, a first end of the download interface (7) being coupled to the FPGA (1), and a second end of the download interface (7) being coupled to the device.

Optionally, a display interface (8) may also be included, the display interface (8) coupling the display to the FPGA (1).

Optionally, a key control module (9) may be further included, the key control module (9) being coupled to the FPGA (1).

Optionally, a peripheral unit (10) may be further included, a first end of the peripheral unit (10) being coupled to the FPGA (1), and a second end of the peripheral unit (10) being coupled to the high-speed connector (2).

Optionally, the peripheral unit (10) may include a chip common communication interface (6) including, but not limited to, ethernet, USB, UART, ADC, DAC, and the like.

Optionally, a power supply (11) may be further included, where the power supply (11) is mounted on the chip test board and supplies power to the chip test board (T).

Optionally, a memory module (12) may also be included, the memory module (12) being coupled to the FPGA (1).

In order to better understand the technical solution of the present utility model, the following description is given with reference to a specific example, in which details are listed mainly for the purpose of understanding, and are not to be construed as limiting the scope of protection of the present utility model.

The FPGA (1) is connected with n sub-boards (3) through a high-speed connector (2), the n sub-boards (3) are respectively connecting plates matched with chip packaging types of various sizes or types, when a certain chip needs to be tested, the sub-boards (3) corresponding to the connecting plates are selected to be connected to the high-speed connector (2), and the chip (4) to be tested is mounted on the selected sub-boards (3), so that the test can be started.

A second embodiment of the present utility model relates to a chip testing apparatus comprising a chip testing board as described above.

It should be noted that in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, and two cases are included: the act is performed solely on the basis of the element and is performed on the basis of the element and other elements. Multiple, etc. expressions include 2, 2 times, 2, and 2 or more, 2 or more times, 2 or more.

Further, it is understood that various changes or modifications of the present utility model may be made by those skilled in the art after reading the above disclosure, and such equivalents are intended to fall within the scope of the utility model as claimed.

Claims

1. A chip test board, comprising: an FPGA (1), a high-speed connector (2) and n daughter boards (3);

the FPGA (1) is coupled to a first end of the high-speed connector (2);

2. The chip test board of claim 1, further comprising a debug interface (5), a first end of the debug interface (5) being coupled to the FPGA (1), a second end of the debug interface (5) being coupled to a device.

3. The chip test board of claim 2, further comprising a communication interface (6), a first end of the communication interface (6) being coupled to the FPGA (1), a second end of the communication interface (6) being coupled to the device.

4. The chip test board of claim 2, further comprising a download interface (7), a first end of the download interface (7) being coupled to the FPGA (1), a second end of the download interface (7) being coupled to the device.

5. The chip test board of claim 1, further comprising a display interface (8), the display interface (8) being configured to couple a display to the FPGA (1).

6. The chip test board of claim 1, further comprising a key control module (9), the key control module (9) being coupled to the FPGA (1).

7. The chip test board of claim 1, further comprising a peripheral unit (10), a first end of the peripheral unit (10) being coupled to the FPGA (1), a second end of the peripheral unit (10) being coupled to the high-speed connector (2).

8. The chip test board of claim 1, further comprising a power supply (11), the power supply (11) being mounted on the chip test board for powering the chip test board.

9. The chip test board of claim 1, further comprising a memory module (12), the memory module (12) being coupled to the FPGA (1).

10. Chip testing apparatus comprising a chip testing board according to any of claims 1-8.