CN115623677A

CN115623677A - Antenna packaging structure and manufacturing method thereof

Info

Publication number: CN115623677A
Application number: CN202110797157.1A
Authority: CN
Inventors: 高自强; 王斐; 李彪; 胡先钦
Original assignee: Avary Holding Shenzhen Co Ltd; Qing Ding Precision Electronics Huaian Co Ltd
Current assignee: Avary Holding Shenzhen Co Ltd; Qing Ding Precision Electronics Huaian Co Ltd
Priority date: 2021-07-14
Filing date: 2021-07-14
Publication date: 2023-01-17
Also published as: TW202304056A; TWI792426B

Abstract

An antenna package structure and a method for manufacturing the same. The manufacturing method comprises the following steps: providing a first circuit substrate which comprises a first inner laminated structure, wherein the first inner laminated structure comprises a first surface and a second surface, a first outer circuit layer is embedded in the first inner laminated structure and exposed out of the first surface, and an antenna layer is arranged on the second surface; forming a conductive layer on the first outer circuit layer to form a conductive column; the first surface is provided with a containing groove; installing a chip in the accommodating groove, wherein the conductive part of the chip protrudes out of the first surface; forming an adhesive layer on the first surface, wherein the conductive column and the conductive part are respectively provided with a first end part and a second end part which protrude out of the adhesive layer; providing a second circuit substrate which comprises a second inner laminated structure, wherein the second inner laminated structure comprises a third surface and a fourth surface, and a second outer circuit layer is arranged on the third surface and comprises a first connecting pad and a second connecting pad; the first circuit substrate is laminated on the second circuit substrate and pressed, so that the first end portion faces the first connecting pad and the second end portion faces the second connecting pad.

Description

Antenna packaging structure and manufacturing method thereof

Technical Field

The present disclosure relates to the field of antenna packaging, and particularly to an antenna packaging structure and a method for manufacturing the same.

Background

Conventional antenna packaging techniques include: and after the chip is coated in the mold pressing resin to obtain the communication unit, the communication unit is arranged on the circuit board, so that the pins of the chip are electrically connected with the conductive circuit layer of the circuit board. However, there may be problems with signal loss, air bubbles, etc. after the antenna is packaged.

Disclosure of Invention

In order to solve at least one of the above disadvantages, it is necessary to provide an antenna package structure and a method for manufacturing the same.

The application provides a manufacturing method of an antenna packaging structure, which comprises the following steps: providing a first circuit substrate, wherein the first circuit substrate comprises a first inner laminated structure, an antenna layer and a first outer circuit layer, the first inner laminated structure comprises a first surface and a second surface which are opposite to each other, the first outer circuit layer is embedded in the first inner laminated structure and exposed out of the first surface, and the antenna layer is arranged on the second surface; forming a conductive layer on the first outer circuit layer, wherein the conductive layer and the first outer circuit layer are connected to form a plurality of conductive columns; an accommodating groove is formed in the area, where the first surface is not provided with the conductive column; installing a chip in the accommodating groove, wherein the chip comprises a chip body and a conductive part arranged on the chip body, the chip body is installed in the accommodating groove, and the conductive part protrudes out of the first surface; forming an adhesive layer on the first surface having the conductive post and the conductive portion, the conductive post and the conductive portion having a first end and a second end protruding out of the adhesive layer, respectively; providing a second circuit substrate, wherein the second circuit substrate comprises a second inner laminated structure and a second outer circuit layer, the second inner laminated structure comprises a third surface and a fourth surface which are opposite, and the second outer circuit layer is arranged on the third surface and comprises a first connecting pad and a second connecting pad; and laminating the first circuit substrate with the chip on the second circuit substrate to enable the first surface to be opposite to the third surface, the first end portion to face the first connecting pad and the second end portion to face the second connecting pad, and laminating to obtain the antenna packaging structure.

In some possible implementations, after the conductive pillar is formed, the manufacturing method further includes performing surface treatment on the conductive pillar to obtain a first surface treatment layer; a second surface treatment layer is formed on the first connecting pad and the second connecting pad through surface treatment; and the pressing is carried out under the heating condition, so that the first surface treatment layer and the second surface treatment layer are contacted and melted together to form an alloy layer.

In some possible implementation manners, the first circuit substrate is a hard board, the second circuit substrate is a soft board, the second circuit substrate is divided into a first area and a second area along an extending direction of the second circuit substrate, and the first circuit substrate having the chip is disposed on the second area.

In some possible implementations, the second circuit substrate is further provided with an electrical connection portion, the electrical connection portion is electrically connected to the second outer circuit layer, and the electrical connection portion is provided on the first region.

In some possible implementations, forming the conductive layer specifically includes: covering a patterned dry film on the first surface, wherein the patterned dry film is provided with a pattern opening for exposing the first outer circuit layer; forming the conductive layer in the pattern opening; and removing the patterned dry film.

In some possible implementations, the conductive layer is formed by electroplating copper.

In some possible implementation manners, when the adhesive layer is formed, the adhesive layer is in a semi-curing state, a gap is formed between the chip body and the inner wall of the accommodating groove, and after the pressing, part of the adhesive layer is further arranged in the gap.

In some possible implementations, a surface of the chip body is flush with the first surface.

In some possible implementations, the conductive portions are pins or solder balls.

The present application further provides an antenna package structure manufactured by the above manufacturing method, including: the first circuit substrate comprises a first inner laminated structure, an antenna layer and a conductive column, wherein the first inner laminated structure comprises a first surface and a second surface which are opposite to each other, the conductive column comprises a conductive layer and a first outer side circuit layer, the first outer side circuit layer is embedded in the first inner laminated structure and is exposed out of the first surface, the conductive layer is connected with the first outer side circuit layer and protrudes out of the first surface, the antenna layer is arranged on the second surface, and an accommodating groove is formed in the area, not provided with the conductive column, of the first surface; the chip comprises a chip body and a conductive part arranged on the chip body, the chip body is arranged in the accommodating groove, and the conductive part protrudes out of the first surface; the second circuit substrate comprises a second inner laminated structure and a second outer circuit layer, the second inner laminated structure comprises a third surface and a fourth surface which are opposite, the second outer circuit layer is arranged on the third surface and comprises a first connecting pad and a second connecting pad, the first circuit substrate and the second circuit substrate are arranged in a laminated mode, the first surface is opposite to the third surface, the conductive column is electrically connected with the first connecting pad, and the conductive part is electrically connected with the second connecting pad; and the adhesive layer is arranged between the first surface and the third surface and coats the first connecting pad, the second connecting pad, the conductive column and the conductive part.

This application is because the protruding first surface that stretches out of the conductive part of chip, compares in the condition of installing the conductive part of chip in the holding tank bottom, and the conductive part of this application can directly be connected with the second connection pad electricity on second outside line layer, and need not set up extra lead wire, consequently can shorten the transmission path between second outside line layer to the chip, is favorable to reducing signal loss. Moreover, the conductive part of the chip protrudes out of the first surface, so that the situation that bubbles are easily generated at the bottom of the accommodating groove after pressing when the conductive part of the chip is arranged at the bottom of the accommodating groove can be avoided. Moreover, the adhesive layer can fully cover the first connecting pad, the second connecting pad, the conductive column and the conductive part, so that the risk of generating bubbles is further reduced.

Drawings

Fig. 1A is a schematic structural diagram of a first circuit substrate according to an embodiment of the present disclosure.

Fig. 1B is a schematic view of an internal structure of the first circuit substrate shown in fig. 1.

Fig. 2 is a schematic structural view of the first circuit substrate shown in fig. 1 covered with a patterned dry film.

Fig. 3 is a schematic structural diagram of the conductive layer formed in the patterned dry film shown in fig. 2 to form the conductive pillar.

Fig. 4 is a schematic structural view of the first circuit substrate shown in fig. 3 after a receiving groove is formed therein.

Fig. 5 is a schematic structural view of the chip mounted in the accommodating groove shown in fig. 4.

Fig. 6 is a schematic structural view of the first circuit substrate shown in fig. 5 after an adhesive layer is disposed thereon.

Fig. 7 is a schematic structural diagram of a second circuit substrate according to an embodiment of the present disclosure.

Fig. 8 is a schematic structural diagram of an antenna package structure obtained by laminating and pressing the first circuit substrate shown in fig. 6 and the second circuit substrate shown in fig. 7.

Description of the main elements

First circuit board 10

First inner laminate 11

First surface 11A

Second surface 11B

First outer wiring layer 12

Antenna layer 13

Conductive layer 14

Conductive post 15

Accommodating groove 16

Patterned dry film 20

Pattern opening 21

Chip 30

Chip body 31

Conductive part 32

Adhesive layer 40

Second circuit board 50

Second inner laminate 51

Third surface 51A

Fourth surface 51B

Second outer wiring layer 52

Electric connection part 53

Antenna package structure 100

Flexible board area 101

Hard plate region 102

First base layer 110

First inner circuit layer 111

Adhesive layer 112

Conduction part 113

First surface treatment layer 150

First end 151

Second end 321

First region 501

Second region 502

Second base layer 510

Second inner wiring layer 511

First connecting pad 521

Second connecting pad 522

Second surface treatment layer 5210

Gold-tin alloy layer L

The following detailed description will further illustrate the present application in conjunction with the above-described figures.

Detailed Description

The following description will refer to the accompanying drawings to more fully describe the present disclosure. There is shown in the drawings exemplary embodiments of the present application. This application may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. These exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like reference numerals designate identical or similar components.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Further, as used herein, the terms "comprises," "comprising," "includes" and/or "including" or "having" and/or "having," integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. Furthermore, unless otherwise defined herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present application and will not be interpreted in an idealized or overly formal sense.

The following description of exemplary embodiments refers to the accompanying drawings. It should be noted that the components depicted in the referenced drawings are not necessarily shown to scale; and the same or similar components will be given the same or similar reference numerals or similar terms.

Embodiments of the present application will now be described in further detail with reference to the accompanying drawings.

An embodiment of the present application provides a method for manufacturing an antenna package structure, which includes the following steps:

step S1: referring to fig. 1A and 1B, a first circuit substrate 10 is provided. The first wiring substrate 10 includes a first inner laminated structure 11, an antenna layer 13, and a first outer wiring layer 12. The first inner laminate 11 includes opposing first and

second surfaces

11A, 11B. The first outer circuit layer 12 is embedded in the first inner stacked structure 11 and exposed to the first surface 11A. The antenna layer 13 is disposed on the second surface 11B.

In some embodiments, the surface of the first outer wiring layer 12 may be flush with the first surface 11A of the first inner laminate 11.

In some embodiments, the first inner laminated structure 11 includes a first base layer 110 and at least a first inner circuit layer 111 disposed on the first base layer 110. Adhesive layers 112 are disposed between the antenna layer 13 and an adjacent first inner circuit layer 111, between two adjacent first inner circuit layers 111, between the first base layer 110 and an adjacent first inner circuit layer 111, and between the first outer circuit layer 12 and an adjacent first inner circuit layer 111. The first inner laminated structure 11 is further provided with a conducting portion 113, and the conducting portion 113 penetrates through the first inner laminated structure 11 for electrically connecting the antenna layer 13 and the first outer circuit layer 12.

Step S2: referring to fig. 2, a patterned dry film 20 is covered on the first surface 11A having the first outer circuit layer 12. The patterned dry film 20 has a pattern opening 21 for exposing the first outer wiring layer 12.

And step S3: referring to fig. 3, the conductive layer 14 is formed in the pattern opening 21, and then the patterned dry film 20 is removed. The conductive layer 14 and the first outer circuit layer 12 are connected to each other and collectively form a plurality of conductive posts 15. Therefore, each conductive pillar 15 is partially buried in the first circuit substrate 10, and the other part protrudes from the first surface 11A.

In some embodiments, conductive layer 14 may be formed by electroplating copper.

In some embodiments, a surface treatment may be further performed on the protruding portion of the conductive pillar 15, so as to obtain the first surface treatment layer 150. Specifically, the first surface treatment layer 150 may be formed on the top surface and the side surface of the portion from which the conductive pillar 15 protrudes.

The first surface treatment layer 150 is used to prevent the conductive pillar 15 from being exposed to the first surface 11A and thus being oxidized, which may affect the electrical characteristics of the conductive pillar. The surface treatment may be performed by forming a protective layer (not shown) by electroless gold plating, electroless nickel plating, or the like, or forming an organic solderability preservative (OSP, not shown) on the conductive posts 15.

And step S4: referring to fig. 4, an accommodating groove 16 is formed in a region of the first surface 11A where the conductive pillar 15 is not disposed. The accommodating groove 16 is formed from the first surface 11A to the second surface 11B, and the accommodating groove 16 does not penetrate through the second surface 11B.

In some embodiments, receiving slot 16 may be formed by laser machining. In other embodiments, the receiving groove 16 may be formed by a mechanical cutting method such as high pressure water jet, air knife cutting, lathe, or other methods such as chemical etching and physical etching.

Step S5: referring to fig. 5, a chip 30 is mounted in the receiving groove 16. The chip 30 includes a chip body 31 and a conductive portion 32 provided on the chip body 31. The chip body 31 is mounted in the receiving groove 16, and the conductive portion 32 protrudes out of the first surface 11A.

In some embodiments, the conductive portions 32 may be pins or solder balls.

In some embodiments, the surface of the chip body 31 may be flush with the first surface 11A.

Step S6: referring to fig. 6, a liquid adhesive is formed on the first surface 11A having the conductive post 15 and the conductive portion 32 and is pre-cured, so that the liquid adhesive is converted into a semi-cured adhesive layer 40. The semi-curing means that the adhesive layer 40 is already formed into an adhesive film, but still has fluidity under pressure. The conductive column 15 and the conductive part 32 have a first end 151 and a second end 321 protruding out of the adhesive layer 40, respectively.

In some embodiments, the liquid glue is filled in the gaps between the conductive posts 15, the gaps between the conductive portions 32, and the gaps between the conductive posts 15 and the conductive portions 32.

In some embodiments, a certain gap may be provided between the chip body 31 and the inner wall of the receiving groove 16. Part of the adhesive layer 40 may also be disposed in the gap between the chip body 31 and the inner wall of the receiving groove 16, so as to fix the chip body 31 in the receiving groove 16.

Step S7: referring to fig. 7, a second circuit substrate 50 is provided. The second circuit substrate 50 includes a second inner laminate 51 and a second outer circuit layer 52. The second inner laminate 51 includes third and fourth opposing

surfaces

51A, 51B. The second outer circuit layer 52 is disposed on the third surface 51A and includes a first connecting pad 521 and a second connecting pad 522.

In some embodiments, the second inner laminated structure 51 includes a second base layer 510 and at least a second inner wiring layer 511 embedded in the second base layer 510.

In some embodiments, the second wiring substrate 50 further includes an electrical connection portion 53. The electrical connection portion 53 may be electrically connected to the second outer wiring layer 52 through the second inner wiring layer 511. Wherein, the electrical connection portion 53 can be disposed on the third surface 51A or the fourth surface 51B. The electrical connection 53 may be an electrical connector or a gold finger. The electrical connection portion 53 is used for electrical connection with an external main board (not shown).

In some embodiments, the first connecting pad 521 and the second connecting pad 522 may also have a second surface treatment layer 5210 formed thereon by surface treatment. The second surface treatment layer 5210 is used to prevent the first connecting pad 521 and the second connecting pad 522 from being exposed out of the third surface 51A and thus from surface oxidation, which may affect the electrical characteristics thereof. The surface treatment may be performed by forming a protective layer (not shown) by electroless gold plating, electroless nickel plating, or the like, or forming an organic solderability preservative (OSP, not shown) on the conductive posts 15.

Step S8: referring to fig. 8, the first circuit substrate 10 having the chip 30 is stacked on the second circuit substrate 50 such that the first surface 11A is opposite to the third surface 51A. Furthermore, the first end 151 of the conductive post 15 faces the first connection pad 521 and the second end 321 of the conductive portion 32 faces the second connection pad 522, so as to obtain an intermediate body (not shown). And pressing the intermediate to obtain the antenna packaging structure 100.

Since the adhesive layer 40 is in a semi-cured state, the adhesive layer 40 can flow and fix the first end portion 151 and the first connection pad 521 of the conductive post 15, and the second end portion 321 and the second connection pad 522 of the conductive fixing portion 32. Thereby, the electrical connection between the chip 30 and the second wiring substrate 50 is achieved. On the other hand, the fluidity of the adhesive layer 40 enables the adhesive layer to fully coat the first connecting pad 521, the second connecting pad 522, the conductive post 15 and the conductive portion 32, thereby improving the filling performance thereof and reducing the risk of generating bubbles after lamination.

In some embodiments, the first surface treatment layer 150 may be a electroless gold plating layer and the second surface treatment layer 5210 may be an electroless tin plating layer. The pressing is performed under a heating condition, so that the first surface treatment layer 150 and the second surface treatment layer 5210 are brought into contact with each other and then melted together under a heating condition to form the gold-tin alloy layer L.

The first circuit board 10 is a hard board, and the second circuit board 50 may be a hard board or a soft board. In some embodiments, the second circuit substrate 50 is a flexible board. The second circuit board 50 is divided into a first region 501 and a second region 502 along the extending direction thereof, the electrical connection portion 53 is disposed on the first region 501, and the first circuit board 10 having the chip 30 is disposed on the second region 502. Thus, the antenna package structure 100 includes a flexible board region 101 and a rigid board region 102. Wherein the first region 501 of the second circuit substrate 50 forms the flexible board region 101. The second region 502 of the second circuit substrate 50 and the first circuit substrate 10 with the chip 30 form the hard board region 102.

In some embodiments, the first base layer 110 and the adhesive layer of the first circuit substrate 10 are both made of flexible materials. In some embodiments, the material of the first base layer 110 and the adhesive layer may be at least one of Polyimide (PI), polyethylene naphthalate (PEN), or Polyethylene terephthalate (PET).

The second base layer 510 of the second circuit board 50 is a hard material, and may be a composite material of fibers and resin, specifically, may be formed of fibers such as glass fibers or organic fibers, and resins such as epoxy resin, polyimide resin, bismaleimide Triazine (BT) resin, polyphenylene ether (PPE) resin, polyphenylene oxide (PPO) resin, and the like, which are impregnated in the fiber material; the resin composition may be formed of a porous film such as a Polyimide (PI) film, an aromatic polyamide film, a Polytetrafluoroethylene (PTFE) film, a Liquid Crystal Polymer (LCP) film, or the like, and a resin such as an epoxy resin, a Polyimide resin, a Bismaleimide Triazine (BT) resin, a polyphenylene ether (PPE) resin, a polyphenylene oxide (PPO) resin, or the like, which is impregnated in the porous film; the adhesive layer may be formed of a thin film such as a Polyimide (PI) thin film, an aromatic polyamide thin film, or a Liquid Crystal Polymer (LCP) thin film, and an adhesive provided on both surfaces of the thin film.

In operation, the antenna layer 13 can radiate a transmission signal outwards. On the other hand, the antenna layer 13 may also be configured to receive an electrical signal and transmit the electrical signal from the second circuit substrate 50 to the main board, so that the main board can analyze or process the electrical signal.

This application is through burying chip 30 in storage tank 16 for antenna packaging structure 100 wholly has less thickness, and first circuit substrate 10 can provide effects such as protection, electromagnetic shield for chip 30, and the isolation of signal improves, and the reliability also correspondingly improves. Secondly, since the conductive portion 32 of the chip 30 protrudes out of the first surface 11A, compared with the case that the conductive portion 32 of the chip 30 is mounted at the bottom of the receiving groove 16, the conductive portion 32 of the present application can be directly electrically connected to the second connecting pad 522 of the second outer circuit layer 52 without providing an additional lead, so that the transmission path between the second outer circuit layer 52 and the chip 30 can be shortened, which is beneficial to reducing signal loss. Moreover, the conductive portion 32 of the chip 30 protrudes out of the first surface 11A, so that when the conductive portion 32 of the chip 30 is mounted at the bottom of the accommodating groove 16, bubbles are easily generated at the bottom of the accommodating groove 16 after pressing. Again, the conductive column 15 is formed by electroplating on the first outer circuit layer 12, which is beneficial to improving the consistency of signal transmission. Finally, the chip 30 is embedded in the first circuit substrate 10 without fabricating an external circuit layer on the first circuit substrate 10, thereby preventing the conductive portion 32 of the chip 30 from being etched back by a wet process used for fabricating the external circuit layer.

Referring to fig. 8, an embodiment of the present invention further provides an antenna package structure 100 including a first circuit substrate 10, a second circuit substrate 50, a chip 30 and an adhesive layer 40.

The first wiring substrate 10 includes a first inner laminated structure 11, an antenna layer 13, and a conductive pillar 15. The first inner laminate 11 includes opposing first and

second surfaces

11A and 11B. The conductive post 15 includes the conductive layer 14 and the first outer wiring layer 12. The first outer circuit layer 12 is embedded in the first inner stacked structure 11 and exposed to the first surface 11A. The conductive layer 14 is connected to the first outer wiring layer 12 and protrudes out of the first surface 11A. The antenna layer 13 is disposed on the second surface 11B. The first surface 11A is provided with a receiving groove 16 in a region where the conductive pillar 15 is not disposed. The accommodating groove 16 is formed from the first surface 11A to the second surface 11B, and the accommodating groove 16 does not penetrate through the second surface 11B. The chip 30 is mounted in the receiving groove 16. The chip 30 includes a chip body 31 and conductive portions 32 provided on the chip body 31. The chip body 31 is mounted in the receiving groove 16, and the conductive portion 32 protrudes out of the first surface 11A.

The second circuit substrate 50 includes a second inner laminate 51 and a second outer circuit layer 52. The second inner laminate 51 includes third and fourth opposing

surfaces

51A, 51B. The second outer circuit layer 52 is disposed on the third surface 51A and includes a first connecting pad 521 and a second connecting pad 522. The first circuit substrate 10 and the second circuit substrate 50 are stacked, and the first surface 11A is opposite to the third surface 51A. The conductive pillar 15 is electrically connected to the first bonding pad 521, and the conductive portion 32 is electrically connected to the second bonding pad 522. The adhesive layer 40 is disposed between the first surface 11A and the third surface 51A, and covers the first connection pad 521, the second connection pad 522, the conductive pillar 15 and the conductive portion 32.

Although the present invention has been described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the present invention.

Claims

1. A manufacturing method of an antenna packaging structure comprises the following steps:

providing a first circuit substrate, wherein the first circuit substrate comprises a first inner laminated structure, an antenna layer and a first outer circuit layer, the first inner laminated structure comprises a first surface and a second surface which are opposite, the first outer circuit layer is embedded in the first inner laminated structure and exposed out of the first surface, and the antenna layer is arranged on the second surface;

forming a conductive layer on the first outer circuit layer, wherein the conductive layer and the first outer circuit layer are connected to form a plurality of conductive columns;

an accommodating groove is formed in the area, where the first surface is not provided with the conductive column;

installing a chip in the accommodating groove, wherein the chip comprises a chip body and a conductive part arranged on the chip body, the chip body is installed in the accommodating groove, and the conductive part protrudes out of the first surface;

forming an adhesive layer on the first surface having the conductive post and the conductive portion, the conductive post and the conductive portion having a first end and a second end protruding out of the adhesive layer, respectively;

providing a second circuit substrate, wherein the second circuit substrate comprises a second inner laminated structure and a second outer circuit layer, the second inner laminated structure comprises a third surface and a fourth surface which are opposite, and the second outer circuit layer is arranged on the third surface and comprises a first connecting pad and a second connecting pad;

and laminating the first circuit substrate with the chip on the second circuit substrate to enable the first surface to be opposite to the third surface, the first end portion to face the first connecting pad and the second end portion to face the second connecting pad, and laminating to obtain the antenna packaging structure.

2. The method for manufacturing an antenna package structure according to claim 1, wherein after the conductive pillar is formed, the method further includes performing a surface treatment on the conductive pillar to obtain a first surface treatment layer;

a second surface treatment layer is formed on the first connecting pad and the second connecting pad through surface treatment;

and the pressing is carried out under the heating condition, so that the first surface treatment layer and the second surface treatment layer are contacted and melted together to form an alloy layer.

3. The method of manufacturing an antenna package structure according to claim 1, wherein the first circuit substrate is a hard board, the second circuit substrate is a soft board, the second circuit substrate is divided into a first region and a second region along an extending direction of the second circuit substrate, and the first circuit substrate having the chip is disposed on the second region.

4. The method for manufacturing an antenna package structure according to claim 3, wherein the second circuit substrate is further provided with an electrical connection portion, the electrical connection portion is electrically connected to the second outer circuit layer, and the electrical connection portion is disposed on the first region.

5. The method for manufacturing an antenna package structure according to claim 1, wherein the forming the conductive layer specifically includes:

covering a patterned dry film on the first surface, wherein the patterned dry film is provided with a pattern opening for exposing the first outer circuit layer;

forming the conductive layer in the pattern opening;

and removing the patterned dry film.

6. The method for manufacturing an antenna package structure according to claim 5, wherein the conductive layer is formed by electroplating copper.

7. The method for manufacturing an antenna package structure according to claim 1, wherein the adhesive layer is semi-cured when the adhesive layer is formed, a gap is formed between the chip body and the inner wall of the accommodating groove, and after the bonding, a part of the adhesive layer is further disposed in the gap.

8. The method for manufacturing an antenna package structure according to claim 1, wherein a surface of the chip body is flush with the first surface.

9. The method of claim 1, wherein the conductive portion is a pin or a solder ball.

10. An antenna package structure manufactured by the manufacturing method of any one of claims 1 to 9, comprising:

the first circuit substrate comprises a first inner laminated structure, an antenna layer and a conductive column, wherein the first inner laminated structure comprises a first surface and a second surface which are opposite to each other, the conductive column comprises a conductive layer and a first outer side circuit layer, the first outer side circuit layer is embedded in the first inner laminated structure and is exposed out of the first surface, the conductive layer is connected with the first outer side circuit layer and protrudes out of the first surface, the antenna layer is arranged on the second surface, and an accommodating groove is formed in the area, not provided with the conductive column, of the first surface;

the chip comprises a chip body and a conductive part arranged on the chip body, the chip body is arranged in the accommodating groove, and the conductive part extends out of the first surface;

the second circuit substrate comprises a second inner laminated structure and a second outer circuit layer, the second inner laminated structure comprises a third surface and a fourth surface which are opposite, the second outer circuit layer is arranged on the third surface and comprises a first connecting pad and a second connecting pad, the first circuit substrate and the second circuit substrate are arranged in a laminated mode, the first surface is opposite to the third surface, the conductive column is electrically connected with the first connecting pad, and the conductive part is electrically connected with the second connecting pad;

and the adhesive layer is arranged between the first surface and the third surface and coats the first connecting pad, the second connecting pad, the conductive column and the conductive part.