CN115603713A - Pulse signal processing method and device and matching circuit - Google Patents
Pulse signal processing method and device and matching circuit Download PDFInfo
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Abstract
The application provides a pulse signal processing method, a pulse signal processing device and a matching circuit, wherein the method is applied to a storage control unit of the matching circuit, the matching circuit comprises a storage control unit and a reading control unit, the storage control unit is used for acquiring a power supply signal from a power supply and writing the power supply signal into an internal preset storage area, and the reading control unit is used for reading the power supply signal stored in the preset storage area from the storage control unit and transmitting the power supply signal to a load; the method comprises the following steps: if the power supply signal which comprises the low-level pulse information and is from the power supply is obtained, detecting whether the duration time of the power supply signal which comprises the low-level pulse information is longer than a first preset time length; if not, maintaining the writing of the power supply signal in the high level state into the preset storage area; and if so, writing the power supply signal in a low level state into the preset storage area. The embodiment of the application is beneficial to improving the working reliability of the matching circuit.
Description
Technical Field
The present application relates to the field of electronic circuit technologies, and in particular, to a pulse signal processing method and apparatus, and a matching circuit.
Background
In a power supply system, a matching circuit is usually required between a load and a power supply, and a power supply signal from the power supply is transmitted to the load through the matching circuit. Due to the fact that operation of devices is delayed, when a power supply signal is transmitted to a load by a matcher at present, the problems that pulse signal waveforms cannot be accurately read and pulse signal wave troughs cannot be read mistakenly exist, and due to the fact that a matching circuit cannot actively judge whether the matching circuit is in a closed state or a continuous closed state in a pulse state, the matching circuit cannot transmit the pulse signal to the load, and the matching circuit has the problem of working reliability.
Disclosure of Invention
The present application aims to overcome the deficiencies in the prior art, and provide a pulse signal processing method, a pulse signal processing device, and a matching circuit, so as to improve the reliability of the matching circuit.
In order to achieve the above object, the present application provides a pulse signal processing method applied to a storage control unit of a matching circuit, where the matching circuit includes the storage control unit and a read control unit, the storage control unit is configured to obtain a power signal from a power supply and write the power signal into an internal preset storage area, and the read control unit is configured to read the power signal stored in the preset storage area from the storage control unit and transmit the power signal to a load; the method comprises the following steps:
if the power supply signal which comprises the low-level pulse information and is from the power supply is obtained, detecting whether the duration time of the power supply signal which comprises the low-level pulse information is longer than a first preset time length;
if not, maintaining the writing of the power supply signal in the high level state into the preset storage region;
and if so, writing the power supply signal in a low level state into the preset storage region.
Further, the method further comprises: and if a power supply signal including high-level pulse information from the power supply is acquired, maintaining the power supply signal in the high-level state written into the preset storage region within a second preset time length, wherein the second preset time length is not less than the time interval between the next time when the reading control unit reads the power supply signal and the current moment.
Further, the reading control unit reads the power supply signal from the storage control unit every third preset time interval; the second preset time length is not less than the preset time length with a larger numerical value in the third preset time length and the fourth preset time length, and the fourth preset time length is the device operation time length from the time when the reading control unit starts to read the power supply signal to the time when the reading control unit actually reads the power supply signal.
The application also provides another pulse signal processing method, which is applied to a storage control unit of a matching circuit, wherein the matching circuit comprises the storage control unit and a reading control unit, the storage control unit is used for acquiring a power supply signal from a power supply and storing the power supply signal in an internal preset storage area, and the reading control unit is used for reading the power supply signal stored in the preset storage area from the storage control unit and transmitting the power supply signal to a load; the method comprises the following steps: and if a power supply signal including high-level pulse information from the power supply is acquired, maintaining the power supply signal in the high-level state written into the preset storage region within a second preset time length, wherein the second preset time length is not less than the time interval between the next time when the reading control unit reads the power supply signal and the current moment.
Further, the reading control unit reads the power supply signal from the storage control unit every third preset time interval; the second preset time length is not less than the preset time length with a larger numerical value in the third preset time length and the fourth preset time length, and the fourth preset time length is the device operation time length from the time when the reading control unit starts to read the power supply signal to the time when the reading control unit actually reads the power supply signal.
Further, the method further comprises: if the power supply signal which comprises the low-level pulse information and is from the power supply is obtained, detecting whether the duration time of the power supply signal which comprises the low-level pulse information is longer than a first preset time length; if not, maintaining the writing of the power supply signal in the high level state into the preset storage region; and if so, writing the power supply signal in a low level state into the preset storage region.
The application also provides a pulse signal processing device which is applied to a storage control unit of a matching circuit, wherein the matching circuit comprises the storage control unit and a reading control unit, the storage control unit is used for acquiring a power supply signal from a power supply and storing the power supply signal in an internal preset storage area, and the reading control unit is used for reading the power supply signal stored in the preset storage area from the storage control unit and transmitting the power supply signal to a load; the device comprises: the detection module is used for detecting whether the duration time of the power supply signal containing the low-level pulse information is longer than a first preset time length or not if the power supply signal containing the low-level pulse information from the power supply is obtained; the first writing module is used for maintaining the writing of the power supply signal in the high level state into the preset storage area if the power supply signal is not written into the preset storage area; and the second writing module is used for writing the power supply signal in the low level state into the preset storage region if the power supply signal is in the low level state.
The application also provides another pulse signal processing device which is applied to a storage control unit of a matching circuit, wherein the matching circuit comprises the storage control unit and a reading control unit, the storage control unit is used for acquiring a power supply signal from a power supply and storing the power supply signal in an internal preset storage area, and the reading control unit is used for reading the power supply signal stored in the preset storage area from the storage control unit and transmitting the power supply signal to a load; the device comprises: and the writing module is used for maintaining the power supply signal in the high level state written into the preset storage region within a second preset time length if the power supply signal including the high level pulse information from the power supply is acquired, wherein the second preset time length is not less than the time interval between the next time the reading control unit reads the power supply signal and the current time.
The application also provides a matching circuit, which comprises a storage control unit and a reading control unit, wherein the storage control unit is electrically connected with the reading control unit; the storage control unit is used for detecting whether the duration time of the power supply signal containing the low-level pulse information is longer than a first preset time length or not if the power supply signal containing the low-level pulse information from the power supply is obtained; if not, maintaining the writing of the power supply signal in the high level state into a preset storage area in the storage control unit; if so, writing a power supply signal in a low level state into the preset storage region; the reading control unit is used for reading the power supply signal stored in the preset storage area from the storage control unit and transmitting the power supply signal to a load.
The application also provides another matching circuit which comprises a storage control unit and a reading control unit, wherein the storage control unit is electrically connected with the reading control unit; the storage control unit is used for maintaining a power supply signal in a high level state written into a preset storage region in the storage control unit within a second preset time length if the power supply signal including high level pulse information from a power supply is obtained, wherein the second preset time length is not less than the time interval between the next time the power supply signal is read by the reading control unit and the current time; the reading control unit is used for reading the power supply signal stored in the preset storage area from the storage control unit and transmitting the power supply signal to a load.
It can be seen that, in the embodiment of the present application, the storage control unit in the matching circuit is configured to acquire a power signal from a power supply and write the power signal into the internal preset storage area, the read control unit is configured to read the power signal stored in the preset storage area from the storage control unit and transmit the power signal to a load, when the read control unit acquires a power signal including low-level pulse information from the power supply, the read control unit may detect whether a duration time of the power signal including the low-level pulse information is longer than a first preset duration, and maintain to write the power signal in a high-level state into the preset storage area all the time when the duration time of the power signal including the low-level pulse information is not longer than the first preset duration, and only write the power signal in the low-level state into the preset storage area when the duration time of the power signal including the low-level pulse information is longer than the first preset duration, which is beneficial to ensuring that the read control unit can stably read the high-level pulse information when reading the power signal, so that the acquired power signal can be stably transmitted to the load to perform pulse operation, and thus being beneficial to improving the reliability of the operation of the matching circuit.
Drawings
The present application is further explained by means of the attached drawings, but the embodiments in the attached drawings do not constitute any limitation to the present application, and for a person skilled in the art, other drawings can be obtained from the following drawings without inventive effort.
Fig. 1 is a schematic structural diagram of a power supply system provided in the present application;
fig. 2 is a schematic diagram of a matching circuit according to the present disclosure;
fig. 3 is a schematic flow chart of a pulse signal processing method provided in the present application;
FIG. 4 is a schematic diagram of a power supply signal provided by an embodiment of the present application;
fig. 5 is a schematic diagram illustrating transmission of a power signal in a power supply system according to an embodiment of the present disclosure;
FIG. 6 is a schematic diagram illustrating transmission of power signals in another power system provided by an embodiment of the present application;
fig. 7 is a schematic flowchart of another pulse signal processing method provided in the embodiment of the present application;
fig. 8 is a functional block diagram of a pulse signal processing apparatus according to an embodiment of the present application;
fig. 9 is a functional block diagram of another pulse signal processing apparatus according to an embodiment of the present application.
Detailed Description
The technical solutions of the present application will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
Referring to fig. 1, fig. 1 is a schematic diagram of a configuration of a power supply system according to an embodiment of the present disclosure, the power supply system includes a matching circuit, and a power supply and a load respectively connected to the matching circuit, wherein the power supply is configured to provide a power supply signal, and after the matching circuit obtains the power supply signal from the power supply, the matching circuit adjusts a load impedance between the power supply and the matching power supply and the load, and simultaneously forwards the power supply signal to the load. In a specific implementation, the power supply system may be, for example, a plasma power supply system, i.e., the load in the power supply system may be, for example, a plasma chamber load.
Referring to fig. 2, fig. 2 is a schematic diagram of a configuration of a matching circuit according to an embodiment of the present disclosure, and specifically, the matching circuit may be applied to the power supply system shown in fig. 1, where the matching circuit includes a storage control unit and a read control unit, where the storage control unit is configured to obtain a power supply signal from a power supply and write the power supply signal into an internal preset storage area, and the read control unit is configured to read the power supply signal stored in the preset storage area from the storage control unit and transmit the power supply signal to a load.
In a possible embodiment, the storage control unit is specifically configured to: if the power supply signal which comprises the low-level pulse information and is from the power supply is obtained, detecting whether the duration time of the power supply signal which comprises the low-level pulse information is longer than a first preset time length; if not, maintaining the writing of the power supply signal in the high level state into the preset storage region; and if so, writing the power supply signal in a low level state into the preset storage region.
In another possible implementation, the storage control unit is specifically configured to: and if a power signal including high-level pulse information from the power supply is acquired, maintaining the power signal in a high-level state written into the preset storage region within a second preset time length, wherein the second preset time length is not less than the time interval between the time when the reading control unit reads the power signal next time and the current moment.
In the above embodiment, after the storage control unit obtains the information including the high level pulse information or the low level pulse information, reference may be made to relevant contents of the following method embodiments to store the power supply signal, which is not described herein again.
It can be seen that, in the embodiment of the present application, the storage control unit included in the matching circuit writes the low-level loaded power signal into the preset storage area when the duration of the power signal including the low-level pulse information is longer than a first preset duration, otherwise, writes the high-level power signal into the preset storage area continuously; or when the storage control unit receives a power supply signal which comprises high-level pulse information and is from a power supply, the storage control unit maintains a high-level state written into the preset storage area within a second preset duration which is not less than the time interval between the next time that the reading control unit reads the power supply signal and the current time; the above embodiments can all enable the reading control unit to stably read the power supply signal in the high level state to obtain the pulse information when reading the power supply signal from the storage control unit, thereby stably transmitting the power supply signal to the load, and being beneficial to improving the reliability of the work of the matching circuit.
Referring to fig. 3, fig. 3 is a schematic flowchart of a pulse signal processing method that is provided in an embodiment of the present application and is applicable to a storage control unit of a matching circuit shown in fig. 2, where the matching circuit includes the storage control unit and a read control unit, the storage control unit is configured to obtain a power signal from a power source and write the power signal into an internal preset storage area, and the read control unit is configured to read the power signal stored in the preset storage area from the storage control unit and transmit the power signal to a load; the method comprises the following steps:
in a specific implementation, the power source may be a radio frequency power source, the first preset duration may be set according to a type of the radio frequency power source, when the radio frequency power source is a fixed frequency power source, that is, a pulse frequency of the power source is fixed, the first preset duration is not less than a time interval between a last high level of a previous pulse and a first high level of a subsequent pulse, that is, the first preset duration is not less than a time interval between a high level end time of the previous pulse and a high level start time of the subsequent pulse, and when the radio frequency power source is a variable frequency power source, that is, a pulse frequency of the power source is changed, the first preset duration is not less than a maximum value in a time interval between a high level end time of the previous pulse and a high level start time of the subsequent pulse.
Step 202, if not, maintaining writing the power supply signal in the high level state into the preset storage area;
and 203, writing a power supply signal in a low level state into the preset storage area if the power supply signal is in the low level state.
In step 202 and step 203, the storage control unit writes the power signal into the preset storage area, that is, the storage control unit continuously updates the power signal stored in the preset storage area, and when the read control unit reads the power signal from the storage control unit, the read power signal is continuously updated.
Specifically, referring to fig. 4, fig. 4 is a schematic diagram of a power supply signal provided in an embodiment of the present application, and fig. 4 shows a waveform diagram of a raw power supply signal and a power supply signal in a preset storage region, where the raw power supply signal is a power supply signal transmitted to a matching circuit from a power supply in the power supply system shown in fig. 1, and the power supply signal in the preset storage region is stored in the preset storage region when the power supply signal in the preset storage region, i.e., the power supply signal is read from the storage control unit by a read control unit in the matching circuit shown in fig. 2 in fig. 4. In the legend of the power supply signal in the preset storage area, a solid line represents the actually stored power supply signal, and an area marked by a dotted line corresponds to high-level pulse information in the original power supply signal.
Taking the case that the reading control unit reads the power signals from the storage control unit at time points t1, t2, and t3, respectively, if the storage control unit does not control the storage policy of the power signals, that is, if the storage control unit obtains the power signals including the low-level pulse information, the power signals in the low-level state are directly written into the preset storage region, and if the storage control unit obtains the power signals including the high-level pulse information, the power signals in the high-level state are written into the preset storage region, the power signals stored in the preset storage region are consistent with the original power signals, referring to fig. 5, at this time, the transmission process of the power signals in the power system may be as shown in fig. 5, and the reading control unit may erroneously read the pulse signal troughs at time points t1 and t3, so that the power signals cannot be stably transmitted to the load.
In step 201-step 203, when the duration of the obtained power signal including the low-level pulse information is short (i.e., not higher than the first preset duration), the read control unit does not write the power signal in the low-level state into the preset storage region, but continuously writes the power signal in the high-level state into the preset storage region, and when the duration of the power signal including the low-level pulse information is long (i.e., higher than the first preset duration), the low-level pulse signal is written into the preset storage region, and at this time, the power signal stored in the preset storage region can be continuously maintained in the high-level state, as shown in fig. 6, the transmission process of the power signal in the power system can be as shown in fig. 6, when the read control unit reads the power signal at time points t1, t2, and t3, the power signal in the high-level state can be stably obtained, the load impedance can be stably transmitted to the load, and meanwhile, when the duration of the low-level pulse information is higher than the preset duration, the power signal in the high-level state can be stably written into the read control unit, so that the read control unit can correctly read the load, and the off reliability of the circuit can be favorably improved.
In specific implementation, the storage control unit may be, for example, a field programmable gate array FPGA, the preset storage region may be a memory of the FPGA, and the read control unit may be, for example, a core single chip microcomputer STM32. Of course, the selection device is only an exemplary illustration, and the selection of the specific devices of the storage control unit and the reading control unit in practical applications is not limited to this.
In one possible example, the method further comprises: and if a power supply signal including high-level pulse information from the power supply is acquired, maintaining the power supply signal in the high-level state written into the preset storage region within a second preset time length, wherein the second preset time length is not less than the time interval between the next time when the reading control unit reads the power supply signal and the current moment.
In the specific implementation, if the storage control unit writes the power signal in the high level state into the preset storage area only within the duration of receiving the power signal of the high level pulse information, the power signal in the high level state is not written into the preset storage area any more but is written into the power signal in the low level state when the power signal of the high level pulse information is not obtained, and if the duration of the power signal in the high level state is less than the time for reading the power signal from the preset storage area next time by the reading control unit, the power signal in the low level state which may be read by the reading control unit when the power signal is read next time is read, so that the reliability of the operation of the matching circuit is affected. By setting a second preset duration which is not less than the time interval between the next time the reading control unit reads the power signal and the current time, after the storage control unit obtains the power signal comprising the high-level pulse information, the time for writing the power signal in the high-level state into the preset storage area is prolonged by the second preset duration, so that the time interval between the end time of the power signal in the high-level state stored in the preset storage area and the end time of the high-level pulse in the original power signal input by the power source is made to be the second preset duration after the end time of the high-level pulse in the original power signal input by the power source, and the time interval between the end time of the power signal in the high-level state stored in the preset storage area and the end time of the high-level pulse in the original power signal input by the power source is made to be the second preset duration, and when the reading control unit reads the power signal next time, the power signal in the high-level state can still be accurately obtained.
As can be seen, in this example, when the storage control unit obtains the power signal including the high-level pulse information, the storage control unit continuously writes the power signal in the high-level state into the preset storage region within a second preset duration that is not less than a time interval between a next time when the reading control unit reads the power signal and a current time, so that the reading control unit can stably read the power signal in the high-level state when reading the power signal next time, thereby performing pulse operation and improving the working reliability of the matching circuit.
In one possible example, the read control unit reads the power supply signal from the storage control unit every third preset time interval; the second preset time length is not less than the preset time length with a larger numerical value in the third preset time length and the fourth preset time length, and the fourth preset time length is the device operation time length from the time when the reading control unit starts to read the power supply signal to the time when the reading control unit actually reads the power supply signal.
In a specific implementation, the reading control unit may periodically read the power signal from the storage control unit. The second preset duration can determine a value of the second preset duration according to a time interval of reading the power supply signal by the reading control unit each time and a period operation delay of reading the power supply signal by the storage control unit.
If the read cycle (i.e., the third preset time) of the read control unit reading the power signal is longer than the device operation delay (i.e., the fourth preset time) of the read control unit, the time period (i.e., the second preset time) for prolonging the writing of the power signal in the high level state is set to be not less than the read cycle (i.e., the third preset time). On the contrary, if the read cycle of the read control unit for reading the power signal is less than the device operation delay of the read control unit, the time period for extending the writing of the power signal in the high level state (the second preset time period) is set to be not less than the device operation delay of the read control unit (the fourth preset time period).
In specific implementation, the preset time length with a larger numerical value in the third preset time length and the fourth preset time length may be set to be not less than N times (N is a positive integer greater than 1, and a specific numerical value may be preset by a user) of the other preset time length, or the preset time length with the larger numerical value in the third preset time length and the fourth preset time length may be set to be not less than the preset time length with the larger numerical value in the third preset time length and the fourth preset time length only when the third preset time length and the fourth preset time length do not belong to the same order of magnitude, where the numerical value of N may be set as needed without specific limitation here. That is, when the difference between the third preset duration and the fourth preset duration is large, the delay caused by the duration with a smaller value is negligible, thereby simplifying the working strategy of the reading control unit. For example, the third predetermined duration is microseconds (
) And the fourth preset time is in the millisecond (ms) level, the second preset time is not less than the fourth preset time.
In addition, in a case where the third preset duration and the fourth preset duration are of the same magnitude and do not satisfy that the larger preset duration is not less than N times the smaller preset duration (for example, N is 9 and the fourth preset duration is 6 times the third preset duration), the second preset duration may be set to be not less than the sum of the third preset duration and the fourth preset duration.
As can be seen, in this example, in the case that the reading control unit reads the power signal from the storage control unit at intervals of the third preset duration, the second preset duration is not less than the preset duration with a larger numerical value among the third preset duration and the fourth preset duration, and the fourth preset duration is the device operation duration from the time when the reading control unit starts to read the power signal to the time when the reading control unit actually reads the power signal, which is beneficial to ensuring that the reading control unit stably reads the power signal in the high level state, and further improves the working reliability of the matching circuit.
Referring to fig. 7, fig. 7 is a schematic flowchart of another pulse signal processing method provided in this embodiment, which can be applied to the matching circuit shown in fig. 2, wherein the matching circuit includes the storage control unit and a read control unit, the storage control unit is configured to obtain a power signal from a power supply and write the power signal into an internal preset storage area, and the read control unit is configured to read the power signal stored in the preset storage area from the storage control unit and transmit the power signal to a load; the method comprises the following steps:
step 301, if a power signal including high level pulse information from the power supply is acquired, maintaining the power signal in the high level state written into the preset storage region within a second preset time period, where the second preset time period is not less than a time interval between a next time when the reading control unit reads the power signal and a current time.
It can be seen that, in the embodiment of the present application, when receiving a power signal including high level pulse information from a power supply, the storage control unit maintains writing of a high level state into the preset storage region within a second preset duration that is not less than a time interval between a next time when the reading control unit reads the power signal and a current time, that is, after receiving the power signal including the high level pulse information, the storage control unit extends a time when the high level pulse signal is written into the preset storage region, so that when the reading control unit reads the power signal from the preset storage region next time, the power signal in the high level state can still be accurately read, and reliability of operation of the matching circuit is improved.
In one possible example, the read control unit reads the power supply signal from the storage control unit every third preset time interval; the second preset time length is not less than the preset time length with a larger numerical value in the third preset time length and the fourth preset time length, and the fourth preset time length is the device operation time length from the time when the reading control unit starts to read the power supply signal to the time when the reading control unit actually reads the power supply signal.
As can be seen, in this example, in the case that the reading control unit reads the power signal from the storage control unit every third preset duration, the second preset duration is not less than the preset duration with a larger value of the third preset duration and the fourth preset duration, and the fourth preset duration is the device operation duration from the time when the reading control unit starts to read the power signal to the time when the reading control unit actually reads the power signal, which is beneficial to ensuring that the reading control unit stably reads the power signal in a high level state, and further improves the working reliability of the matching circuit.
In one possible example, the method further comprises: if the power supply signal which comprises the low-level pulse information and is from the power supply is obtained, detecting whether the duration time of the power supply signal which comprises the low-level pulse information is longer than a first preset time length; if not, maintaining the writing of the power supply signal in the high level state into the preset storage region; and if so, writing a power supply signal in a low level state into the preset storage region.
It can be seen that, in this example, when the storage control unit reads the power signal including the low-level pulse information, if the duration of the power signal including the low-level pulse information is longer than the first preset duration, the power signal in the low-level state is written into the preset storage area, which is beneficial to ensuring that the reading control unit can stably read the high-level pulse information when reading the power signal, and further improving the reliability of the operation of the matching circuit.
Referring to fig. 8, fig. 8 is a functional block diagram of a pulse signal processing apparatus according to an embodiment of the present disclosure; the pulse signal processing device 60 is applicable to a matching circuit as shown in fig. 2, wherein the matching circuit includes the storage control unit and a read control unit, the storage control unit is used for obtaining a power supply signal from a power supply and writing the power supply signal into an internal preset storage area, and the read control unit is used for reading the power supply signal stored in the preset storage area from the storage control unit and transmitting the power supply signal to a load; the pulse signal processing device 60 includes:
the detection module 601 is configured to detect whether a duration of a power signal including low-level pulse information is longer than a first preset duration if the power signal including the low-level pulse information from the power supply is acquired;
a first writing module 602, configured to maintain writing of a power signal in a high level state into the preset storage area if the power signal is not written into the preset storage area;
a second writing module 603, configured to write a power signal in a low level state into the preset storage region if the power signal is in the low level state.
In one possible example, the pulse signal processing device 60 is further configured to: and if a power signal including high-level pulse information from the power supply is acquired, maintaining the power signal in a high-level state written into the preset storage region within a second preset time length, wherein the second preset time length is not less than the time interval between the time when the reading control unit reads the power signal next time and the current moment.
In one possible example, the read control unit reads the power supply signal from the storage control unit every third preset time interval; the second preset time length is not less than the preset time length with a larger numerical value in the third preset time length and the fourth preset time length, and the fourth preset time length is the device operation time length from the time when the reading control unit starts to read the power supply signal to the time when the reading control unit actually reads the power supply signal.
Referring to fig. 9, fig. 9 is a functional block diagram of another pulse signal processing apparatus according to an embodiment of the present disclosure; the pulse signal processing device 70 is applicable to a matching circuit as shown in fig. 2, wherein the matching circuit includes the storage control unit and a read control unit, the storage control unit is used for obtaining a power supply signal from a power supply and writing the power supply signal into an internal preset storage area, and the read control unit is used for reading the power supply signal stored in the preset storage area from the storage control unit and transmitting the power supply signal to a load; the pulse signal processing device 70 includes:
the writing module 701 is configured to maintain the power signal in the high level state written into the preset storage region within a second preset time period if the power signal including the high level pulse information from the power supply is acquired, where the second preset time period is not less than a time interval between a next time when the reading control unit reads the power signal and a current time.
In one possible example, the read control unit reads the power supply signal from the storage control unit every third preset time interval; the second preset time length is not less than the preset time length with a larger numerical value in the third preset time length and the fourth preset time length, and the fourth preset time length is the device operation time length from the time when the reading control unit starts to read the power supply signal to the time when the reading control unit actually reads the power supply signal.
In one possible example, the pulse signal processing device 70 is further configured to: if the power supply signal which comprises the low-level pulse information and is from the power supply is obtained, detecting whether the duration time of the power supply signal which comprises the low-level pulse information is longer than a first preset time length; if not, maintaining the writing of the power supply signal in the high level state into the preset storage region; and if so, writing a power supply signal in a low level state into the preset storage region.
All relevant contents of each scene related to the method embodiment may be referred to the functional description of the corresponding functional module, and are not described herein again. The pulse signal processing apparatus 60 can perform the steps performed by the storage control unit in the pulse signal processing method shown in fig. 3. The pulse signal processing apparatus 70 can perform the steps performed by the storage control unit in the pulse signal processing method shown in fig. 7.
It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
In the several embodiments provided in the present application, it should be understood that the disclosed method, apparatus and system may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative; for example, the division of the modules is only a logic function division, and there may be another division manner in actual implementation; for example, multiple modules or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or modules, and may be in an electrical, mechanical or other form.
The modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical modules, may be located in one position, or may be distributed on a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
In addition, functional modules in the embodiments of the present invention may be integrated into one processing module, or each module may be physically included alone, or two or more modules may be integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a mode of hardware and a software functional module.
Finally, it should be emphasized that the present application is not limited to the above-mentioned embodiments, but only the preferred embodiments of the application are described above, and the application is not limited thereto, and any modifications, equivalents, improvements and the like made within the spirit and principle of the application should be included in the protection scope of the application.
Claims (10)
1. The pulse signal processing method is characterized in that the pulse signal processing method is applied to a storage control unit of a matching circuit, the matching circuit comprises the storage control unit and a reading control unit, the storage control unit is used for acquiring a power supply signal from a power supply and writing the power supply signal into an internal preset storage area, and the reading control unit is used for reading the power supply signal stored in the preset storage area from the storage control unit and transmitting the power supply signal to a load; the method comprises the following steps:
if the power supply signal which comprises the low-level pulse information and is from the power supply is obtained, detecting whether the duration time of the power supply signal which comprises the low-level pulse information is longer than a first preset time length;
if not, maintaining the writing of the power supply signal in the high level state into the preset storage region;
and if so, writing a power supply signal in a low level state into the preset storage region.
2. The method of claim 1, further comprising:
and if a power signal including high-level pulse information from the power supply is acquired, maintaining the power signal in a high-level state written into the preset storage region within a second preset time length, wherein the second preset time length is not less than the time interval between the time when the reading control unit reads the power signal next time and the current moment.
3. The method of claim 2, wherein the read control unit reads the power signal from the storage control unit every third preset duration; the second preset time length is not less than the preset time length with a larger numerical value in the third preset time length and the fourth preset time length, and the fourth preset time length is the device operation time length from the time when the reading control unit starts to read the power supply signal to the time when the reading control unit actually reads the power supply signal.
4. The pulse signal processing method is characterized by being applied to a storage control unit of a matching circuit, wherein the matching circuit comprises the storage control unit and a reading control unit, the storage control unit is used for acquiring a power supply signal from a power supply and storing the power supply signal in an internal preset storage area, and the reading control unit is used for reading the power supply signal stored in the preset storage area from the storage control unit and transmitting the power supply signal to a load; the method comprises the following steps:
and if a power supply signal including high-level pulse information from the power supply is acquired, maintaining the power supply signal in the high-level state written into the preset storage region within a second preset time length, wherein the second preset time length is not less than the time interval between the next time when the reading control unit reads the power supply signal and the current moment.
5. The method of claim 4, wherein the read control unit reads the power signal from the storage control unit every third preset duration; the second preset time length is not less than the preset time length with a larger numerical value in the third preset time length and the fourth preset time length, and the fourth preset time length is the device operation time length from the time when the reading control unit starts to read the power supply signal to the time when the reading control unit actually reads the power supply signal.
6. The method according to claim 4 or 5, characterized in that the method further comprises:
if the power supply signal which comprises the low-level pulse information and is from the power supply is obtained, detecting whether the duration time of the power supply signal which comprises the low-level pulse information is longer than a first preset time length;
if not, maintaining the writing of the power supply signal in the high level state into the preset storage region;
and if so, writing a power supply signal in a low level state into the preset storage region.
7. The pulse signal processing device is characterized by being applied to a storage control unit of a matching circuit, wherein the matching circuit comprises the storage control unit and a reading control unit, the storage control unit is used for acquiring a power supply signal from a power supply and storing the power supply signal in an internal preset storage area, and the reading control unit is used for reading the power supply signal stored in the preset storage area from the storage control unit and transmitting the power supply signal to a load; the device comprises:
the detection module is used for detecting whether the duration time of the power supply signal containing the low-level pulse information is longer than a first preset time length or not if the power supply signal containing the low-level pulse information from the power supply is obtained;
the first writing module is used for maintaining the writing of the power supply signal in the high level state into the preset storage area if the power supply signal is not written into the preset storage area;
and the second writing module is used for writing the power supply signal in the low level state into the preset storage region if the power supply signal is in the low level state.
8. The pulse signal processing device is characterized by being applied to a storage control unit of a matching circuit, wherein the matching circuit comprises the storage control unit and a reading control unit, the storage control unit is used for acquiring a power supply signal from a power supply and storing the power supply signal in an internal preset storage area, and the reading control unit is used for reading the power supply signal stored in the preset storage area from the storage control unit and transmitting the power supply signal to a load; the device comprises:
and the writing module is used for maintaining the power supply signal in the high level state written into the preset storage region within a second preset time length if the power supply signal including the high level pulse information from the power supply is obtained, wherein the second preset time length is not less than the time interval between the next time the reading control unit reads the power supply signal and the current time.
9. A matching circuit is characterized by comprising a storage control unit and a reading control unit, wherein the storage control unit is electrically connected with the reading control unit;
the storage control unit is used for detecting whether the duration time of the power supply signal containing the low-level pulse information is longer than a first preset time length or not if the power supply signal containing the low-level pulse information from the power supply is obtained; if not, maintaining the writing of the power supply signal in the high level state into the preset storage area in the storage control unit; if so, writing a power supply signal in a low level state into the preset storage region; the reading control unit is used for reading the power supply signal stored in the preset storage area from the storage control unit and transmitting the power supply signal to a load.
10. A matching circuit is characterized by comprising a storage control unit and a reading control unit, wherein the storage control unit is electrically connected with the reading control unit;
the storage control unit is used for maintaining a power supply signal in a high level state written into a preset storage area in the storage control unit within a second preset time length if the power supply signal including high level pulse information from a power supply is acquired, wherein the second preset time length is not less than the time interval between the next time the power supply signal is read by the reading control unit and the current time; the reading control unit is used for reading the power supply signal stored in the preset storage area from the storage control unit and transmitting the power supply signal to a load.
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| CN202211523627.6A CN115603713B (en) | 2022-12-01 | 2022-12-01 | Pulse signal processing method and device and matching circuit |
| PCT/CN2023/127256 WO2024114200A1 (en) | 2022-12-01 | 2023-10-27 | Pulse signal processing method and apparatus, and matching circuit |
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| CN202211523627.6A CN115603713B (en) | 2022-12-01 | 2022-12-01 | Pulse signal processing method and device and matching circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024114200A1 (en) * | 2022-12-01 | 2024-06-06 | 深圳市恒运昌真空技术股份有限公司 | Pulse signal processing method and apparatus, and matching circuit |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030042955A1 (en) * | 2001-08-30 | 2003-03-06 | Kabushiki Kaisha Toshiba | Electronic circuit and semiconductor storage device |
| CN101075479A (en) * | 2006-05-18 | 2007-11-21 | 富士通株式会社 | Semiconductor memory device with reduced current consumption |
| CN102281051A (en) * | 2010-06-09 | 2011-12-14 | 海力士半导体有限公司 | Data input circuit |
| CN107170477A (en) * | 2016-03-08 | 2017-09-15 | 东芝存储器株式会社 | Semiconductor storage |
| CN111863105A (en) * | 2019-04-24 | 2020-10-30 | 长鑫存储技术有限公司 | Memory cell detection method and memory detection method |
| CN114047951A (en) * | 2021-11-08 | 2022-02-15 | 武汉威士登智能控制技术有限公司 | Pulse uniformity control algorithm |
| CN114765039A (en) * | 2021-01-15 | 2022-07-19 | 长鑫存储技术有限公司 | Method for detecting self-refreshing frequency |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4165491A (en) * | 1976-11-08 | 1979-08-21 | Sperry Rand Corporation | Circuit for detecting zero crossing points for data signal |
| JPH10285940A (en) * | 1997-04-04 | 1998-10-23 | Hitachi Ltd | Power converter controller |
| CN104935309A (en) * | 2014-03-18 | 2015-09-23 | 宝山钢铁股份有限公司 | Pulse distribution system with high anti-interference capability, and distribution method therefor |
| CN109088621B (en) * | 2018-07-27 | 2022-07-05 | 天津经纬恒润科技有限公司 | Signal filtering method and device |
| CN113707078B (en) * | 2019-08-14 | 2024-02-27 | 酷矽半导体科技(上海)有限公司 | Driving device, display control chip, display device and display control method |
| CN113298033A (en) * | 2021-06-17 | 2021-08-24 | 麦克方程(北京)科技有限责任公司 | Signal processing method and device, electronic equipment and readable storage medium |
| CN115603713B (en) * | 2022-12-01 | 2023-04-04 | 深圳市恒运昌真空技术有限公司 | Pulse signal processing method and device and matching circuit |
-
2022
- 2022-12-01 CN CN202211523627.6A patent/CN115603713B/en active Active
-
2023
- 2023-10-27 WO PCT/CN2023/127256 patent/WO2024114200A1/en unknown
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030042955A1 (en) * | 2001-08-30 | 2003-03-06 | Kabushiki Kaisha Toshiba | Electronic circuit and semiconductor storage device |
| CN101075479A (en) * | 2006-05-18 | 2007-11-21 | 富士通株式会社 | Semiconductor memory device with reduced current consumption |
| CN102281051A (en) * | 2010-06-09 | 2011-12-14 | 海力士半导体有限公司 | Data input circuit |
| CN107170477A (en) * | 2016-03-08 | 2017-09-15 | 东芝存储器株式会社 | Semiconductor storage |
| CN111863105A (en) * | 2019-04-24 | 2020-10-30 | 长鑫存储技术有限公司 | Memory cell detection method and memory detection method |
| CN114765039A (en) * | 2021-01-15 | 2022-07-19 | 长鑫存储技术有限公司 | Method for detecting self-refreshing frequency |
| CN114047951A (en) * | 2021-11-08 | 2022-02-15 | 武汉威士登智能控制技术有限公司 | Pulse uniformity control algorithm |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024114200A1 (en) * | 2022-12-01 | 2024-06-06 | 深圳市恒运昌真空技术股份有限公司 | Pulse signal processing method and apparatus, and matching circuit |
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|---|---|
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| CN115603713B (en) | 2023-04-04 |
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Address after: 518102 Room 101, 201, 301, Building B, Functional Support Area, Taohuayuan Zhichuang Town, Tiegang Community, Xixiang Street, Baoan District, Shenzhen, Guangdong Province Patentee after: Shenzhen Hengyunchang Vacuum Technology Co.,Ltd. Address before: 518102 Room 101, 201, 301, Building B, Functional Support Area, Taohuayuan Zhichuang Town, Tiegang Community, Xixiang Street, Baoan District, Shenzhen, Guangdong Province Patentee before: SHENZHEN HENGYUNCHANG VACUUM TECHNOLOGY CO.,LTD. |