CN113298033A - Signal processing method and device, electronic equipment and readable storage medium - Google Patents
Signal processing method and device, electronic equipment and readable storage medium Download PDFInfo
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Abstract
The application provides a signal processing method, a signal processing device, an electronic device and a readable storage medium, and relates to the field of signal processing. The method comprises the following steps: determining a target level signal from the received input level signals, wherein the target level signal is a level signal in a preset observation window in the input level signals, and the input level signals comprise a high level and/or a low level; when the target level signal has a high level and the accumulated duration of the high levels in the target level signal is within a first preset duration range, determining that the target level signal includes a bit signal 0. In the scheme, the input level signal is observed by utilizing the preset observation window, so that the accumulated duration of the high level in the window can be detected, the bit signal is determined without acquiring the rising edge and the falling edge of the high level, the accuracy of bit signal identification is favorably improved, and the accuracy of bit signal identification due to noise influence is avoided.
Description
Technical Field
The present application relates to the field of signal processing, and in particular, to a signal processing method, an apparatus, an electronic device, and a readable storage medium.
Background
Electronic devices based on hardware-implemented data reception exist on the market, the hardware providing an upper layer communication interface for receiving data in bytes, and the software processing data frames organized in bytes. The data reception implemented by hardware is typically: the received level signal is converted into byte data, the level signal which needs to undergo continuous gradation during the conversion into a binary level, then the binary level is converted into a bit signal 0/1, and finally the bit signal 0/1 is converted into byte data. The binary level is a level signal including a high level and a low level. At present, in the process of converting binary level into bit signal, the accuracy of binary level conversion bit signal is easily affected by the noise in binary level, so that the converted byte data has errors.
Disclosure of Invention
An object of the embodiments of the present application is to provide a signal processing method, a signal processing apparatus, an electronic device, and a readable storage medium, which can improve the accuracy of binary level conversion bit signals and improve the accuracy and reliability of byte data obtained based on bit signal conversion.
In order to achieve the above object, embodiments of the present application are implemented as follows:
in a first aspect, an embodiment of the present application provides a signal processing method, where the method includes:
determining a target level signal from received input level signals, wherein the target level signal is a level signal in a preset observation window in the input level signals, and the input level signals comprise a high level and/or a low level;
when the target level signal has a high level and the accumulated duration of the high level in the target level signal is within a first preset duration range, determining that the target level signal comprises a bit signal 0.
In the above embodiment, the input level signal is observed through the preset observation window, so that the accumulated duration of the high level in the window can be detected, the bit signal is determined without acquiring the rising edge and the falling edge of the high level, the accuracy of bit signal identification is improved, and the accuracy of bit signal identification due to noise influence is avoided.
With reference to the first aspect, in some optional embodiments, the method further comprises:
when the target level signals are all low level, or when the target level signals have high level and the accumulated duration of the high level in the target level signals is not within the first preset duration range, determining that the target level signals comprise bit signals 1 or idle signals.
In the above embodiment, in the preset observation window, the target level signal whose accumulated duration of the low level or the high level is not within the first preset duration range may be determined as the bit signal 1 or the idle signal, and thus, the influence of the high level noise suddenly appearing in the low level signal on the identification bit signal may be eliminated, thereby improving the accuracy of bit signal identification.
With reference to the first aspect, in some optional embodiments, determining that the target level signal includes a bit signal 1 or an idle signal includes:
determining a first time interval between the target level signal and a first bit signal 0 from the input level signals, wherein the first bit signal 0 is a bit signal 0 which is before the target level signal and is closest to the time interval of the target level signal in the input level signals;
when the first time interval is greater than or equal to a second preset time length, determining that the target level signal comprises the idle signal, wherein the second preset time length is greater than the maximum value in the first preset time length range;
when the target level signal is between the first bit signal 0 and a second bit signal 0, and a second time interval between the first bit signal 0 and the second bit signal 0 is less than the second preset time length, determining that the target level signal includes the bit signal 1, and the second bit signal 0 is a first bit signal 0 after the first bit signal 0 in the input level signal.
In the above-described embodiment, the bit signal 1 generally appears along with the bit signal 0, and the idle signal is generally at the low level for a long period of time, so that, based on the electrical characteristics of the bit signal 1 and the idle signal, in combination with the appearance period of the bit signal 0, it is possible to quickly and accurately determine whether the target signal at the low level is the bit signal 1 or the idle signal.
With reference to the first aspect, in some optional embodiments, the method further comprises:
and converting the bit signal 0 and/or the bit signal 1 corresponding to the input level signal according to the input sequence of the bit signal 0 and the bit signal 1 and a preset decoding strategy to obtain byte data.
In the above-described embodiment, since the accuracy and reliability of converting the input level signal into the bit signal 0/1 are high, when the byte data is converted by the bit signal 0/1, the accuracy and reliability of the obtained byte data can be improved.
With reference to the first aspect, in some optional embodiments, the input level signal comprises a KNX protocol-based level signal;
the bit signal 0 comprises a high level signal lasting 35 microseconds first and a low level signal lasting 69 microseconds second;
the bit signal 1 is a low level signal lasting for 104 microseconds;
the observation time length corresponding to the preset observation window is any time length of more than or equal to 35 microseconds and less than or equal to 104 microseconds.
In the above embodiment, the observation duration of the preset observation window is between 35 microseconds and 104 microseconds, which is beneficial to observing the high-level part of the bit signal 0, and avoids that the high-level observation is missed or the duration of a single bit signal is exceeded, so as to influence the effectiveness of the counted high-level accumulated duration.
With reference to the first aspect, in some optional embodiments, the first preset duration range is greater than or equal to 20 microseconds and less than or equal to the observation duration.
In a second aspect, the present application also provides a signal processing apparatus, the apparatus comprising:
the device comprises a first determining unit, a second determining unit and a control unit, wherein the first determining unit is used for determining a target level signal from received input level signals, the target level signal is a level signal in a preset observation window in the input level signals, and the input level signals comprise high levels and/or low levels;
and the second determining unit is used for determining that the target level signal comprises a bit signal 0 when the target level signal has a high level and the accumulated duration of the high level in the target level signal is within a first preset duration range.
With reference to the second aspect, in some optional embodiments, the second determining unit is further configured to:
when the target level signals are all low level, or when the target level signals have high level and the accumulated duration of the high level in the target level signals is not within the first preset duration range, determining that the target level signals comprise bit signals 1 or idle signals.
In a third aspect, the present application further provides an electronic device, which includes a processor and a memory coupled to each other, wherein the memory stores a computer program, and when the computer program is executed by the processor, the electronic device is caused to perform the method described above.
In a fourth aspect, the present application also provides a computer-readable storage medium having stored thereon a computer program which, when run on a computer, causes the computer to perform the method described above.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1a is a schematic waveform diagram of a bit signal 0 according to an embodiment of the present disclosure.
Fig. 1b is a schematic waveform diagram of a noisy bit signal 0 according to an embodiment of the present disclosure.
Fig. 1c is a second schematic waveform diagram of a noisy bit signal 0 according to an embodiment of the present disclosure.
Fig. 2a is a schematic waveform diagram of a bit signal 1 according to an embodiment of the present disclosure.
Fig. 2b is a waveform diagram of a bit signal 1 with noise according to an embodiment of the present disclosure.
Fig. 3 is a timing diagram of an input level signal according to an embodiment of the present disclosure.
Fig. 4 is a schematic flowchart of a signal processing method according to an embodiment of the present application.
Fig. 5 is a schematic flowchart of a signal processing apparatus according to an embodiment of the present application.
Icon: 200-signal processing means; 210-a first determination unit; 220-second determination unit.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. It should be noted that the terms "first," "second," and the like are used merely to distinguish one description from another, and are not intended to indicate or imply relative importance.
The application provides an electronic device which can receive data based on hardware. The electronic device may receive input level signals transmitted by other devices or modules and then convert the input level signals into bit signals 0/1. The input level signal is other equipment or modules, and data to be transmitted is encoded into a level signal formed by high and low levels through a preset encoding strategy. Other devices or modules are devices for sending input level signals to the electronic device, and may be flexibly determined according to actual situations, and are not specifically limited herein.
The electronic device may convert the bit signal 0/1 converted by the electronic device into byte data according to a decoding policy corresponding to a preset encoding policy. In other embodiments, the bit signal 0/1 may be sent by the electronic device to a decoding device that converts the bit signal 0/1 into byte data. The preset encoding strategy and the decoding strategy may be flexibly determined according to actual situations, and are well known to those skilled in the art and will not be described herein again.
If no error occurs in the transmission and decoding process of the input level signal, the input level signal is converted and decoded, and the obtained byte data is the same as the data to be transmitted.
Referring to fig. 1a, 1b, 2a, 2b and 3 in combination, in the level signal based on KNX protocol (KNX protocol is abbreviated as Konnex protocol, and is a global home and building control standard), the normal bit signal 0 is as shown in fig. 1a, that is, the bit signal 0 is a high level lasting 35 microseconds (symbol us) at the beginning, and then a low level lasting 69 microseconds. During the generation or transmission of the bit signal 0, noise may exist, and as shown in fig. 1b, the noise is at a low level with a short duration in a high level of 35 microseconds; or the noise appears as a high level with a short duration in a low level of 69 microseconds.
The normal bit signal 1 is low for 104 microseconds as shown in fig. 2 a. The noisy bit signal 1 is shown in fig. 2b, i.e. the high level with a short duration, which appears in the low level of 104 microseconds, is a noisy signal.
As shown in fig. 3, the waveform timing chart of the input level signal received by the electronic device understandably includes level signals corresponding to bit signal 0 and bit signal 1.
The order of the bit signal 0 and the bit signal 1 is determined according to actual conditions, and is not limited to that shown in fig. 3. In addition, the waveform diagram of the bit signal 0 with noise is not limited to that shown in fig. 1b, the waveform diagram of the bit signal 1 with noise is not limited to that shown in fig. 2b, and the position and duration of the noise in the bit signal are determined according to actual conditions, and are not particularly limited herein.
In this embodiment, the electronic device may include a processing module and a storage module. The storage module stores a computer program which, when executed by the processing module, enables the electronic device to perform the steps of the method described below.
The electronic device is a device having a data communication function, and may be determined according to actual situations, and is not particularly limited herein. Understandably, the electronic device may also comprise other modules, for example, the electronic device may also comprise a communication module for transmitting data.
Referring to fig. 4, the present application provides a signal processing method, which can be applied to the electronic device described above, and is executed by the electronic device or implements the steps of the method. The method may comprise the steps of:
step S110, determining a target level signal from received input level signals, wherein the target level signal is a level signal in a preset observation window in the input level signals, and the input level signals comprise a high level and/or a low level;
step S120, when the target level signal has a high level and the accumulated duration of the high level in the target level signal is within a first preset duration range, determining that the target level signal includes a bit signal 0.
In the above embodiment, the input level signal is observed through the preset observation window, so that the accumulated duration of the high level in the window can be detected, the bit signal is determined without acquiring the rising edge and the falling edge of the high level, the accuracy of bit signal identification is improved, and the accuracy of bit signal identification due to noise influence is avoided.
The individual steps of the process are explained in detail below, as follows:
in step S110, an input level signal is determined according to data to be transmitted and a preset encoding strategy. For example, the input level signal may be a level signal based on the KNX protocol described above, or a level signal having similar electrical characteristics to the level signal of the KNX protocol. The type of input level signal is not particularly limited here.
The data to be transmitted may be flexibly determined according to actual situations, including but not limited to a physical address of the source device, data collected by the sensor (e.g., temperature data collected by the temperature sensor), and is not limited specifically herein. The source device may be a host device or an upper computer accessing the sensor, and is configured to output data collected by the sensor to the electronic device.
Illustratively, a partial timing diagram of the input level signal may be as shown in fig. 3. In the input level signal shown in fig. 3, a noise signal is included.
In this embodiment, the electronic device may perform observation processing on the received input level signal through a preset observation window to determine a target level signal. The input level signal in the preset observation window is the target level signal, as shown in fig. 3.
The electronic device may periodically perform observation processing on the input level signal through the preset observation windows at a preset period to obtain a target level signal corresponding to each preset observation window. The preset period may be a duration of 1 bit signal. For example, if the duration of one bit signal is 104 microseconds, the electronic device may use 104 microseconds as a time interval between two adjacent observations, where the time interval refers to a time interval between start times of two preset observation windows, so that the input level signal of each preset observation window may be identified, and missing detection is avoided.
In step S120, the electronic device may determine whether the target level signal is the bit signal 0 based on the electrical characteristics of the target level signal in the preset window. The first preset duration range may be determined according to actual conditions.
For example, when the input level signal is a level signal based on the KNX protocol, the bit signal 0 includes a high level signal lasting 35 microseconds first and a low level signal lasting 69 microseconds later. Bit signal 1 is a low level signal lasting 104 microseconds. At this time, the observation time duration corresponding to the preset observation window may be any time duration greater than or equal to 35 microseconds and less than or equal to 104 microseconds. The first preset duration range may be greater than or equal to 20 microseconds and less than or equal to the observation duration.
For example, the first preset duration may range from 20 microseconds to 75 microseconds. When the accumulated duration of the high level in the preset observation window is in the range of 20 microseconds to 75 microseconds, it is determined that the input level signal of the preset observation window includes a bit signal 0, the starting time of the bit signal 0 is the time of the first rising edge in the preset observation window, and the ending time of the bit signal 0 is the time corresponding to 104 microseconds after the starting time.
In the above embodiment, the observation duration of the preset observation window is between 35 microseconds and 104 microseconds, which is beneficial to observing the high-level part of the bit signal 0, and avoids that the high-level observation is missed or the duration of a single bit signal is exceeded, so as to influence the effectiveness of the counted high-level accumulated duration.
In this embodiment, the method may further include: when the target level signals are all low level, or when the target level signals have high level and the accumulated duration of the high level in the target level signals is not within the first preset duration range, determining that the target level signals comprise bit signals 1 or idle signals.
Understandably, in the preset observation window, the electronic device may determine a target level signal, the accumulated duration of which is at the high level is not within the first preset duration range, as a bit signal 1 or an idle signal, or determine a target level signal, which is continuously at the low level, as a bit signal 1 or an idle signal. Therefore, the accuracy of identifying the bit signal 1 or the idle signal can be prevented from being influenced by high-level noise which suddenly appears in the low-level signal, so that the accuracy of identifying the bit signal is improved, and the influence of noise on identifying the bit signal is filtered.
Referring to fig. 1c, if the coordinate O-TV is established by time-level, the T-axis represents time, and the V-axis represents level, the above-mentioned detection method for determining the bit signal 0, the bit signal 1 and the idle signal by presetting the high level accumulation duration in the observation window and filtering the interference of noise is essentially area integration, which may be called "area filtering algorithm". That is, the total duration of the high level may be replaced with the total area of the region on the reference line where the waveform of the high level projects the low level, as shown in fig. 1 c.
In this embodiment, the idle signal and the bit signal 1 are both normally at a sustained low level, except that the bit signal 1 is present along with the bit signal 0, and the idle signal is normally at a low level for a longer duration. Based on this, it can be determined whether the level signal of the non-bit signal 0 is the bit signal 1 or the idle signal according to the duration of the sustained low level. For example, determining that the target level signal includes a bit signal 1 or an idle signal may include:
determining a first time interval between the target level signal and a first bit signal 0 from the input level signals, wherein the first bit signal 0 is a bit signal 0 which is before the target level signal and is closest to the time interval of the target level signal in the input level signals;
when the first time interval is greater than or equal to a second preset time length, determining that the target level signal comprises the idle signal, wherein the second preset time length is greater than the maximum value in the first preset time length range;
when the target level signal is between the first bit signal 0 and a second bit signal 0, and a second time interval between the first bit signal 0 and the second bit signal 0 is less than the second preset time length, determining that the target level signal includes the bit signal 1, and the second bit signal 0 is a first bit signal 0 after the first bit signal 0 in the input level signal.
The first bit signal 0 may be understood as a first bit signal 0 before the current target level signal, the second bit signal 0 may be understood as a first bit signal 0 after the current target level signal, and the second preset time duration may be set according to practical situations, for example, the second preset time duration may be a time duration longer than a single bit signal, such as 1 millisecond, 10 milliseconds, and the like.
Understandably, when it is determined that the current target level signal is not the bit signal 0 and it cannot be directly determined that the target level signal is the bit signal 1 or the idle signal at this time, the bit signal detection is continued to be performed on the level after the target level signal, and if the bit signal 0 exists within a second preset time period after the target level signal, it may be determined that the target level signal is the bit signal 1. And if the bit signal 0 does not exist within a second preset time period after the target level signal and is still at a continuous low level, determining that the target level signal is an idle signal.
Referring to fig. 3 again, for example, if the input level signal is a level signal based on the KNX protocol, the first predetermined duration range may be 20 microseconds to 75 microseconds, the observation duration of the predetermined observation window is 104 microseconds, and the second predetermined duration range may be 1 millisecond. At this time, through presetting an observation window, it can be determined that the a section of the input level signal is a bit signal 0, and then observing and identifying the B section level signal, because the high level of the B section level signal is not within the first preset duration range (20 microseconds to 75 microseconds), the B section level signal is a non-bit signal 0, and it is necessary to continue to detect the level after the B section level signal. When the C-segment level signal is detected through the preset observation window, it may be determined that the duration of the high level (assumed to be 30 microseconds) in the preset observation window is within 20 microseconds to 75 microseconds, and therefore, the C-segment level signal may be determined as the bit signal 0, and then it may be determined that the B-segment level signal is the bit signal 1 based on A, C segments that are both the bit signal 0 and the interval duration with the B-segment level signal is less than 1 millisecond, where a time point of the A, B, C-segment level signal may be determined based on a rising edge of the preset observation window in the a-segment, and then 104 microseconds are gradually increased based on the time of the rising edge, and thus a single-segment level signal such as B, C may be obtained.
In the above embodiment, the bit signal 1 usually appears along with the bit signal 0, and the idle signal is usually at the low level for a long time, so based on the electrical characteristics of the bit signal 1 and the idle signal, in combination with the appearance period of the bit signal 0, the influence of noise on the bit signal identification can be filtered, the target signal at the low level is determined to be the bit signal 1 or the idle signal quickly and accurately, and the processing flow of the bit signal identification is simplified.
In this embodiment, the method may further include:
and converting the bit signal 0 and/or the bit signal 1 corresponding to the input level signal according to the input sequence of the bit signal 0 and the bit signal 1 and a preset decoding strategy to obtain byte data.
The preset decoding strategy can be determined according to actual conditions. In the present embodiment, since the accuracy and reliability of converting the input level signal into the bit signal 0/1 are high, when the byte data is converted by the highly reliable bit signal 0/1, the accuracy and reliability of the obtained byte data can be improved.
Referring to fig. 5, an embodiment of the present application further provides a signal processing apparatus 200, which can be applied to the electronic device described above for executing the steps of the method. The signal processing apparatus 200 includes at least one software functional module which can be stored in a memory module in the form of software or Firmware (Firmware) or solidified in an Operating System (OS) of the electronic device. The processing module is used for executing executable modules stored in the storage module, such as software functional modules and computer programs included in the signal processing apparatus 200.
The signal processing apparatus 200 may include a first determining unit 210 and a second determining unit 220, and may perform the following operations:
a first determining unit 210, configured to determine a target level signal from received input level signals, where the target level signal is a level signal within a preset observation window in the input level signals, and the input level signals include a high level and/or a low level;
a second determining unit 220, configured to determine that the target level signal includes a bit signal 0 when the target level signal has a high level and an accumulated duration of the high level in the target level signal is within a first preset duration range.
Optionally, the second determining unit 220 is further configured to: when the target level signals are all low level, or when the target level signals have high level and the accumulated duration of the high level in the target level signals is not within the first preset duration range, determining that the target level signals comprise bit signals 1 or idle signals.
Optionally, the second determining unit 220 is further configured to:
determining a first time interval between the target level signal and a first bit signal 0 from the input level signals, wherein the first bit signal 0 is a bit signal 0 which is before the target level signal and is closest to the time interval of the target level signal in the input level signals;
when the first time interval is greater than or equal to a second preset time length, determining that the target level signal comprises the idle signal, wherein the second preset time length is greater than the maximum value in the first preset time length range;
when the target level signal is between the first bit signal 0 and a second bit signal 0, and a second time interval between the first bit signal 0 and the second bit signal 0 is less than the second preset time length, determining that the target level signal includes the bit signal 1, and the second bit signal 0 is a first bit signal 0 after the first bit signal 0 in the input level signal.
Optionally, the signal processing apparatus 200 may further include a decoding unit, configured to convert the bit signal 0 and/or the bit signal 1 corresponding to the input level signal according to the input sequence of the bit signal 0 and the bit signal 1 and a preset decoding policy to obtain byte data.
In this embodiment, the processing module may be an integrated circuit chip having signal processing capability. The processing module may be a general purpose processor. For example, the processor may be a Central Processing Unit (CPU), a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component, and may implement or execute the methods, steps, and logic blocks disclosed in the embodiments of the present Application.
The memory module may be, but is not limited to, a random access memory, a read only memory, a programmable read only memory, an erasable programmable read only memory, an electrically erasable programmable read only memory, and the like. In this embodiment, the storage module may be configured to store a first preset duration range, a second preset duration, a preset observation window, and the like. Of course, the storage module may also be used to store a program, and the processing module executes the program after receiving the execution instruction.
It should be noted that, as will be clear to those skilled in the art, for convenience and brevity of description, the specific working process of the electronic device described above may refer to the corresponding process of each step in the foregoing method, and will not be described in detail herein.
The embodiment of the application also provides a computer readable storage medium. The computer-readable storage medium has stored therein a computer program which, when run on a computer, causes the computer to execute the signal processing method as described in the above embodiments.
From the above description of the embodiments, it is clear to those skilled in the art that the present application can be implemented by hardware, or by software plus a necessary general hardware platform, and based on such understanding, the technical solution of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a usb disk, a removable hard disk, etc.), and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the method described in the embodiments of the present application.
In summary, the present application provides a signal processing method, a signal processing apparatus, an electronic device, and a readable storage medium. The method comprises the following steps: determining a target level signal from the received input level signals, wherein the target level signal is a level signal in a preset observation window in the input level signals, and the input level signals comprise a high level and/or a low level; when the target level signal has a high level and the accumulated duration of the high levels in the target level signal is within a first preset duration range, determining that the target level signal includes a bit signal 0. In the scheme, the input level signal is observed by utilizing the preset observation window, so that the accumulated duration of the high level in the window can be detected, the bit signal is determined without acquiring the rising edge and the falling edge of the high level, the accuracy of bit signal identification is favorably improved, and the accuracy of bit signal identification due to noise influence is avoided.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus, system, and method may be implemented in other ways. The apparatus, system, and method embodiments described above are illustrative only, as the flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions. In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A method of signal processing, the method comprising:
determining a target level signal from received input level signals, wherein the target level signal is a level signal in a preset observation window in the input level signals, and the input level signals comprise a high level and/or a low level;
when the target level signal has a high level and the accumulated duration of the high level in the target level signal is within a first preset duration range, determining that the target level signal comprises a bit signal 0.
2. The method of claim 1, further comprising:
when the target level signals are all low level, or when the target level signals have high level and the accumulated duration of the high level in the target level signals is not within the first preset duration range, determining that the target level signals comprise bit signals 1 or idle signals.
3. The method of claim 2, wherein determining that the target level signal comprises a bit signal 1 or an idle signal comprises:
determining a first time interval between the target level signal and a first bit signal 0 from the input level signals, wherein the first bit signal 0 is a bit signal 0 which is before the target level signal and is closest to the time interval of the target level signal in the input level signals;
when the first time interval is greater than or equal to a second preset time length, determining that the target level signal comprises the idle signal, wherein the second preset time length is greater than the maximum value in the first preset time length range;
when the target level signal is between the first bit signal 0 and a second bit signal 0, and a second time interval between the first bit signal 0 and the second bit signal 0 is less than the second preset time length, determining that the target level signal includes the bit signal 1, and the second bit signal 0 is a first bit signal 0 after the first bit signal 0 in the input level signal.
4. The method of claim 2, further comprising:
and converting the bit signal 0 and/or the bit signal 1 corresponding to the input level signal according to the input sequence of the bit signal 0 and the bit signal 1 and a preset decoding strategy to obtain byte data.
5. The method of claim 2, wherein the input level signal comprises a KNX protocol based level signal;
the bit signal 0 comprises a high level signal lasting 35 microseconds first and a low level signal lasting 69 microseconds second;
the bit signal 1 is a low level signal lasting for 104 microseconds;
the observation time length corresponding to the preset observation window is any time length of more than or equal to 35 microseconds and less than or equal to 104 microseconds.
6. The method of claim 5, wherein the first predetermined time period range is greater than or equal to 20 microseconds and less than or equal to the observation time period.
7. A signal processing apparatus, characterized in that the apparatus comprises:
the device comprises a first determining unit, a second determining unit and a control unit, wherein the first determining unit is used for determining a target level signal from received input level signals, the target level signal is a level signal in a preset observation window in the input level signals, and the input level signals comprise high levels and/or low levels;
and the second determining unit is used for determining that the target level signal comprises a bit signal 0 when the target level signal has a high level and the accumulated duration of the high level in the target level signal is within a first preset duration range.
8. The apparatus of claim 7, wherein the second determining unit is further configured to:
when the target level signals are all low level, or when the target level signals have high level and the accumulated duration of the high level in the target level signals is not within the first preset duration range, determining that the target level signals comprise bit signals 1 or idle signals.
9. An electronic device, characterized in that the electronic device comprises a processor and a memory coupled to each other, the memory storing a computer program which, when executed by the processor, causes the electronic device to perform the method according to any of claims 1-6.
10. A computer-readable storage medium, in which a computer program is stored which, when run on a computer, causes the computer to carry out the method according to any one of claims 1-6.
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