CN113707078B - Driving device, display control chip, display device and display control method - Google Patents

Driving device, display control chip, display device and display control method Download PDF

Info

Publication number
CN113707078B
CN113707078B CN202111025175.4A CN202111025175A CN113707078B CN 113707078 B CN113707078 B CN 113707078B CN 202111025175 A CN202111025175 A CN 202111025175A CN 113707078 B CN113707078 B CN 113707078B
Authority
CN
China
Prior art keywords
data
pulse width
width modulation
constant current
light emitting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202111025175.4A
Other languages
Chinese (zh)
Other versions
CN113707078A (en
Inventor
费小泂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cool Silicon Semiconductor Technology Shanghai Co ltd
Original Assignee
Cool Silicon Semiconductor Technology Shanghai Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cool Silicon Semiconductor Technology Shanghai Co ltd filed Critical Cool Silicon Semiconductor Technology Shanghai Co ltd
Priority to CN202111025175.4A priority Critical patent/CN113707078B/en
Publication of CN113707078A publication Critical patent/CN113707078A/en
Application granted granted Critical
Publication of CN113707078B publication Critical patent/CN113707078B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/10—Controlling the intensity of the light
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/20—Controlling the colour of the light
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/32—Pulse-control circuits
    • H05B45/325—Pulse-width modulation [PWM]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/345—Current stabilisation; Maintaining constant current
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
    • H05B47/10—Controlling the light source
    • H05B47/16—Controlling the light source by timing means
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of El Displays (AREA)
  • Led Devices (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The invention relates to a driving device, a display control chip, a display device and a display control method. The driving device is used for driving the light emitting diode and comprises a pulse width modulation module, and the pulse width modulation module forms a corresponding pulse width modulation signal according to gray data matched with the light emitting diode. The pulse width modulation signal is used for driving the light emitting diode to perform display control, and the pulse width modulation module is provided with a counter and a data comparator. Triggering a counter to count by a clock signal and obtaining a count value; the count value is reordered according to the rule from low weight to high weight to obtain reverse order data; the pulse width modulation module sends the gray data and the reverse order data into the data comparator for comparison: the pulse width modulated signal has a valid logic value when the inverted data is lower than the gray data.

Description

Driving device, display control chip, display device and display control method
Technical Field
The present invention relates generally to the field of illuminated displays, and more particularly to providing corresponding driving devices and display control chips, and display devices and display control methods in illuminated display scenes containing solid state light emitting diode light sources.
Background
In the field of illuminated display, pulsed dimming is to change the time width of the diode on or off in a certain period of time and consider the current flowing through the diode during the on-lighting period of the light emitting diode to be a fixed value, thereby realizing a change in luminance. According to the Grassman law and the standard chromaticity diagram of the International luminous illumination Commission, reference color components of pixel points need to be distributed in a preset intensity range in an illumination and display system, and all colors which can be perceived by a vision system can be basically obtained by depending on gray level changes of primary colors and different brightness superposition. Because various core parameters such as working voltage and luminous efficiency of various primary color light-emitting diode light sources are different in industry, when primary colors are mixed, the light intensity ratio designed for each primary color light source is difficult to achieve in practical application, so that certain occasions must be compensated by adopting a gamma correction algorithm with a large ratio on software, typically, the brightness range of blue is obviously smaller than the brightness range of red light and green light, which requires more hardware resources and more complex circuits. It is necessary to design new driving schemes for primary light sources that allow flexible allocation of hardware limited resolution to primary colors and free allocation of the power duty cycle of the primary light sources.
Disclosure of Invention
The application designs a drive arrangement, drive multichannel emitting diode, includes:
the system comprises a plurality of pulse width modulation modules, a plurality of light emitting diodes and a plurality of light emitting diodes, wherein each pulse width modulation module forms a corresponding pulse width modulation signal according to gray data matched with one light emitting diode matched with the pulse width modulation module;
each path of constant current unit is connected with one path of light emitting diode in series;
whether any one light-emitting diode flows through constant current provided by a constant current unit connected in series or not is controlled by one pulse width modulation signal corresponding to the any one light-emitting diode;
the common cycle period of each path of pulse width modulation signal is divided into a plurality of sub-time periods, the effective logic value of each path of pulse width modulation signal is distributed in a corresponding sub-time period, and a plurality of paths of light emitting diodes are sequentially lighted in a time-sharing manner in the cycle period;
each sub-time period is distributed with a clock signal, and the number of the clock signals in each sub-time period is a preset value;
determining the time length of each sub-time period according to the number of clock signals distributed by each sub-time period and the clock signals in a clock counting mode;
The frequencies of the plurality of clock signals allocated for the plurality of sub-periods of each cycle period are set to be the same or different.
The driving device described above, wherein:
at least a plurality of light emitting diodes with three primary colors of red, green and blue are provided, the gray data of each light emitting diode is adjusted under the condition of mixed color of the three primary colors, and different colors are obtained by the change of the gray data matched with each light emitting diode.
The driving device described above, wherein:
the pulse width modulation modules are provided with a counter, the multi-bit counting data output by the counter comprises specified high-bit data and specified low-bit data, and the number of sub-time periods in each cycle period is determined by the bit number of the specified high-bit data;
the time length of each sub-time period is counted by a counter triggered by a clock signal matched with the sub-time period, and the preset value of the number of the clock signals in each sub-time period is determined by the bit number of the designated low-order data.
The driving device described above, wherein:
setting the bit number Z of the appointed high-order data and the bit number F of the appointed low-order data as natural numbers larger than zero;
the number of sub-periods per cycle period does not exceed 2 Z And the preset value in each sub-period is 2 F 。
The driving device described above, wherein:
the counter is configured with a data selector, a plurality of clock signals distributed for a plurality of sub-time periods are input to a plurality of data input ends of the data selector, and the appointed high-order data are regarded as channel selection signals of the data selector;
in each cycle period, the appointed low-order data triggers the appointed high-order data to carry once after each counting is full, and then triggers the data selector to switch and output different clock signals;
the different channel select signals map the different clock signals output by the data selector, thereby assigning a clock signal to each sub-period and for triggering the counter to count.
The driving device described above, wherein:
each pulse width modulation module is configured with a data comparator;
the appointed low-order data are reordered according to the rule that the weight is from low to high, and reverse order data are obtained;
in any sub-time period, the corresponding pulse width modulation module sends the gray data matched with one path of light emitting diode matched with the pulse width modulation module and the reverse data into the data comparator for comparison:
the pulse width modulated signal has a valid logic value when the inverted data is lower than the gray data.
The driving device described above, wherein:
each pulse width modulation module outputs a dithering signal with an effective logic value once every a plurality of cycle periods, so that the average value of the duty ratio of each path of pulse width modulation signal in the cycle periods is adjusted by the dithering signal;
the effective logic value of one pulse width modulation signal generated by each pulse width modulation module in a corresponding sub-time period is in discrete distribution, and when the jitter signal is output, any pulse width modulation module sets the last effective logic value in the pulse width modulation signals generated by the pulse width modulation module and immediately outputs the jitter signal.
The driving device described above, wherein:
the effective logic values of each pulse width modulation signal in a corresponding sub-period are arranged in a continuous manner; or alternatively
The effective logic values of each pulse width modulated signal within a corresponding one of the sub-periods are arranged in a decentralized manner.
The driving device described above, wherein:
each pulse width modulation module outputs a dithering signal with an effective logic value once every a plurality of cycle periods, and any pulse width modulation module outputs the dithering signal:
if the effective logic values of the pulse width modulation signals are arranged in a continuous mode, setting the effective logic values of the pulse width modulation signals generated by any pulse width modulation module and outputting jitter signals immediately after finishing; or alternatively
If the effective logic values of the pulse width modulation signals are distributed in a scattered mode, the last effective logic value in the pulse width modulation signals generated by any pulse width modulation module is set to output a jitter signal immediately after the last effective logic value is finished.
The driving device described above, wherein:
the LED driving circuit comprises a shunt module connected with a plurality of LEDs in parallel and used for stabilizing the input voltage supplied to the driving device;
the LED and constant current unit are coupled in series between the power input end and the potential reference end, and the shunt module is also coupled between the power input end and the potential reference end;
the shunt module comprises an adjustable parallel voltage reference circuit, wherein the cathode of the adjustable parallel voltage reference circuit is coupled to the power input end through a resistor or not, the anode of the adjustable parallel voltage reference circuit is coupled to the potential reference end, and a resistor voltage divider is arranged between the power input end and the potential reference end;
the reference terminal of the adjustable parallel type voltage reference circuit is coupled to the voltage dividing node of the resistor divider.
The driving device described above, wherein:
the first data transmission module is provided with a decoder and is used for decoding gray data from received communication data;
The driving device intercepts the communication data belonging to the first data transmission module from each frame of communication data, and then forwards the rest other communication data received by the driving device.
The driving device described above, wherein:
setting a constant current unit in a mode in which a supplied constant current is fixed; or alternatively
The programmable constant current unit is set in a mode that the supplied constant current can be regulated, and the driving device comprises a first data transmission module with a decoder, wherein the first data transmission module is used for decoding first current regulation data from received communication data, and the driving device regulates the magnitude of the constant current supplied by the constant current unit according to the first current regulation data.
The driving device described above, wherein:
providing multiple paths of constant current units, wherein each path of light emitting diode is connected with a corresponding path of constant current unit in series in a one-to-one mode, and when a path of pulse width modulation signal corresponding to any path of light emitting diode has an effective logic value, the any path of light emitting diode is lightened and the path of constant current unit connected in series is started; or alternatively
And each path of light emitting diodes is connected with the common constant current unit in series, and when one path of pulse width modulation signal corresponding to any path of light emitting diodes has an effective logic value, the common constant current unit is started, and any path of light emitting diodes are switched to be connected with the common constant current unit in series to be lightened.
The driving device described above, wherein:
the bypass module is connected with the multiple light emitting diodes in parallel, a result obtained by performing NOR logic operation on the multiple pulse width modulation signals is regarded as a control signal of the bypass module, and the bypass module is triggered to split the total input current of the driving device when the control signal has an effective logic value.
The driving device described above, wherein:
the load and one path of constant current unit of the bypass module are connected in series;
each path of light emitting diode and load are respectively provided with a constant current unit, when the pulse width modulation signal corresponding to any path of light emitting diode has an effective logic value, the constant current unit connected in series is started, and when the control signal has an effective logic value, the constant current unit connected in series is started; or alternatively
The multiple light emitting diodes and the load share a common constant current unit, when the pulse width modulation signal corresponding to any one light emitting diode has an effective logic value, the pulse width modulation signal is switched to be connected in series with the common constant current unit, and when the control signal has an effective logic value, the load is switched to be connected in series with the common constant current unit.
The driving device described above, wherein: the load comprises a light emitting diode or a non-light emitting diode or a resistor.
The driving device described above, wherein:
a current source module with a constant current source is arranged on a line for supplying power to the driving device and is used for maintaining the total input current of the driving device at a preset value;
the constant current source is set in a mode in which the output current is fixed or the programmable constant current source is set in a mode in which the output current is adjustable.
The driving device described above, wherein:
the second data transmission module configured by the current source module is provided with a decoder for decoding second current regulation data from communication data received by the current source module;
the current source module adjusts the output current of the programmable constant current source according to the second current adjustment data.
The driving device described above, wherein:
as the second current regulation data received by the current source module is refreshed, the total input current is updated from a predetermined value corresponding to the second current regulation data before the refresh to a predetermined value corresponding to the second current regulation data after the refresh.
The driving device described above, wherein:
the current source module is used for forwarding the rest other communication data received by the current source module after intercepting the communication data belonging to the current source module from each frame of communication data by the second data transmission module.
The driving device described above, wherein:
The driving device further comprises a first data transmission module with a decoder, wherein the first data transmission module is used for decoding gray data from received communication data and decoding first current regulation data from the communication data, and the driving device regulates the magnitude of constant current provided by the programmable constant current unit according to the first current regulation data;
setting the constant current provided by the constant current unit by using first current regulation data sent to the driving device and setting the output current of the constant current source by using second current regulation data sent to the current source module in each frame of communication data;
when the first current regulation data and the second current regulation data are set, the current flowing through any one light emitting diode is limited not to exceed the output current of a constant current source in the current source module.
The driving device described above, wherein:
the result of the NOR logic operation of the multi-path pulse width modulation signal is regarded as the control signal of a bypass module connected with the multi-path light emitting diode in parallel, and when the control signal has an effective logic value, the bypass module is triggered to be conducted and the shunt is implemented;
the shunt current when the bypass module shunts is determined by a constant current unit, and the shunt current is not more than the output current of the constant current source in the current source module when the first current regulation data and the second current regulation data are set.
The application relates to a display control chip, comprising the driving device.
The application relates to a display control chip, drive multichannel emitting diode, include:
the system comprises a plurality of pulse width modulation modules, a plurality of light emitting diodes and a plurality of light emitting diodes, wherein each pulse width modulation module forms a corresponding pulse width modulation signal according to gray data matched with one light emitting diode matched with the pulse width modulation module;
each path of pulse width modulation signal is used for driving one path of light emitting diode corresponding to the pulse width modulation signal to perform display control;
the common cycle period of each path of pulse width modulation signal is divided into a plurality of sub-time periods, the effective logic value of each path of pulse width modulation signal is distributed in a corresponding sub-time period, and a plurality of paths of light emitting diodes are sequentially lighted in a time-sharing manner in the cycle period;
each sub-time period is distributed with a clock signal, and the number of the clock signals in each sub-time period is a preset value;
the time length of each sub-time period is counted by triggering a counter through a clock signal matched with the sub-time period;
the frequencies of the plurality of clock signals allocated for the plurality of sub-periods of each cycle period are set to be the same or different.
The display device of the driving apparatus includes:
The multi-stage driving device is set into a cascade connection mode, each stage of driving device intercepts communication data belonging to each frame of communication data through a first data transmission module of the multi-stage driving device, and forwards the received rest of other communication data to a rear-stage driving device which is in cascade connection with the multi-stage driving device, so that each stage of driving device captures gray data belonging to the stage;
each level driving device drives a plurality of light emitting diodes matched with the driving device to carry out display control according to the gray data of the level.
The display device of the driving apparatus includes:
each driving device further comprises a power supply input end for receiving input voltage and a potential reference end;
any one light emitting diode in each driving device and a corresponding constant current unit are coupled in series between the power input end and the potential reference end, and a shunt module is also coupled between the power input end and the potential reference end.
The display device of the driving apparatus includes:
the multi-stage driving means are arranged in one or more columns, the power input of the first driving means in each column being coupled to the power supply anode and the potential reference of the last driving means in the column being coupled to the power supply cathode, and the power input of the following driving means in each column being coupled to the potential reference of the adjacent preceding driving means.
The display device of the driving apparatus includes:
each column driving device is connected in series with at least one current source module with a constant current source, and is used for limiting the total input current flowing from the power input end of any one driving device to the potential reference end in each column driving device to a preset value, and setting the constant current source in a mode of fixed output current or setting the programmable constant current source in a mode of adjustable output current.
The display device of the driving apparatus includes:
under the condition of setting a programmable constant current source, a decoder of a second data transmission module configured by the current source module is used for decoding second current regulation data from received communication data, and the current source module regulates the output current of the constant current source according to the second current regulation data; and
each current source module and the multistage driving device are also arranged in cascade connection, so that the current source module with the data forwarding function and the driving device can both forward communication data to the opposite party.
The display device of the driving apparatus includes:
after the last frame of communication data transmitted to the current source module and the driving device is refreshed to the next frame of communication data, the second current regulation data received by each current source module is synchronously refreshed according to frames;
The total input current of each of the column drivers is also redetermined by the current source module in series with each column driver according to the refreshed second current regulation data.
The display device of the driving apparatus includes:
the first data transmission module of the driving device is also used for decoding first current regulation data from the communication data, and the driving device regulates the constant current value provided by the programmable constant current unit according to the first current regulation data;
after the last frame of communication data transmitted to the current source module and the driving devices is refreshed to the next frame of communication data, the first current regulation data received by each driving device is synchronously refreshed according to the frames, so that the constant current provided by each constant current unit in each driving device is redetermined according to the refreshed first current regulation data.
The display device of the driving apparatus includes:
a bypass module connected with the multiple light-emitting diodes in parallel is arranged in each driving device, and a result obtained by performing a NOR logic operation on the multiple pulse width modulation signals corresponding to the multiple light-emitting diodes in each driving device is regarded as a control signal of the bypass module, and the bypass module is triggered to split the total input current of the driving device when the control signal has an effective logic value;
The shunt value of the bypass module in each driving device is determined by the constant current provided by one constant current unit, so that after the last frame of communication data transmitted to the current source module and the driving device is refreshed to the next frame of communication data, the constant current of the one constant current unit distributed to the bypass module in each driving device is redetermined according to the refreshed first current regulation data.
The display device of the driving apparatus includes:
the current source module and the multi-stage driving device transmit communication data in a mode based on a single-wire communication protocol.
The application relates to a display control method for driving multiple light emitting diodes, comprising the following steps:
setting any one light emitting diode and one constant current unit to be connected in series;
forming pulse width modulation signals corresponding to each path of light emitting diodes by using a pulse width modulation module according to gray data matched with each path of light emitting diodes, wherein a plurality of paths of light emitting diodes correspond to a plurality of paths of pulse width modulation signals;
whether each path of light emitting diode flows through constant current provided by a constant current unit connected with the light emitting diode in series or not is controlled by a path of pulse width modulation signal corresponding to the light emitting diode;
dividing a cycle period shared by each path of pulse width modulation signals into a plurality of sub-time periods, and arranging the effective logic value of each path of pulse width modulation signals in a corresponding sub-time period;
Distributing a clock signal for each sub-time period and setting the number of the clock signals of each sub-time period as a preset value;
determining the time length of each sub-time period according to the number of clock signals distributed in each sub-time period in a clock counting mode;
the frequencies of the plurality of clock signals allocated to the plurality of sub-periods of each cycle period are set to be the same or different.
The method, wherein:
the bypass module with the shunt function and the shunt module with the voltage stabilizing function are connected with the multipath light emitting diodes in parallel;
the bypass module is controlled to be connected or not by using a control signal, a result obtained by performing NOR logic operation on the multi-channel pulse width modulation signal is defined as the control signal, and the current of the bypass module under the condition of connection and shunt is a preset constant current value;
and in each cycle period, when none of the multiple light emitting diodes is conducted, at least the bypass module and the shunt module jointly implement shunt.
The method, wherein:
the effective logic values of each pulse width modulation signal in a corresponding sub-period are arranged in a continuous manner; or alternatively
The effective logic values of each pulse width modulated signal within a corresponding one of the sub-periods are arranged in a decentralized manner.
The method, wherein:
each pulse width modulation module outputs a dithering signal with an effective logic value once every a plurality of cycle periods, and any pulse width modulation module outputs the dithering signal:
if the effective logic values of the pulse width modulation signals are arranged in a continuous mode, setting the effective logic values of the pulse width modulation signals generated by any pulse width modulation module and outputting jitter signals immediately after finishing; or alternatively
If the effective logic values of the pulse width modulation signals are distributed in a scattered mode, the last effective logic value in the pulse width modulation signals generated by any pulse width modulation module is set to output a jitter signal immediately after the last effective logic value is finished.
The method, wherein:
the time length of any sub-time period is counted by triggering a counter through a clock signal matched with the counter, so that a count value of any sub-time period is obtained, and the count value is reordered according to a rule that the weight is low to high, so that inverted data are obtained;
and comparing the inverted sequence data of the count value of any sub-time period with the gray data matched with the lighted light emitting diode of the same sub-time period, wherein the pulse width modulation signal has a valid logic value when the inverted sequence data is lower than the gray data.
The method, wherein:
the time length of each sub-time period is adjusted in a mode of adjusting the frequency of one clock signal distributed by each sub-time period, and then the total time length of the cycle period shared by the pulse width modulation signals is adjusted.
The method, wherein:
the plurality of clock signals allocated for the plurality of sub-periods are respectively obtained by dividing the initial clock signal output from one oscillator by a plurality of times.
The application discloses a drive arrangement, drive emitting diode includes:
the pulse width modulation module forms a corresponding pulse width modulation signal according to the gray data matched with the light emitting diode;
the pulse width modulation signal is used for driving the light emitting diode to perform display control;
the pulse width modulation module is configured with a counter and a data comparator;
triggering the counter to count by a clock signal and obtaining a count value;
the count value is reordered according to the rule from low weight to high weight to obtain reverse order data;
the pulse width modulation module sends the gray data and the reverse order data into the data comparator for comparison:
the pulse width modulated signal has a valid logic value when the inverted data is lower than the gray data.
Drawings
So that the manner in which the above recited objects, features and advantages of the present invention can be understood in detail, a more particular description of the invention, briefly summarized below, may be had by reference to the appended drawings.
Fig. 1 is a schematic circuit architecture diagram of a driving circuit that drives a light source and is integrated with a data transmission function.
Fig. 2 is an alternative example of a constant current unit capable of outputting a constant current to a light emitting diode connected in series therewith.
Fig. 3 is another example of a constant current unit capable of outputting a constant current to a light emitting diode connected in series therewith.
Fig. 4 shows a data transmission module of the driving circuit and a pulse width modulation module cooperate to form a pulse width modulation signal.
Fig. 5 is a waveform diagram of the pulse width modulation module forming a multi-channel pulse width modulation signal according to gray data.
Fig. 6 is a graph of a cycle period common to each pulse width modulated signal divided into sub-time periods of adjustable duration.
Fig. 7 is a diagram of adjusting the time length of a sub-period in a manner that adjusts the frequency of a clock signal of the sub-period.
Fig. 8 is a schematic diagram of a driving circuit driving multiple light emitting diodes configured to share the same common constant current unit.
Fig. 9 is a schematic diagram of a bypass module connected in parallel with a plurality of leds to form a parallel shunt branch.
Fig. 10 is a schematic diagram of a bypass module with light emitting or non-light emitting diode loads in parallel with multiple light emitting diodes.
Fig. 11 shows that the light emitting diodes and the bypass modules connected in parallel with them are each provided with a constant current unit alone.
Fig. 12 is an example of a pwm module used for pwm signals with distributed active logic values.
FIG. 13 is a control signal resulting from a NOR operation performed on a pulse width modulated signal of continuous active logic values.
Fig. 14 is a control signal obtained by performing a nor operation on a pulse width modulated signal of a distributed active logic value.
Fig. 15 is an example of a pwm module circuit that generates pwm signals with distributed active logic values.
Fig. 16 is a graph of different gray scale data resulting in pulse width modulated signals having different discrete effective logic values.
Fig. 17 is a waveform of a pulse width modulated signal having a continuous active logic value with one dither signal added.
Fig. 18 is a waveform of a pulse width modulated signal having a distributed effective logic value with one dither signal added.
Fig. 19 is a schematic diagram of an alternative circuit architecture of a current source module that may provide a constant current source to a drive circuit.
Fig. 20 is a diagram of a second data transfer module of the current source module and trimming resistor to achieve regulation of the output current.
Fig. 21 is a schematic diagram of a cascade of driver circuits arranged in one or more columns with adjustable current source modules in each column.
Detailed Description
The solution according to the invention will now be described more clearly and completely in connection with the following examples, which are given by way of illustration only and not by way of all examples, on the basis of which those skilled in the art will attain solutions without inventive effort.
Referring to fig. 1, a driver chip IC, which is temporarily in the form of an integrated circuit, is taken as a typical example of a driver circuit for driving the light source of the light emitting diode to light, but it should be emphasized that this does not mean that the driver circuit can be designed as an integrated circuit only because discrete electronic components can also build up a functionally identical driver circuit. The drive circuit may be designed as an integrated circuit or may be built from discrete electronic components. The data transmission module DAT1 of the driving circuit and the data transmission module DAT2 of the current source module PCS, which will be described later, have the same decoding function, and they both have a decoder and can decode the input serial data according to a predetermined communication protocol, except that the former data requires decoding gray data from the received communication data and the latter data requires decoding current adjustment data. In fact, the decoder restores the signal with the preset coding rule in the communication data into the common binary data, and the restored data are slightly different in use so that the names are different. Circuits that perform basic protection functions like over-temperature protection, start-up protection, electrostatic protection, transient voltage protection, and spike current discharge circuits, and the like, as well as oscillators and power-on reset circuits, and even clock circuits, all belong to the necessary or optional parts of the driving chip, and are well known to those skilled in the art and will not be described again. The pulse width modulation essentially converts the amplitude of a signal into the time of the signal and obtains the pulse width signal, and the implementation mechanism of the pulse width modulation mainly comprises a counting comparison mode, a time delay unit mode, a shifting mode, a mixed mode combining the counting comparison and the time delay unit and other main technical routes, and the result is the pulse width signal with a certain duty ratio in any mode. The so-called digital pulse width modulation DPWM technique in the industry is within the category of the prior art. The pulse width modulation module of the driving circuit forms a pulse width modulation signal according to gray data, and the gray data is used for determining the duty ratio of the pulse width modulation signal, so that the pulse width modulation signal can be considered to represent the duty ratio information carried by the gray data. A driving circuit is a typical example of the driving device.
Referring to fig. 1, four-way light emitting diodes are only schematically shown based on convenience of explanation, and it should be understood that the specific number of light sources is not limited in any way and is only used for reference. Assuming that the data transmission module DAT1 decodes four groups of gray data in the communication data, the first pulse width modulation module PWM1 forms a first pulse width modulation signal corresponding to the first light emitting diode LED1 according to the gray data allocated to the first light emitting diode LED1, the second pulse width modulation module PWM2 is set according to the same rule to form a second pulse width modulation signal corresponding to the second light emitting diode LED2 according to the gray data allocated to the second light emitting diode LED2, the third pulse width modulation module PWM3 forms a third pulse width modulation signal corresponding to the third light emitting diode LED3 according to the gray data allocated to the third light emitting diode LED3, and the fourth pulse width modulation module PWM4 forms a fourth pulse width modulation signal corresponding to the fourth light emitting diode LED4 from the gray data allocated to the fourth light emitting diode LED 4. From this it can be learned that: each pulse width modulation module in the driving circuit forms a corresponding pulse width modulation signal according to the gray data matched with the corresponding light emitting diode, specifically, each pulse width modulation module forms a pulse width modulation signal corresponding to each light emitting diode according to the gray data distributed to each light emitting diode. The four-way light emitting diode comprises a white light type light emitting diode besides a red, green and blue three-primary-color light source, or comprises two alternatives of green, red, blue and the like. If the illumination display scene does not need multiple light-emitting diode light sources but only needs a single light source, the four light-emitting diodes can be reduced to only a single diode.
Referring to fig. 1, a first light emitting diode LED1 and a constant current unit CC1 are connected in series, and the constant current unit CC1 generating a constant current is controlled by a first pulse width modulation signal. The first pulse width modulation signal determines constant current lighting time of the first light emitting diode in the period of the first pulse width modulation signal. A constant current of full amplitude for the light source is loaded onto the light source in a repetitive pulse sequence of on or off: when the current is in the off state, for example, the first pulse width modulation signal has the low level logic, the constant current is disconnected from the first light emitting diode LED 1.
Referring to fig. 1, a second light emitting diode LED2 and a constant current unit CC2 are connected in series, and the constant current unit CC2 generating a constant current is controlled by a second pulse width modulation signal. The second path pulse width modulation signal determines the constant current lighting time of the second path light emitting diode in the period of the second path pulse width modulation signal. The constant current is output and loaded on the second path light emitting diode LED2 if the second path pulse width modulation signal has a high level logic, whereas the constant current is disconnected from the second path light emitting diode LED2 if the second path pulse width modulation signal has a low level logic.
Referring to fig. 1, a third light emitting diode LED3 is arranged to be connected in series with the constant current unit CC3, and the constant current unit CC3 that generates a constant current is controlled by a third pulse width modulation signal that determines a constant current lighting time of the third light emitting diode in a period of the third pulse width modulation signal. The constant current is output and loaded on the third light emitting diode LED3 if the third pulse width modulation signal has a high level logic, whereas the constant current is disconnected from the third light emitting diode LED3 if the third pulse width modulation signal has a low level logic.
Referring to fig. 1, a fourth light emitting diode LED4 is arranged and connected in series with the constant current unit CC4, and the constant current unit CC4 generating a constant current is controlled by a fourth pulse width modulation signal, and the fourth pulse width modulation signal determines a constant current lighting time of the fourth light emitting diode in a period of the fourth pulse width modulation signal. The constant current is output and loaded on the fourth light emitting diode LED4 when the fourth pulse width modulation signal has a high level logic, whereas the constant current is disconnected from the fourth light emitting diode LED4 when the fourth pulse width modulation signal has a low level logic. In this example, multiple constant current units, such as the constant current units CC1-CC4, are provided, and each led is separately connected in series with a corresponding constant current unit in a one-to-one manner. If the pulse width modulation signal of any one path, such as the fourth path, corresponding to the LED4, has an effective logic level, such as a high level, the any one path, such as the LED4, is turned on by a constant current, and a path of constant current unit, such as the CC4, connected in series with the any one path, such as the LED4, is turned on.
Referring to fig. 1, the driving circuit is provided with a shunt module SHU connected in parallel with the plurality of light emitting diodes and is used for shunting the plurality of light emitting diodes. The driving current of each path of pulse width modulation signal for the corresponding light source is either completely or completely absent in the cycle period, and the constant current of the driving current is regarded as being loaded on each path of light emitting diode in a repeated pulse sequence of on or off, so that the current which is on or off and is hopped by each path of light emitting diode is liable to cause the large swing of the input and output currents of the driving circuit, the higher the frequency of the swing of the current is and the greater the degree of the current swing is, and the instantaneous current of the solid-state light emitting diode light source is a great challenge for the design of the driving circuit. The meaning of the shunt module SHU is: when any one led is turned on or off to generate current jump, the shunt module SHU will adaptively adjust the shunt value flowing through the shunt module SHU to maintain the total input current of the driving circuit at a preset value. Taking the constant current unit CC1 as an example, it is either turned on or turned off under the control of the first pulse width modulation signal, when the constant current unit is turned on, the current splitting module may adaptively reduce the current of the first light emitting diode LED1 to compensate the on current of the first light emitting diode LED1, or when the constant current unit is turned off, the current splitting module may adaptively increase the current flowing through the first light emitting diode LED1 to compensate the current reduction condition of the first light emitting diode LED 1. The current which is in jump and is generated when other LEDs are turned on or off is compensated by the shunt module SHU. Even if the current jump event occurs and the total current of the multiple light emitting diodes is not changed, the shunt value of the shunt module can be kept unchanged, for example, the current reduced by turning off one light emitting diode is exactly compensated by turning on the other light emitting diode synchronously, and the compensation mechanism aims to clamp the total input current of the driving circuit to be within a preset value or a preset range.
Referring to fig. 2, a topology that is more suitable for use in the field of solid state light source display or lighting is a linear converter, which is also referred to in the industry as a linear modulator or series regulator. The constant output current generated by the constant current unit CC1 is the driving current ID1 supplied to the light source load: the transistor MQ constitutes an equivalent adjustable electrical resistance connecting the power supply and the light source and operates in a linear state or in a non-switching state. A light emitting diode light source, a transistor MQ and a sampling resistor RS1 are connected in series between a power input end and a potential reference end in the driving circuit, driving current flowing through the light source also flows through the sampling resistor RS1 connected in series with the light source, sampling voltage and reference voltage VB1 at two ends of the sampling resistor RS1 are respectively input to a negative end and a positive end of an error amplifier EA1 for amplification comparison, and an output voltage part of the error amplifier EA1 is also required to be coupled to a control end of the transistor MQ to drive the transistor to operate in a pipeline mode. The magnitude of the drive current flowing through the sampling resistor multiplied by the resistance of the sampling resistor is equal to the sampling voltage, which can in fact be used indirectly to characterize the magnitude of the drive current. The reference voltage VB1 approaches equal to or greater than the sampled voltage across the sampling resistor and it essentially indirectly determines the magnitude of the drive current. The reference voltage VB1 allows for a stable voltage provided by the bandgap reference source BG1 with a higher robustness if the driving circuit is designed as an integrated circuit. The current mirror structure is used by the improved constant current unit CC1 to provide driving current for the light source, so that a mirror transistor of the transistor MQ is required to be defined in the current mirror structure, the current flowing in the mirror transistor, which is not shown in the figure, is equal to the driving current ID1 or is in proportion to the driving current ID1, the driving circuit is changed to a mirror transistor of the light source and the transistor MQ connected in series between the power input terminal and the potential reference terminal, and the mirror current provided by the mirror transistor is used as the constant current generated by the constant current unit CC1 to be output to the light source.
Referring to fig. 2, in an alternative example, a controlled switch, not shown, is provided between the output of the error amplifier EA1 and the control terminal of the transistor MQ. Taking the first light emitting diode LED1 and the corresponding first pulse width modulation signal as an example, the first pulse width modulation signal is used to control the controlled switch to be turned on or off in the constant current unit CC 1. The controlled switch is turned on if the first pulse width modulation signal exhibits an active logic level, such as a high level, and is turned off if the first pulse width modulation signal exhibits an inactive logic level, such as a low level. In this embodiment, whether the constant current provided by the constant current unit CC1 connected in series with the first light emitting diode LED1 flows through the first light emitting diode LED1 is controlled by the first pulse width modulation signal corresponding to the first light emitting diode LED 1. Whether the constant current provided by the constant current unit CC2 connected in series with the second light emitting diode LED2 flows or not is controlled by the second pulse width modulation signal corresponding to the second light emitting diode LED 2. And so on until the third light emitting diode LED3 is controlled by a third pulse width modulation signal corresponding to the third light emitting diode LED3 by a constant current provided by the constant current unit CC3 connected in series with the third light emitting diode LED 3. The constant current cells CC1-CC4 claim in this alternative example that controlled switches are provided between the error amplifier EA1 output of each constant current cell and the control terminal of the transistor MQ but this is only an alternative example and not the only solution. Still take the first light emitting diode LED1, the constant current unit CC1 corresponding to the first light emitting diode LED1, and the first pulse width modulation signal as an example: assuming that a first terminal of the transistor MQ is coupled to the cathode of the first light-emitting diode LED1 and that the anode of the first light-emitting diode LED1 is connected to the power input terminal, an opposite second terminal of the transistor MQ is connected to the sampling resistor RS1. In alternative embodiments the controlled switch may also be shifted from the original connection position to lie between the sampling resistor RS1 and the second end of the transistor MQ, or alternatively between the first end of the transistor MQ and the first path light-emitting diode LED1, etc. The controlled switch position moves and causes the circuit to change but still satisfies: whether the first light emitting diode LED1 flows through the constant current provided by the constant current unit CC1 connected in series is controlled by a first pulse width modulation signal corresponding to the first light emitting diode LED 1.
Referring to fig. 3, IN an alternative example, a light emitting diode light source LED1, a transistor PQ and a sampling resistor RS2 are connected IN series between a power input terminal IN and a potential reference terminal OUT of the driving circuit, and a driving current flowing through the light source also flows through the sampling resistor RS2 connected IN series therewith. The sampling voltage at both ends of the sampling resistor RS2 and the reference voltage VB2 are respectively inputted to the positive terminal and the negative terminal of the error amplifier EA2 for amplification comparison, and the output voltage portion of the error amplifier EA2 is coupled to the control terminal of the transistor PQ to drive the transistor to operate in a pipeline. The constant output current generated by the constant current unit CC1 is the driving current ID2 supplied to the light source load. Comparing the embodiment of fig. 2 with the embodiment of fig. 3, the light emitting diode LED1 is shifted to be connected between the transistor PQ and the sampling resistor RS2 in the driving circuit. From this, it can be seen that the topology of the constant current cell CC1 generating a constant output current is not unique but diverse.
Referring to fig. 4, if the driving circuit uses locally stored gradation data as a display resource, the driving apparatus does not need the data transmission module DAT1 functioning as a communication at all. In contrast, the data transmission module DAT1 is indispensable if the driving apparatus is operated in a mode of collecting gray data on line.
Referring to fig. 4, allowing the driving circuit and the current source module PCS to be cascade-connected to each other also allows the driving circuits to be cascade-connected to each other so that they all have a data forwarding function. One of the core functions of the driving circuit is to drive a plurality of light emitting diodes matched with the driving circuit to light according to the display requirement, and when the three primary colors are mixed, the relative brightness ratio of the three primary colors of red, green and blue is changed, so that different colors can be obtained. Changing the brightness ratio of the LEDs of various colors by changing the lighting time of the LEDs of red, green and blue colors in the cycle period during the color mixing of the three primary colors is equivalent to changing the relative brightness ratio of the three primary colors so as to obtain different colors when the gray level of the LEDs is changed. In an alternative example, it is assumed that the first to fourth light emitting diodes LED1 to LED4 are red, green, blue primary color diodes and white light emitting diodes, which are temporarily considered and the other light source sections are omitted. The data transmission module DAT1 of the driving circuit configuration has a decoder which decodes the input serial data according to a predetermined communication protocol and decodes gradation data or the like from the received communication data, and the driving circuit adjusts the color of the pixel according to the gradation data assigned to each of the red, green, blue, and white light emitting diodes. In an alternative example, the mechanism by which the data transmission module DAT1 receives communication data and forwards the data is illustrated by taking the data decoder 110 and the data forwarding module 120 as examples. The signal input terminal DI receives communication data provided from outside, and the decoder 110 needs to decode or decode the data information carried in the communication data, wherein the meaning of data decoding is that the data in a pre-coding format which cannot be directly displayed by the light emitting diode can be restored to a conventional binary code which is easy to identify and execute, the binary code obtained by decoding is temporarily stored in the register 130, and in consideration of that the data refreshing of the register 130 is faster, the decoded data can be stored by using another buffer space or latch 150. The decoding process of the communication data can select to detect the ending instruction code or the resetting instruction in the data to judge whether the data is transmitted and received. Taking the return-to-zero code as an example, the reset instruction is represented by a long low level of relatively long duration. The long low level detection circuit, not shown in the figure, RESETs the driving circuit and refreshes the received gradation data from the latch 150 to the first to fourth pulse width modulation modules PWM1 to PWM4 if it is monitored that a long low level indicating a RESET instruction RESET occurs. The first to fourth pulse width modulation modules respectively generate first to fourth pulse width modulation signals and record the signals as DR and DG and DB and DW, and the four pulse width modulation signals are used for controlling whether the red, green, blue and white light emitting diodes are lighted and the constant current lighting time. And (3) adjusting the gray data of each path of light emitting diode during the color mixing of the three primary colors, and obtaining different colors according to the gray data change of the three primary colors.
Referring to fig. 4, the driver circuit is assumed to be data regenerating or data forwarding by the data forwarding module 120, and performs a so-called data transmission task such as transferring communication data to the rear driver circuit. The simplest forwarding mode of the data forwarding module 120 is to enable the communication data received by the signal input terminal DI to be directly output from the signal output terminal DO, and the driving circuit or the current source module PCS connected in cascade extracts the communication data which matches with the address of the user from the single data line according to the address allocation rule. The alternative first forwarding path Sel1 needs to cooperate with statistics of communication data belonging to each stage of driving circuit, and after each stage of driving circuit intercepts communication data belonging to each frame of communication data, each stage of driving circuit forwards the rest of other received communication data to a next stage of communication data receiver cascaded with the driving circuit, and the next stage of communication data receiver can be a next stage of driving circuit or a current source module PCS. Each stage of the driving circuit counts whether the total number of bits of the communication data attributed to it is completely received, as a result of which, once the communication data attributed to the driving circuit is decoded and completely received by it, an enable signal ENB is generated, which, when active, for example, high-level, triggers the data forwarding module 120 to forward the communication data received at the signal input DI from the signal output DO, in which case the data forwarding module 120 plays the role of a switch whether the received communication data is allowed to be output. It is understood that the data transmission module DAT2 described later and the data transmission module DAT1 of the driving circuit are substantially identical in function in data decoding and data forwarding. To address the cascading attenuation effect, the data forwarding module 120 may reconstruct each bit in addition to acting as a switch so that its transmission loss is trimmed to recover the standard transmission code. The counter 160 may be used to count whether the total number of bits required by the driving circuit is completely received, and the counter 160 generates a valid enable signal ENB after the communication data belonging to the driving circuit is decoded and completely received.
Referring to fig. 4, it can be seen from the foregoing that a similar second forwarding path Sel2 requires the communication data to be decoded by the decoder 110 of the data transmission module DAT 2. The data forwarding module 120 plays a role of a switch to decide whether to allow the decoded data to be forwarded under the control of the enable signal ENB, the forwarded data being the result of the input data being decoded and re-encoded and then forwarded: the coded data having the predetermined coding format at the time of forwarding are decoded and synchronized to be restored to the data of the predetermined coding format under sampling of the clock resource of the data transmission module DAT 1. Other schemes for implementing data forwarding are recoding technology, namely a third forwarding path Sel3, the recoding technology of the data transmission module DAT1 is implemented by the configured encoder 140, after the communication data is decoded and temporarily stored in the storage space of the data transmission module DAT1, the encoder 140 which can recode binary data recodes the temporary data to output, and the relay effect of decoding, storing and recoding the data according to a preset coding format ensures that the data can be smoothly transferred. The second forwarding path Sel2 and the third forwarding path Sel3 described above need to be discriminated from each other: the former uses local clock resource to sample input data and restore the sampling result into data with preset coding format, so each bit data is not only restored with the represented binary data under the sampling condition of clock resource, the sampling result synchronization of clock resource is also regarded as reconstruction data needing to be forwarded, therefore the former is only equivalent to recoding the input data in the data reconstruction process of each bit input data; the latter is different in that input data is actually recoded by means of an additional encoder and conforms to the regulations of protocols like manchester or return-to-zero codes and symbol periods obtained by local decoding, and is output to communication data receivers such as a post-driver circuit or a current source module.
Referring to fig. 4, the first PWM module PWM1 forms a first pulse width modulation signal DR corresponding to the first light emitting diode LED1 according to the gray data distributed to the first light emitting diode LED1, namely, the bit data denoted as R < M > to R <0 >. The cycle count data provided by the counter CNT and the gray scale data R < M > to R <0> are compared using the count comparison mode to obtain the first pulse width modulation signal DR. Digital pulse width modulation based on count comparison is to compare gray scale data with counter data using an exemplary comparator CMP 1. The first pulse width modulation signal has a high level period and a low level period in the working period, for example, the first pulse width modulation signal DR in the high level period can instruct the constant current unit CC1 to provide the generated constant current to the first light emitting diode LED1, and the first pulse width modulation signal DR in the low level period can instruct the constant current unit CC1 not to provide the generated constant current to the first light emitting diode LED1 any more so as to make it unable to be turned on. The first pulse width modulation signal DR is equivalent to the fact that the on time and the off time of the red light emitting diode in the period of the first pulse width modulation signal DR are determined. The natural number M used to represent the number of bits of gray data is greater than 1, and most commonly taking 8 bits, i.e., R <7> through R <0> together, provides 256 gray levels for the red LED, and 65536 gray levels if 16 bits are taken. The number of bits of gradation data is not limited to a specific number of bits of 8 or 16, and the specific number of bits is described here for convenience of explanation. The first path of pulse width modulation signal essentially reflects the duty ratio information carried by the gray data matched with the red light emitting diode. Whether the red light emitting diode flows through the constant current provided by the constant current unit CC1 connected in series with the red light emitting diode is controlled by the corresponding first pulse width modulation signal DR, and the constant current lighting time of the red light emitting diode in the period of the first pulse width modulation signal DR is determined by the corresponding first pulse width modulation signal DR of the red light emitting diode.
Referring to fig. 4, the second PWM module PWM2 forms a second pulse width modulation signal DG corresponding to the second light emitting diode LED2 according to the gray scale data distributed to the second light emitting diode LED2, i.e., the bit data denoted as G < M > to G <0 >. The cycle count data supplied from the counter CNT and the gradation data G < M > to G <0> are compared by using the count comparison mode to obtain the second pulse width modulation signal DG. Digital pulse width modulation based on count comparison is to compare gray scale data with counter data using an exemplary comparator CMP 2. The second pulse width modulation signal has a high level period and a low level period in the working period, for example, the second pulse width modulation signal DG can instruct the constant current unit CC2 to provide the generated constant current to the second light emitting diode LED2 in the high level period, and conversely, the second pulse width modulation signal DG can instruct the constant current unit CC2 to no longer provide the generated constant current to the second light emitting diode LED2 in the low level period, which is equivalent to that the second pulse width modulation signal DG determines the on time and the off time of the green light emitting diode in the period of the second pulse width modulation signal DG. If the number of bits of the gradation data allocated to the green light emitting diodes takes 8 bits, that is, G <7> to G <0> total 8 bits of data, the total can provide 256 gradation levels for the green light emitting diodes, and if 16 bits are taken, 65536 gradation levels are provided. The second pulse width modulation signal essentially represents the duty cycle information carried by the gray scale data of the green light emitting diode match. Whether the green light emitting diode flows through the constant current provided by the constant current unit CC2 connected in series with the green light emitting diode is controlled by the second pulse width modulation signal DG corresponding to the constant current, and the constant current lighting time of the green light emitting diode in the period of the second pulse width modulation signal DG is determined by the second pulse width modulation signal DG corresponding to the green light emitting diode.
Referring to fig. 4, the third PWM module PWM3 forms a third PWM signal DB corresponding to the third LED3 according to the gray-scale data distributed to the third LED3, namely, the bit data denoted as B < M > to B <0 >. The cycle count data supplied from the counter CNT and the gradation data B < M > to B <0> are compared with each other by using the count comparison mode to obtain the second pulse width modulation signal DB. Digital pulse width modulation based on count comparison is to compare gray scale data with counter data using an exemplary comparator CMP 3. The third pulse width modulation signal has a high level period and a low level period in the working period, for example, the third pulse width modulation signal DB can instruct the constant current unit CC3 to provide the generated constant current to the third light emitting diode LED3 in the high level period, and conversely, the third pulse width modulation signal DB can instruct the constant current unit CC3 to no longer provide the generated constant current to the third light emitting diode LED3 in the low level period so as to make the third light emitting diode LED3 non-conductive, which is equivalent to that the third pulse width modulation signal DB determines the on time and the off time of the blue light emitting diode in the period of the third pulse width modulation signal DB. If the number of bits of the gradation data allocated to the blue light emitting diodes takes 8 bits, that is, B <7> to B <0> total 8 bits of data, the total can provide 256 gradation levels for the blue light emitting diodes, and if 16 bits are taken, 65536 gradation levels are provided. The third path of pulse width modulation signal essentially represents the duty cycle information carried by the gray scale data matched by the blue light emitting diode. Whether the blue light emitting diode flows through the constant current provided by the constant current unit CC3 connected in series with the blue light emitting diode is controlled by the third pulse width modulation signal DB corresponding to the constant current, and the constant current lighting time of the blue light emitting diode in the period of the third pulse width modulation signal DB is determined by the third pulse width modulation signal DB corresponding to the blue light emitting diode.
Referring to fig. 4, the fourth pulse width modulation module PWM4 forms a fourth pulse width modulation signal DW corresponding to the fourth light emitting diode LED4 based on the gray scale data assigned to the fourth light emitting diode LED4, namely, the bit data denoted as W < M > to W <0 >. The fourth pulse width modulation signal DW is obtained by comparing the cycle count data supplied from the counter CNT with the gradation data W < M > to W <0> using the count comparison mode. Digital pulse width modulation based on count comparison is to compare gray scale data with counter data using an exemplary comparator CMP 4. The fourth pulse width modulation signal has a high level period and a low level period in the working period, the fourth pulse width modulation signal DW can instruct the constant current unit CC4 to provide the generated constant current to the fourth light emitting diode LED4 in the high level period, and the fourth pulse width modulation signal DW can instruct the constant current unit CC4 to no longer provide the generated constant current to the fourth light emitting diode LED4 in the low level period so that the fourth light emitting diode LED cannot be turned on, which is equivalent to the fourth pulse width modulation signal DW determining the on time and the off time of the white light emitting diode in the fourth pulse width modulation signal DW period. If the bit number of the gradation data allocated to the white light emitting diodes takes 8 bits, that is, W <7> to W <0> total 8 bits of data, the total can provide 256 gradation levels for the white light emitting diodes. The fourth pulse width modulation signal essentially reflects the duty ratio information carried by the gray data matched by the white light emitting diode. Therefore, whether the white light emitting diode flows the constant current provided by the constant current unit CC4 connected in series with the white light emitting diode is controlled by the fourth pulse width modulation signal corresponding to the white light emitting diode. And the constant-current lighting time of the white light emitting diode in the period of the fourth pulse width modulation signal DW is determined by the fourth pulse width modulation signal DW corresponding to the white light emitting diode.
Referring to fig. 5, a cyclic period T common to the respective pulse width modulation signals DR and DG and DB and DW is divided into a plurality of sub-periods T1-T4 as shown. The effective logic value of each pulse width modulation signal is distributed in a corresponding sub-time period, and then the multiple light emitting diodes are sequentially lightened in a time-sharing way in the cycle period T: the first pulse width modulation signal DR has an effective logic value, such as a logic high level 1, distributed within the first sub-period T1, the second pulse width modulation signal DG has an effective logic value, such as a logic high level 1, distributed within the second sub-period T2, the third pulse width modulation signal DB has an effective logic value, such as a logic high level 1, distributed within the third sub-period T3, and the fourth pulse width modulation signal DW has an effective logic value, such as a logic high level 1, distributed within the fourth sub-period T4. The multiple light emitting diodes are time-division sequentially lighted in a cycle period T: the first sub-period T1 has the pulse width modulation signal DR having a valid logic value, the second sub-period T2 has the pulse width modulation signal DG having a valid logic value, the third sub-period T3 has the pulse width modulation signal DB having a valid logic value, and the fourth sub-period T4 has the pulse width modulation signal DW having a valid logic value, the fourth sub-period T4 has the pulse width modulation signal DR having a valid logic value. The red leds will not light up in T2-T4 and the green leds will not light up in T1 and T3-T4, the blue leds will not light up in T4 and T1-T2 and the white leds will not light up in T1-T3. Each sub-time period is allocated with a clock signal, and the number of the clock signals of each sub-time period is set as a preset value: the first sub-period T1 distributes the clock signal CK1 and the number of the clock signals of the first sub-period T1 are preset values, the second sub-period T2 distributes the clock signal CK2 and the number of the clock signals of the second sub-period T2 are preset values, the third sub-period T3 distributes the clock signal CK3 and the number of the clock signals of the third sub-period T3 are preset values, and the fourth sub-period T4 distributes the clock signal CK4 and the number of the clock signals of the fourth sub-period T4 are preset values. Determining the time length of each sub-time period according to the clock signal distributed by each sub-time period and the number of the clock signals in a clock counting mode: the time length of the first sub-period T1 is calculated to be equal to the number of clock signals CK1 times the period time of the clock signals CK1, the time length of the second sub-period T2 is the number of clock signals CK2 times the period time of the clock signals CK2, the time length of the third sub-period T3 is the number of clock signals CK3 times the period time of the clock signals CK3, and the time length of the fourth sub-period T4 is the number of clock signals CK4 times the period time of the clock signals CK 4. The frequencies of the plurality of clock signals CK1-CK4 allocated for the plurality of sub-periods T1-T4 of each cycle period may be set to be the same or different in an alternative example.
Referring to fig. 4, a plurality of pulse width modulation modules PWM1 to PWM4 are configured with one counter CNT, and the multi-bit count data output from the counter includes designated high-order data and designated low-order data. Assume that the specified high-order data includes high-order data Q shown in the figure<M+1>-Q<M+2>While the specified low bit data includes Q<M>-Q<0>. The number of sub-periods within each cycle may be determined by the number of bits Z of the specified high-order data, and the preset value for the number of clock signals within each sub-period may be determined by the number of bits F of the specified low-order data. The time length of each sub-time period is counted by a clock signal trigger counter matched with the sub-time period: the first sub-period T1 is counted by the clock signal CK1, the second sub-period T2 is counted by the clock signal CK2, the third sub-period T3 is counted by the clock signal CK3, and the fourth sub-period T4 is counted by the clock signal CK 4. Setting the number of bits Z of the specified high-order data and the number of bits F of the specified low-order data to be natural numbers greater than zero, e.g. F=M+1, the number of sub-periods within T per cycle does not exceed 2 Z And the preset value in each sub-period is 2 F . The preset value for the number of clock signals in each sub-period can be determined by the number of bits F of the specified low-order data. In an alternative example, assuming that m=7 and z=2, the number of sub-periods in each cycle period does not exceed 4 and the number of clock signals in each sub-period is 256. If four sub-periods are employed, corresponding to the clock signal CK1 being counted 256 times in the first period T1, the clock signal CK2 being counted 256 times in the second period T2, and the clock signal CK3 being counted 256 times in the third period T3, the clock signal CK4 being counted 256 times in the fourth period T4, the total time length of the cycle period T is t1+t2+t3+t4. Also for example z=1, the number of sub-periods per cycle period T does not exceed 2. The adjustment of the frequency of a clock signal allocated to each sub-period is equivalent to the adjustment of the time length of each sub-period, and then the adjustment of the total time length of the cycle period shared by the pulse width modulation signals, for example, the adjustment of the frequency of each of CK1-CK4 can adjust the total time length of T. In this embodiment it is assumed that the multi-bit count data output by the counter CNT includes Q <M+2>To Q<0>High order bits specified in count dataAccording to can not be limited to two bits Q<M+1>-Q<M+2>The number of bits M+1 of the specified low-order data is also optional.
Referring to fig. 4, the counter CNT is configured with a data selector MUX. The clock signals CK1-CK4 allocated for the sub-periods T1-T4 are input to the data inputs of the data selector MUX. The designated high-order data is regarded as a channel selection signal of the data selector MUX, such as the high-order data Q<M+1>-Q<M+2>The channel select signals SL1/SL2 or address code input are considered as data selectors. If the high-order data Q<M+1>-Q<M+2>If the value is 00, the data selector MUX is triggered to switch to the output clock signal CK1, and the high-order data Q<M+1>-Q<M+2>When the value is 01, the data selector MUX is triggered to switch to the output clock signal CK2, and the high-order data Q<M+1>-Q<M+2>If the value is 10, the data selector MUX is triggered to switch to the output clock signal CK3, and the high-order data Q<M+1>-Q<M+2>A value of 11 triggers the switching of the data selector MUX to the output clock signal CK4. In addition, the first period T1 will result in the high-order data from the initial 00 carry to 01 once after ending, the second period T2 will result in the high-order data from 01 carry to 10 after ending, and the third period T3 will result in the high-order data from 10 carry to 11 after ending. The specified low-level data Q within each cycle period T <M>-Q<0>Each time the count is full, the designated high-order data Q is triggered<M+1>-Q<M+2>And executing carry once operation, and triggering the data selector MUX to switch and output different clock signals. For example, in an alternative example, the counter CNT is triggered by the clock signal CK1 to count a preset value 2 F Next, the first sub-period T1 is obtained, and when the clock signal CK1 triggers the low-order data Q output by the counter CNT<M>To Q<0>All 1's would trigger the designated high bit data Q when the count is full<M+1>-Q<M+2>Carry operations from 00 to 01 are performed. In an alternative example, the counter CNT is triggered by the clock signal CK2 to count a preset value 2 F Next obtaining a second sub-period T2, and when the clock signal CK2 triggers the low-order data Q output by the counter CNT<M>To Q<0>All 1's would trigger the designated high bit data Q when the count is full<M+1>-Q<M+2>Carry out carry from 01 to 10And (3) operating. In an alternative example, the counter CNT is triggered by the clock signal CK3 to count a preset value 2 F A third sub-period T3 is obtained, and the clock signal CK3 triggers the low-order data Q output by the counter CNT<M>To Q<0>All 1's would trigger the designated high bit data Q when the count is full<M+1>-Q<M+2>Carry operations from 10 to 11 are performed. When the last cycle T ends and the next cycle T comes, Q <M+1>-Q<M+2>And reset to 00 again. Different channel selection signals are mapped to different clock signals output by the data selector, e.g. Q<M+1>-Q<M+2>The four states of (a) are that the four channel selection signals map the different clock signals CK1-CK4 output by the data selector, so that one clock signal is allocated for each sub-period and used to trigger the counter CNT to count. The oscillator OSC generates an initial clock signal which is divided by the divider DIV a plurality of times to obtain four clock signals CK1-CK4 having different frequencies. In an alternative example, four clock signals CK1-CK4 of different frequencies may also be generated independently by four separate oscillators.
Referring to fig. 4, in an alternative embodiment, the data selector MUX is not used any more, it is also possible to allocate a clock signal to each sub-period and the number of clock signals of each sub-period is a preset value. For example, the first counter, which is not shown, is directly triggered by the clock signal CK1 to count, and the time length of the first sub-period T1 is triggered by the clock signal CK1 matched with the first sub-period T1 to count, and the number of times the first counter counts in the first sub-period T1 may be a preset value defined in advance. The same principle can be used for counting by triggering a second counter which is not shown by the clock signal CK2, the time length of the second sub-period T2 is counted by triggering the second counter by the clock signal CK2 matched with the second sub-period T2, and the number of times of counting by the second counter in the second sub-period T2 can also be a preset value which is defined in advance. The same principle can be used for counting by triggering a third counter which is not shown by the clock signal CK3, the time length of the third sub-period T3 is counted by triggering the third counter by the clock signal CK3 matched with the third sub-period T3, and the number of times of counting by the third counter in the third sub-period T3 can also be a preset value which is defined in advance. The same principle can be used for counting by triggering a fourth counter which is not shown by the clock signal CK4, the time length of the fourth sub-period T4 is counted by triggering the fourth counter by the clock signal CK4 matched with the time length, and the number of times of counting by the fourth counter in the fourth sub-period T4 can also be a preset value which is defined in advance. The same purpose is still achieved by the clock counting method, but more hardware resources are consumed, the time length of each sub-period can be determined according to the clock signal distributed in each sub-period and the number of the clock signals, and the frequencies of the clock signals CK1-CK4 distributed for the sub-periods in each cycle period T can be the same or different.
Referring to fig. 5, the first pulse width modulation signal DR in this embodiment exhibits an effective logic value, i.e., a logic high level RH, during the first sub-period T1. The second pulse width modulated signal DG exhibits a valid logic value, i.e. a logic high GH level, during the second sub-period T2. The third pulse width modulated signal DB exhibits a valid logic value, i.e., a logic high level BH, during the third sub-period T3. The fourth pulse width modulated signal DW exhibits an effective logic value, i.e., a logic high level WH, during a fourth sub-period T4. The effective logic values of each of the first through fourth pulse width modulated signals DR-DW during a respective one of the sub-periods are arranged in a continuous manner. The effective logic values of the logic high level RH in the first sub-period T1 are arranged in a continuous manner, the effective logic values of the logic high level GH in the second sub-period T2 are arranged in a continuous manner, the effective logic values of the logic high level BH in the third sub-period T3 are arranged in a continuous manner, and the effective logic values of the logic high level WH in the fourth sub-period T4 are arranged in a continuous manner.
Referring to fig. 5, in an alternative example, the first pulse width modulation module PWM1 is enabled during the first sub-period T1 and compares the gray data R < M > -R <0> of the red light source matching with the low data portion of the count data of the counter CNT, i.e., Q < M > -Q <0>, during the first sub-period T1, so that the effective logic level of the first pulse width modulation signal DR can be arranged during the first sub-period T1. The second sub-period 2 starts after the end of the first sub-period T1, the second pulse width modulation module PWM2 is enabled during the second sub-period T2, and the second pulse width modulation module PWM2 compares the gray-scale data G < M > -G <0> matched with the low-data portion of the count data of the counter CNT during the second sub-period T2, that is, Q < M > -Q <0>, so that the effective logic level of the second pulse width modulation signal DG is safely discharged during the second sub-period T2. When the third sub-period T3 starts after the end of the second sub-period T2, the third pulse width modulation module PWM3 is enabled during the third sub-period T3, and the third pulse width modulation module PWM3 compares the gray-scale data B < M > -B <0> matched with the low-bit data portion of the count data of the counter CNT during the third sub-period T3, that is, Q < M > -Q <0>, so that the effective logic level of the third three-way pulse width modulation signal DB can be safely discharged during the third sub-period T3. After the third sub-period T3 ends and the fourth sub-period T4 starts, the fourth pulse width modulation module PWM4 is enabled in the fourth sub-period T4, and the fourth pulse width modulation module PWM4 compares the gray-scale data W < M > -W <0> matched with the low-data portion of the count data of the counter CNT in the fourth sub-period T4, that is, Q < M > -Q <0>, so that the effective logic level of the fourth pulse width modulation signal DW can be safely discharged in the fourth sub-period T4. The first to fourth pulse width modulation modules PWM1 to PWM4 compare the gray data with the count data using the data comparators CMP1 to CMP4, respectively. Taking the gray data R < M > -R <0> given by the red light source in the first sub-period T1 as an example, the low data state output by the counter CNT can be used to trigger the RS latch LAT carried by the comparator CMP1 to be set and start outputting a high level at the start time of the first sub-period T1 when the first sub-period T1 arrives, and the low data Q < M > -Q <0> in the first sub-period T1 is counted from all zeros and once the given gray data R < M > -R <0>, the RS latch LAT is triggered to be reset and switched to output a low level, that is, the output of the comparator CMP1 is inverted. Other examples take the gray data G < M > -G <0> given by the green light source in the second sub-period T2 as an example, the low data state output by the counter CNT is used to trigger the RS latch LAT carried by the comparator CMP2 to be set and start outputting high level at the start time of the second sub-period T2 when the second sub-period T2 arrives, the low data Q < M > -Q <0> in the second sub-period T2 is counted from all zeros and when the given gray data G < M > -G <0> is counted, the RS latch LAT is triggered to be reset and switched to output low level, i.e. the output of the comparator CMP2 is inverted. Note that in this embodiment, the low data Q < M > -Q <0> in the first sub-period T1 starts counting from all 0 until all 1 is counted, and the low data Q < M > -Q <0> after being counted fully means that the first sub-period T1 ends and the high data is carried once, and also marks the beginning of the second sub-period T2 and the low data Q < M > -Q <0> starts counting from all 0 again until all 1 is counted fully. The low bit data Q < M > -Q <0> after the second sub-period T2 expires means that the second sub-period T2 ends and the high bit data is again carried over, marking the beginning of the third sub-period T3 and the low bit data Q < M > -Q <0> again counts from all 0's until all 1's are counted. Finally, the low-order data Q < M > -Q <0> means that the third sub-period T3 ends and the high-order data is carried again after the third sub-period T3 is full, marking the beginning of the fourth sub-period T4 and the low-order data Q < M > -Q <0> again counts from all 0's until all 1's are full. This one cycle T is completed and the next cycle T is entered.
Referring to fig. 6, the respective TIME lengths of the sub-periods T1 to T4 are adjusted in such a manner that the frequencies of the clock signals CK1 to CK4 are adjusted to be high or low within the same TIME 1. T1 of fig. 6 is longer than fig. 5, T2 of fig. 6 is shorter than fig. 5 and T3 of fig. 6 is longer than fig. 5, T4 of fig. 6 is shorter than fig. 5, but t=t1+t2+t3+t4 is allowed to be unchanged. The driving scheme designed for primary light sources can thus flexibly allocate the primary colors even in the face of limited resolution and freely allocate the power duty cycle of the primary light sources within the cycle period T. This is because the frequency of the clock signal CK1 is made lower than that of fig. 5 in the T1 stage of fig. 6, and the frequency of the clock signal CK2 is made higher than that of fig. 5 in the T2 stage of fig. 6, and the frequency of the clock signal CK3 is made lower than that of fig. 5 in the T3 stage of fig. 6, and the frequency of the clock signal CK4 is made higher than that of fig. 5 in the T4 stage of fig. 6. This way of frequency conversion is very beneficial for freely distributing the respective luminance ratios of the primary light sources. For example, by changing the lighting time of the diodes of the primary colors of red, green and blue in the cycle period during color mixing, the brightness ratio of the light emitting diodes of each primary color is changed, and the relative brightness ratio of the three primary colors during color mixing is changed. For example, when the ratio of the red, green and blue primary colors is 3:6:1 in colorimetry, pure white is displayed, if the actual ratio deviates at any point, the deviation of white balance can occur, the phenomenon that white is bluish or yellowish green is generated is very easy, and the white balance can be easily realized by the frequency conversion mode.
Referring to fig. 7, the respective TIME lengths of the sub-periods T1 to T4 are adjusted in such a manner that the frequencies of the clock signals CK1 to CK4 are adjusted to be high or low within the same TIME 1. T1 of fig. 7 is half of fig. 5, T2 of fig. 7 is half of fig. 5 and T3 of fig. 7 is half of fig. 5, T4 of fig. 7 is half of fig. 5. The total time length T of fig. 7 is half of the total time length T of fig. 5. The total time length of the cycle period shared by the pulse width modulation signals can be flexibly adjusted.
Referring to fig. 8, the embodiment described in reviewing fig. 1 is equipped with multiple constant current cells CC1-CC4 and requires that a first light emitting diode LED1 be provided in series with its corresponding constant current cell CC1, a second light emitting diode LED2 be connected in series with its corresponding constant current cell CC2, and a third light emitting diode LED3 be provided in series with its corresponding constant current cell CC3, and a fourth light emitting diode LED4 be provided in series with the constant current cell CC 4. Each light emitting diode is connected with a corresponding constant current unit in series in a one-to-one manner, wherein when a pulse width modulation signal such as a first pulse width modulation signal corresponding to any light emitting diode such as the first light emitting diode LED1 has an effective logic level such as a high level, the any light emitting diode such as the first light emitting diode LED1 is turned on and the constant current unit such as the constant current unit CC1 connected in series with the any light emitting diode such as the first light emitting diode LED1 is turned on. The present embodiment claims to replace the embodiment of fig. 1 with a solution that can save the number of components and reduce the chip area. The original design method that each path of light emitting diode is connected with the corresponding path of constant current unit in series in a one-to-one mode is cancelled, the constant current unit CC1 is reserved as a matched common constant current unit, the total number of the constant current units is single, and other constant current units CC2-CC4 are abandoned. The new design scheme requires that each light emitting diode is connected in series with the common constant current unit, the first light emitting diode LED1 is connected in series with the common constant current unit CC1 through a first switch S1 corresponding to the light emitting diode LED1, the second light emitting diode LED2 is connected in series with the common constant current unit CC1 through a second switch S2 corresponding to the light emitting diode LED2, the third light emitting diode LED3 is connected in series with the common constant current unit CC1 through a third switch S3 corresponding to the light emitting diode LED3, and the fourth light emitting diode LED4 is connected in series with the common constant current unit CC1 through a fourth switch S4 corresponding to the light emitting diode LED 3. When the pulse width modulation signal corresponding to any one light emitting diode has an effective logic level, the common constant current unit CC1 is started and any one light emitting diode is switched to be connected in series with the common constant current unit CC1 to be lightened. The first switch S1 is turned on when the first pulse width modulation signal has an active logic level, for example, a high level, so that the common constant current unit CC1 is further enabled and the first light emitting diode LED1 is switched to be connected in series with the common constant current unit CC1 to be turned on. When the second pulse width modulation signal has an active logic level, for example, a high level, the second switch S2 is turned on, so that the common constant current unit CC1 is further enabled, and the second light emitting diode LED2 is switched to be connected in series with the common constant current unit CC1 and is turned on. When the third pulse width modulation signal has an active logic level such as a high level, the third switch S3 is turned on, so that the constant current unit CC1 is further enabled, and the third light emitting diode LED3 is switched to be in series with the common constant current unit CC1 and is turned on. When the fourth pulse width modulation signal has an active logic level such as a high level, the fourth switch S4 is turned on to further enable the constant current unit CC1 and the fourth light emitting diode LED4 is switched to be connected in series with the common constant current unit CC1 to be turned on. Each light emitting diode and the common constant current unit are coupled in series between the power input terminal and the potential reference terminal. Since the first to fourth switches are controlled by the first to fourth pulse width modulation signals, respectively, they are turned on in an active logic level, e.g., a high level state, and turned off in an inactive logic level, e.g., a low level state. Whether each path of light emitting diode flows through the constant current provided by the common constant current unit connected in series with the light emitting diode is still controlled by one path of pulse width modulation signal corresponding to the constant current, and the constant current lighting time of each path of light emitting diode in the period of the pulse width modulation signal is still determined by one path of pulse width modulation signal corresponding to the light emitting diode, so that the display effect obtained by the multi-path constant current unit and the common constant current unit with single quantity is completely the same.
Referring to fig. 8, the data transmission module DAT1 of the driving circuit configuration has a decoder for decoding input serial data according to a preset communication protocol and decoding gray data from received communication data, and the driving circuit adjusts gray scales of the respective light emitting diodes according to the gray data allocated to the respective light emitting diodes. If the constant current unit CC1 is set in a mode that the constant current is fixed, under any frame of communication data, the current flowing when any light emitting diode is turned on is held by the fixed constant current provided by the constant current unit CC1, the design is simpler and the constant current provided by the constant current unit does not need to be changed. When the last frame of communication data received by the driving circuit is refreshed to the next frame of communication data to adjust the respective gray data of the multiple light emitting diodes, the mixed color corresponding to the gray data decoded by the last frame of communication data is different from the mixed color corresponding to the gray data decoded by the next frame of communication data by taking the three-primary-color light source as an example, so that the power consumption of the three-primary-color light emitting diode under the condition of the last frame of gray data and the power consumption of the three-primary-color light emitting diode under the condition of the next frame of gray data have different conditions without doubt. The power consumption difference caused by different communication data frames may cause power waste if the constant current unit CC1 provides a fixed constant current, and the power waste phenomenon becomes more obvious as the number of driving circuits connected in cascade increases. Instead, as an alternative to the fixed constant current scheme, the programmable constant current unit CC1 is set in a mode in which the supplied constant current can be adjusted, and thus the magnitude of the constant current supplied to each led can be adjusted. Taking three primary color light sources as an example, the constant current is increased when the color mixing color is required to provide a larger constant current to match the display effect, and the constant current is decreased when the color mixing color is required to provide a smaller constant current to match the display effect. The data transmission module DAT1 of the driving circuit configuration is provided with a decoder, decodes the input serial data according to a preset communication protocol and decodes constant current regulation data from the received communication data, and the driving circuit regulates the magnitude of the constant current provided by the programmable constant current unit CC1 according to the constant current regulation data distributed to the constant current unit CC 1. It is obvious that the data transmission module DAT1 of the driving circuit configuration can decode various types of data with different purposes or meanings from the communication data, not just gray data.
Referring to fig. 8, embodiments of adjusting the magnitude of the constant current supplied from the constant current cell CC1 in setting the programmable constant current cell are diversified. The data Y < X > to Y <0> represent constant current regulation data which are distributed to the constant current unit CC1 after the driving circuit is decoded, and the natural number X representing the number of data bits is larger than 1. The constant current adjustment data is used for trimming the resistance value of the sampling resistor RS1/RS2 as shown in fig. 2-3, so that the purpose of adjusting the magnitude of the constant current provided by the constant current unit CC1 can be achieved. If the constant current regulation data is used for fine tuning the voltage value of the reference voltage VB1/VB2, the purpose of regulating the constant current value provided by the constant current unit CC1 can be achieved. Fig. 8 is provided with a single number of common constant current cells CC1, so that constant current adjustment data can be used to adjust the magnitude of the constant current supplied from the common constant current cells CC 1. The other constant current cells CC2-CC4 shown in fig. 1 may be configured as programmable constant current cells, except that the driving circuit needs to increase the storage capacity of a latch or a buffer for storing constant current adjustment data, because the amount of constant current adjustment data that the driving circuit needs to receive increases at this time, so that each constant current cell may be allocated with corresponding constant current adjustment data to adjust the magnitude of the constant current provided by each programmable constant current cell.
Referring to fig. 8, a shunt module SHU connected in parallel with the light emitting diodes LED1-LED4 serves to shunt and also stabilize the input voltage supplied to the driving circuit at a desired value. The circuit configuration implementing the basic functions of the shunt module SHU is likewise not unique but rather diverse. IN an alternative example, the shunt module SHU uses an NPN bipolar transistor, such as with a power supply input IN connected to the collector of the NPN bipolar transistor and a potential reference OUT connected to the emitter of the NPN bipolar transistor. And a zener diode is connected between the collector and the base of the NPN bipolar transistor, a resistor is connected between the base and the emitter of the NPN bipolar transistor, the cathode of the zener diode is connected to the collector of the NPN bipolar transistor, and the anode of the zener diode is connected to the base of the NPN bipolar transistor. A negative electrode of the voltage stabilizing tube is coupled to the power input terminal IN and a positive electrode of the voltage stabilizing tube is coupled to the potential reference terminal OUT to stabilize the input voltage of the driving circuit. IN alternative embodiments the shunt module SHU employs a PNP bipolar transistor such as with a power supply input IN coupled to the emitter of the PNP bipolar transistor and a potential reference OUT coupled to the collector of the PNP bipolar transistor. A zener diode is connected between the collector and the base of the PNP bipolar transistor, and a resistor is connected between the base and the emitter, and it is noted that the cathode of the zener diode is connected to the base of the PNP bipolar transistor, and the anode of the zener diode is connected to the collector of the PNP bipolar transistor, and the input voltage of the driving circuit is stabilized by a voltage stabilizing tube. The negative electrode of the regulator tube is connected to the power input terminal IN and the positive electrode of the regulator tube is coupled to the potential reference terminal OUT. The solution of the shunt module SHU is also diversified.
Referring to fig. 8, a shunt module SHU connected in parallel with the light emitting diodes LED1-LED4 uses an adjustable parallel voltage reference circuit ZT in the preferred embodiment. The adjustable parallel voltage reference circuit can be designed as a separate device and can be integrated into an integrated circuit as part of a functional module of a driver chip. The terms of an adjustable shunt reference voltage source or an adjustable precision shunt voltage regulator (Adjustable precision shunt regulator) or a programmable reference source circuit or a Three-terminal programmable shunt voltage regulator (Three-terminal programmable shunt regulator) or a programmable shunt voltage reference source are used for describing the adjustable shunt voltage reference circuit, but naming rules of different manufacturers or users are slightly different to cause inconsistent terms. Controllable precision voltage stabilizing sources TL431 and TL432 are the most common type of electronic components of an adjustable parallel voltage reference circuit. The adjustable parallel voltage Reference circuit is generally considered to have three terminals and is named Cathode C (captode) and Anode a (Anode) and Reference terminal R (Reference), respectively. The simple scheme is that each path of light emitting diode and one path of constant current unit are coupled in series between a power input end and a potential reference end. The light emitting diode LED1 and the constant current unit CC1 are connected IN series between the power input terminal IN and the potential reference terminal OUT as shown IN fig. 1, the light emitting diode LED2 and the constant current unit CC2 are connected IN series between the power input terminal IN and the potential reference terminal OUT, the light emitting diode LED3 and the constant current unit CC3 are connected IN series between the power input terminal IN and the potential reference terminal OUT, and the light emitting diode LED4 and the constant current unit CC4 are connected IN series between the power input terminal IN and the potential reference terminal OUT so as to directly supply power to the light emitting diodes by using the input voltage at the power input terminal IN, and the shunt module SHU may also be connected IN series between the power input terminal IN and the potential reference terminal OUT. However, this is by no means the only option, since the divided voltage of the input voltage at the power supply input IN can also supply the individual leds, it being possible IN alternative embodiments for each led and the corresponding constant current unit to be coupled IN series between the divided voltage of the input voltage and the potential reference, a shunt module SHU connected IN parallel with the leds and a bypass module described below being arranged to be coupled between the divided voltage of the input voltage and the potential reference. IN other embodiments, a stabilized voltage obtained by performing voltage conversion of an input voltage provided at the power input terminal IN, such as a linear voltage, a switch voltage, or a charge pump voltage, may be used to power each led, each led and a corresponding constant current unit are serially coupled between the stabilized voltage obtained by voltage conversion and a potential reference terminal, and a shunt module SHU connected IN parallel to the leds and a bypass module described later are also coupled between the stabilized voltage obtained by voltage conversion and the potential reference terminal. Embodiments of using the divided voltage of various forms of the input voltage as the power supply voltage of each led or using the stabilized voltage obtained by performing the linear or switching voltage conversion using the input voltage as the power supply voltage of each led are not described in the drawings for brevity. Therefore, the serial connection structure, the shunt module and the bypass module which are described below after the light emitting diode and the constant current unit are connected in series can meet the parallel connection relation, so that the parallel connection of the three components between the power input end and the potential reference end or between other two nodes with potential difference is allowed. For example, if the first node and the second node have a higher potential than the second node and have a potential difference, the same functions of constant current control, current division, voltage stabilization, etc. can be achieved by connecting the first node and the second node in parallel, and it should be understood that the three are connected in parallel between the power input terminal and the potential reference terminal in the drawings by way of illustration only and not limitation.
Referring to fig. 8, a driving circuit is an example of a driving chip IC. Each light emitting diode and the common constant current unit are coupled IN series between the power input terminal IN and the potential reference terminal OUT, and the shunt module SHU is also coupled between the power input terminal IN and the potential reference terminal OUT as a parallel structure thereof. The shunt module SHU optionally contains an adjustable parallel type voltage reference circuit ZT and the cathode C is coupled to the power supply input IN through a resistor or not, and the anode a of the adjustable parallel type voltage reference circuit ZT is also provided to be coupled to the potential reference terminal OUT. The resistor divider VD cooperates with an adjustable parallel voltage reference circuit ZT, the reference terminal R of which is coupled to the voltage dividing node of the resistor divider, i.e. to the interconnection of both resistors IN the resistor divider, which is also connected between the power supply input terminal IN and the potential reference terminal OUT.
Referring to fig. 9, when the first to third pulse width modulation signals DR and DG and DB described above are used, a single period time T of the pulse width modulation signals is divided into three sub-periods, and an effective logic level of each pulse width modulation signal is allocated in a corresponding one of the sub-periods. The result of the nor operation performed by the pwm signals DR and DG and DB is regarded as the control signal DX of the bypass module, and when the control signal DX has an active logic level, such as a high level, the bypass module is triggered to be turned on and the multiple leds are shunted. In an alternative example the shunt current of the bypass module is determined by the constant current cell CC1 as described in fig. 9-10 or the shunt current is determined by the constant current cell CC5 as described in the fig. 11 scheme. The bypass module in fig. 9 comprises a constant current cell CC1 and a resistor RX in series with it. The bypass module of fig. 10 comprises a constant current unit CC1 and a diode LED5 connected in series therewith. The bypass module in fig. 11 comprises a constant current cell CC5 and a resistor RX in series with it.
Referring to fig. 9, the current regulation data allocated to the subsequent current source module PCS is used to set the output current IT of the constant current source of the current source module PCS in the same frame of communication data, a part of the constant current regulation data allocated to the driving circuit is used to set at least the value of the constant current I1 of the constant current cell CC1 in fig. 9 or 10, or a part of the constant current regulation data allocated to the driving circuit is used to set the value of the constant current I5 supplied from the constant current cell CC5 in fig. 11. Taking the driving circuits for driving the first to third light emitting diodes LED1 to LED3 as an example, the result of performing the nor operation on the pulse width modulation signals DR and DG and DB is regarded as the control signal DX of the bypass module. The bypass module is turned on during all of the periods when the control signal has the high level XH, the low level period of the first path of pulse width modulation signal DR causes the control signal DX to be high level during the first sub-period T1, the low level period of the second path of pulse width modulation signal DG causes the control signal DX to be high level during the second sub-period T2, and the low level period of the third path of pulse width modulation signal DB causes the control signal DX to be high level during the third sub-period T3. In this example, the driving circuit only drives three leds, and the total time period of the cycle period T is t1+t2+t3. The input terminals of the nor gate 300 are respectively inputted with the first to third pulse width modulation signals DR, DG and DB, and the control signal DX outputted from the nor gate 300 is used to control whether the bypass module is turned on or not. The shunt current determined by the constant current unit CC1 or the shunt current determined by the constant current unit CC5 in the case that the bypass module is defined to be turned on does not exceed the output current of the constant current source in the current source module PCS.
Referring to fig. 1, in view of that the first to fourth light emitting diodes LED1 to LED4 are sequentially turned on when they are arranged so that their turn-on times do not overlap, it is possible to define that the current flowing through each light emitting diode does not exceed the output current of the constant current source in the current source module. The first sub-period T1 defines that the current I1 flowing through the first light emitting diode LED1 does not exceed the output current IT determined by the current source module. And limiting the current I2 flowing by the second light emitting diode LED2 in the second sub-period T2 not to exceed the output current IT determined by the current source module. The third sub-period T3 likewise defines that the current I3 flowing through the third light-emitting diode LED3 does not exceed the output current IT determined by the current source module. And the current I4 flowing through the fourth light emitting diode LED4 set in the fourth sub-period T4 is also satisfied not to exceed the output current IT of the current source module. In the exemplary embodiment of fig. 1, the currents I1 to I4 flowing when the first to fourth light-emitting diodes LED1 to LED4 are each switched on are each supplied by a constant current unit CC1 to CC 4. In the alternative embodiment shown in fig. 9, the currents I1-I3 flowing through the first to third light emitting diodes LED1-LED3 are provided by the constant current unit CC1, and the current of the load resistor RX of the bypass module is provided by the constant current unit CC 1.
Referring to fig. 9, the main difference between the present embodiment and the embodiment in fig. 1 is that a bypass module is added and the new design requires that each led be connected in series with the common constant current unit. The first path of light emitting diode LED1 is connected with the common constant current unit CC1 in series through a first switch S1 corresponding to the first path of light emitting diode LED, the second path of light emitting diode LED2 is connected with the common constant current unit CC1 in series through a second switch S2 corresponding to the second path of light emitting diode LED, and the third path of light emitting diode LED3 is connected with the common constant current unit CC1 in series through a third switch S3 corresponding to the third path of light emitting diode LED. The load resistor RX of the bypass module is connected in series with the common constant current unit CC1 through a fifth switch S5 corresponding thereto. When the pulse width modulation signal corresponding to any one light emitting diode has an effective logic level, the common constant current unit CC1 is started, and any one light emitting diode is switched to be connected with the common constant current unit CC1 in series to be lightened. When the first pulse width modulation signal has an active logic level, for example, a high level, the first switch S1 is turned on, so that the common constant current unit CC1 is further enabled, and the first light emitting diode LED1 is switched to be connected in series with the common constant current unit CC1 to be turned on. When the second pulse width modulation signal has an active logic level, for example, a high level, the second switch S2 is turned on, so that the common constant current unit CC1 is further enabled, and the second light emitting diode LED2 is switched to be connected in series with the common constant current unit CC1 and is turned on. When the third pulse width modulation signal has an active logic level such as a high level, the third switch S3 is turned on, so that the constant current unit CC1 is further enabled, and the third light emitting diode LED3 is switched to be in series with the common constant current unit CC1 and is turned on. Each path of light emitting diode and the common constant current unit are coupled in series between the power input end and the potential reference end, and the load resistor and the common constant current unit in the bypass module are coupled in series between the power input end and the potential reference end. The bypass module is connected with the multiple light emitting diodes in parallel, and the result of the NOR logic operation performed by the multiple pulse width modulation signals is regarded as the control signal of the bypass module. The first to third pulse width modulation signals DR, DG and DB are respectively input to the plurality of input ends of the nor gate 300, and the result DX obtained by performing the nor operation on the first to third pulse width modulation signals is used to control whether the fifth switch S5 is turned on or not and regards the fifth switch S5 as a control signal, and whether the bypass module is turned on or not is shunted depending on the logic state of the control signal DX.
Referring to fig. 9, the bypass module is triggered to shunt the total input current of the driving circuit if the control signal DX is at an active logic level value, such as a high level. For example, the control signal DX turns on the fifth switch S5 when it is at an active logic level or turns off the fifth switch S5 when it is at an inactive logic level, such as a low level. The bypass module in this example comprises a load resistor RX and a fifth switch S5 and a common constant current unit CC1 associated therewith. The bypass module is not the only example in circuit configuration, for example, a conventional diode capable of being conducted in the forward direction is used instead of the load resistor RX, and it should be noted that the anode of the conventional diode should be coupled to the power input terminal and the cathode should be coupled to the constant current unit. Or the load resistor RX and the conventional diode are connected in series and then connected in series with the constant current unit CC1 between the power input end and the potential reference end, the positive electrode of the conventional diode is required to be directly or indirectly coupled to the power input end, and the negative electrode of the conventional diode is required to be directly or indirectly coupled to the constant current unit. It is even possible to connect the conventional diode in parallel with the load resistor RX before coupling them in series with the constant current cell CC1 between the power supply input terminal and the potential reference terminal, also note that the positive pole of the conventional diode should be coupled to the power supply input terminal and the negative pole should be coupled to the constant current cell. In other alternative embodiments of the bypass module, the load resistor RX may be replaced by a mosfet in the form of a diode connection, or by a bipolar transistor in the form of a base-collector, i.e. a passive load similar to the load resistor RX may be replaced by an active load. The connection mode of the active load is set as follows when the active load is coupled with the constant current unit CC1 in series in the bypass module: the fifth switch S5 should immediately switch on as soon as it is controlled by the control signal to conduct and create a voltage drop across the active load. In other words, as long as any type of load is arranged in the bypass module and connected in series with the constant current unit CC, the control signal DX can trigger the bypass module to be turned on and split the total input current of the driving circuit when an effective logic level exists, and at this time, the active load or the passive load contained in the bypass module can flow through the constant current provided by the constant current unit CC1. The bypass module can be considered to be a preset constant value of the shunt current flowing when the bypass module is connected to the shunt.
Referring to fig. 10, the bypass module includes a common constant current unit CC1 and a load connected in series thereto, and the diode LED5 may include a light emitting diode such as a white light emitting diode or a conventional diode that does not emit light as a load. The bypass module in fig. 9 comprises a common constant current cell CC1 and a load, i.e. a resistor RX, in series with it. The bypass module in fig. 11 comprises a non-common but independent constant current cell CC5 and a load, i.e. a resistor RX, in series therewith.
Referring to fig. 11, the main difference between the present embodiment and fig. 10 is that the multiple light emitting diodes and the bypass module, each of which is equipped with a constant current unit, no longer share the same common constant current unit CC 1. The new design requires that each light emitting diode and the corresponding constant current unit are connected in series. The first path of light emitting diode LED1 and the corresponding constant current unit CC1 are connected in series between the power input end and the potential reference end, the second path of light emitting diode LED2 and the corresponding constant current unit CC2 are connected in series between the power input end and the potential reference end, and the third path of light emitting diode LED3 and the corresponding constant current unit CC3 are connected in series between the power input end and the potential reference end. The load resistor RX and the corresponding constant current unit CC5 of the bypass module are connected in series between the power input end and the potential reference end. When the pulse width modulation signal corresponding to any one light emitting diode has an effective logic level, the constant current unit connected in series is started, and when the control signal DX has an effective logic level, the constant current unit connected in series by the load resistor RX is started. The constant current cell CC1 is enabled when the first pulse width modulated signal exhibits an active logic level, e.g. a high level, and the first light emitting diode LED1 is illuminated by receiving a constant current from the constant current cell CC1 connected in series therewith. The second pulse width modulated signal is enabled when an active logic level, e.g. a high level, is present and the second light emitting diode LED2 is illuminated by receiving a constant current from the constant current cell CC2 connected in series therewith. The third pulse width modulation signal is enabled when an active logic level, e.g. a high level, is present and the third light emitting diode LED3 is illuminated by receiving a constant current from the constant current unit CC3 connected in series therewith. An alternative case in which the constant current cell CC5 of the bypass module is turned on or off is described in the example of the constant current cell CC1 in fig. 2. A controlled switch, not shown, is provided between the output of the error amplifier EA1 of the constant current cell CC5 and the control terminal of the transistor MQ, and a control signal DX may be used to control the conduction of this controlled switch, the controlled switch being turned on if the control signal DX has an active logic level, such as a high level, and further causing the constant current cell CC5 to be enabled and the load resistor RX to flow through the constant current provided by the constant current cell CC5, whereas the controlled switch is turned off if the control signal DX has an inactive logic level, such as a low level. The first to third pulse width modulation signals DR, DG and DB are respectively input to the plurality of input terminals of the nor gate 300, and the result DX obtained by performing the nor operation on the first to third pulse width modulation signals is used to control the conduction of the constant current unit CC 5.
Referring to fig. 12, the foregoing describes that the multi-bit count data output by the counter CNT includes specified high-order data and specified low-order data, and the specified low-order data includes Q < M > -Q <0>. The digital value Q <0> in the combinational logic circuit LG outputs a pulse signal O < M > through a buffer BF as shown. Let Q < M > be the inverse of QN < M >, i.e., any value Q is defined herein as QN after being inverted. In the combinational logic circuit, Q <0> is inverted by the inverter IV to obtain both QN <0> and Q <1>, which are input to the AND gate A1 and the AND gate A1 to output the pulse signal O < M-1>. In the combinational logic circuit, values Q <2> and QN <1> and QN <0> are inputted to the AND gate A2, so that the AND gate A2 can output the pulse signal O < M-2>. In the combinational logic circuit, values Q <3> and QN <2> and QN <1> and QN <0> are inputted into the other AND gate A3, so that the AND gate A3 outputs the pulse signal O < M-3>. In the combinational logic circuit, QN < M-1>, QN < M-2>, QN < M-3>, … … QN <0> and the value Q < M > are input to the AND gate AM shown in the figure according to the same principle, and the sum of M pieces of inversion data from QN < M-1> to QN <0> and the value Q < M > is input to the AND gate AM shown in the figure, so that the AND gate AM can output the pulse signal O <0>. Finally, m+1 so-called pulse signals, i.e., a series of pulse signals from O < M > to O <0>, can be obtained. The series of M+1 groups of pulse signals can be provided for a plurality of pulse width modulation modules, and each pulse width modulation module forms a corresponding pulse width modulation signal according to gray data matched with one light emitting diode matched with the pulse width modulation module and the series of pulse signals O < M > to O <0>.
Referring to fig. 12, taking gray data R < M > -R <0> of a red light source as an example: in this example, the data R < M > AND the pulse signal O < M > are input to the first AND gate AND. AND the data R < M-1> AND the pulse signal O < M-1> are input to the other second AND gate AND. Data R < M-2> AND pulse signal O < M-2> are input to the third AND gate AND, AND so on, data R < M-3> AND pulse signal O < M-3> are input to the fourth AND gate AND. AND so on in the same principle until the data R <0> AND the pulse signal O <0> are input to the m+1th AND gate AND. Together m+1 AND gates AND they output the m+1 group of phase-results in total. The outputs of the first to m+1th AND gates AND are each fed to an OR gate OR shown in the figure, AND the output of the OR gate OR is regarded as the first pulse width modulation signal DR of the red light source. The light sources of other colors can also obtain the second and third pulse width modulation signals DG-DB by this mode. The principle of generating the pulse width modulation signal is to form M+1 sets of pulse signals, i.e., O <0>, O <1>, O <2>, … … O < M >, and then select whether to mask the pulse signals by using gray scale data R < M > -R <0>, such as red light source: if the data R <0> is taken 0 then the pulse signal O <0> is masked and the data R <0> is taken 1 then the pulse signal O <0> is not masked, if the data R <1> is taken 0 then the pulse signal O <1> is not masked and if the data R <1> is taken 1 then the pulse signal O <2> is masked and if the data R <2> is taken 1 then the pulse signal O <2> is not masked, and by analogy with the same principle if the data R < M > is taken 0 then the pulse signal O < M > is masked and if the data R < M > is taken 1 then the pulse signal O < M > is not masked. The first pulse width modulation signal DR representing the duty ratio information carried by the gray data R < M > -R <0> is obtained by selecting whether the pulse signals O <0>, O <1>, O <2>, … … O < M > are outputted from the OR gate OR by the shielding gating action of the gray data R < M > -R <0> of the red light source.
Referring to fig. 13, in an alternative embodiment, multiple light emitting diodes such as tricolor light sources and white light correspond to multiple pulse width modulation signals such as first through fourth pulse width modulation signals DR and DG and DB and DW. The cycle time T of the pulse width modulation signals is divided into a plurality of sub-periods, such as a first sub-period and a second sub-period and a third sub-period and a fourth sub-period, and at the same time, the effective logic level, such as a high level, of each pulse width modulation signal can be allocated in a corresponding sub-period. For example, the active logic high level of the first pulse width modulation signal DR may be allocated in the corresponding first sub-period T1, the active logic high level of the second pulse width modulation signal DG may be allocated in the corresponding second sub-period T2, the active logic high level of the third pulse width modulation signal DB may be allocated in the corresponding third sub-period T3, and the active logic high level of the fourth pulse width modulation signal DW may be allocated in the corresponding fourth sub-period T4. In connection with the embodiments of fig. 9-10 and 11, it is provided that the first to fourth pulse width modulation signals DR and DG and DB and DW are input to several input terminals of the nor gate 300, respectively, and the first to fourth pulse width modulation signals DR and DG and DB and DW are subjected to nor operation to obtain the control signal DX. The control signal DX output from the nor gate 300 controls whether the fifth switch S5 of fig. 9-10 is turned on or not, and controls whether the constant current unit CC5 shown in fig. 11 is turned on or not. The bypass module is triggered to turn on when an active logic level of the control signal DX occurs, such as a high level. For example, the control signal DX is high when the low level period of the first pulse width modulation signal DR appears in the first sub-period T1, the control signal DX is high when the second pulse width modulation signal DG appears in the second sub-period T2, the control signal DX is high when the third pulse width modulation signal DB appears in the third sub-period T3, and the control signal DX is high when the fourth pulse width modulation signal DW appears in the fourth sub-period T4. The high XH represents the waveform of the control signal DX at an active logic value such as high level, and the high XH period of the control signal DX causes the bypass module to conduct and shunt. The effective logic values of each pulse width modulation signal within the corresponding sub-period are arranged in a continuous manner: the effective logic values of the first pulse width modulation signal DR in T1 are arranged in a continuous manner, the effective logic values of the second pulse width modulation signal DG in T2 are arranged in a continuous manner and the effective logic values of the third pulse width modulation signal DB in T3 are arranged in a continuous manner, and the effective logic values of the fourth pulse width modulation signal DW in T4 are arranged in a continuous manner.
Referring to fig. 14, the example of fig. 12 may enable the effective logic values of the first pulse width modulated signal DR, i.e., SRH, within the first sub-period T1 to be arranged in a distributed manner. The effective logic values SGH of the second pulse width modulation signal DG in T2 may also be arranged in a decentralized manner, the effective logic values SBH of the third pulse width modulation signal DB in T3 may also be arranged in a decentralized manner, and the effective logic values SWH of the fourth pulse width modulation signal DH in T4 may also be arranged in a decentralized manner. In contrast to fig. 13-14, fig. 14 essentially breaks up a pulse width modulated signal having an effective logic value that is continuous into several shorter discrete or discrete effective logic values. For example, the continuous-type effective logic value RH of the first pulse-width modulation signal DR in fig. 13 may be broken up into several shorter discrete-type effective logic values SRH of the first pulse-width modulation signal DR in fig. 14, where the duty cycle of the continuous-type effective logic value RH is still equal to the duty cycle of the discrete-type effective logic value SRH. The continuous active logic value GH of the second pulse width modulated signal DG is broken up into a number of shorter discrete active logic values SGH. The continuous valid logic value BH of the third pulse width modulation signal DB breaks up into several discrete valid logic values SBH. The continuous effective logic value WH of the fourth pulse width modulation signal DW breaks up into several discrete effective logic values SWH. Note that the distributed pwm signals DR and DG and DB and DW in fig. 14 still perform a nor operation, and the operation result is regarded as the control signal DX of the bypass module connected in parallel to the multiple leds, and the control signal DX triggers the bypass module to conduct and implement the shunt when a valid logic value occurs. The control signal DX output from the nor gate 300 controls whether the fifth switch S5 in fig. 9 to 10 is turned on or not, and can control whether the constant current unit CC5 shown in fig. 11 is turned on or not. The control signal triggers the bypass module to turn on when an active logic level occurs, such as a high level. For example, the control signal DX is high when the low level period of the first pulse width modulation signal DR appears in the first sub-period T1, the control signal DX is high when the second pulse width modulation signal DG appears in the second sub-period T2, the control signal DX is high when the third pulse width modulation signal DB appears in the third sub-period T3, and the control signal DX is high when the fourth pulse width modulation signal DW appears in the fourth sub-period T4. The high XH represents the waveform when the control signal DX is at an active logic value, such as a high level, and the occurrence of the high XH on the control signal DX causes the bypass module to conduct and shunt. The effective logic values of the pulse width modulated signal within the respective sub-period are arranged in a discrete manner: the effective logic values of the first pulse width modulation signal DR in T1 are arranged in a discrete manner, the effective logic values of the second pulse width modulation signal DG in T2 are arranged in a discrete manner and the effective logic values of the third pulse width modulation signal DB in T3 are arranged in a discrete manner, and the effective logic values of the fourth pulse width modulation signal DW in T4 are arranged in a discrete manner. The high level of the pulse width modulation signal is scattered into a plurality of shorter high levels, the sum of the scattered high levels is equal to the high level before scattering, and the sum of the scattered high level duty ratios is equal to the duty ratio before scattering, which belongs to the image enhancement technology of the Scrambled-PWM. The application of the method can lead the display system to have finer pictures and higher-level color gray scales: the design concept is that the original pulse width signal is broken into a plurality of small secondary pulse width signals or sub pulse width signals on the premise of not changing the duty ratio of the original pulse width signal, and the duty ratio of each small secondary pulse width signal or sub pulse width signal is identical to the duty ratio of the original integral pulse width signal.
Referring to fig. 14, the duty ratio of the effective logic value, SRH, in the first sub-period T1 in fig. 14 is substantially equal to the duty ratio of the effective logic value, RH, in the first sub-period T1 in fig. 13. As can be seen in the same way in fig. 14, the duty cycle of the valid logic value, SGH, in the second sub-period T2 is substantially equal to the duty cycle of the valid logic value, GH, in the second sub-period in fig. 13. The duty cycle of the effective logical value, SBH, in the third sub-period T3 in fig. 14 is also substantially equal to the duty cycle of the effective logical value, BH, in the third sub-period T3 in fig. 13. The duty cycle of the effective logic value SWH in the fourth sub-period T4 in fig. 14 is equivalent to the duty cycle of the effective logic value WH in the fourth sub-period T4 in fig. 13. In this example, the discrete control signal DX controls whether the bypass module is turned on or not, and the result of performing the nor operation on the pulse width modulation signal DR-DW is defined as the control signal DX. The bypass module was also found to have an extremely high on-off frequency compared to fig. 13: because the longer high-level valid logic values of the control signal DX in fig. 13 are also broken up into discrete valid logic values of fig. 14. The effective logic values of the control signals for each sub-period in fig. 14 can be considered to be arranged in a decentralized manner, while the effective logic values of the control signals for each sub-period in fig. 13 are arranged in a continuous manner. The current of the bypass module in the case of switching on the shunt is a preset constant value. If the load of the bypass module is a light emitting diode, such as diode LED5 of fig. 10, it is of great benefit that the control signal DX is broken up to be set to a number of discrete valid logic values. Since the display refresh rate of the LED5 is correspondingly increased, if the load diode LED5 of the bypass module is in the off or on state as shown in fig. 13 for a long time, the screen displayed in visual sense will exhibit a flickering phenomenon, and the discrete control signal can increase the screen refresh rate and avoid the phenomenon.
Referring to fig. 15, the counter CNT is configured with a data selector MUX to which a plurality of clock signals CK1-CK3 allocated for a plurality of sub-periods T1-T3 are input. The designated high-order data is regarded as a channel selection signal of the data selector MUX, and the high-order data Q < M+1> -Q < M+2> is regarded as a channel selection signal SL1/SL2 or address code input of the data selector. If the high-order data Q < M+1> -Q < M+2> is 00, the data selector MUX is triggered to switch to the output clock signal CK1, if the high-order data Q < M+1> -Q < M+2> is 01, the data selector MUX is triggered to switch to the output clock signal CK2, and if the high-order data Q < M+1> -Q < M+2> is 10, the data selector MUX is triggered to switch to the output clock signal CK3. The high-order data is caused to carry once from the initial 00 to 01 after the first period T1 is finished, and the high-order data is caused to carry from 01 to 10 after the second period T2 is finished. After the specified low-order data Q < M > -Q <0> is counted from all 0 to all 1 in each cycle period T, the operation of carrying out carry once is triggered to cause the specified high-order data Q < M+1> -Q < M+2>, and the data selector is triggered to switch and output different clock signals. For example, three states of Q < m+1> -Q < m+2>, i.e., three channel selection signals, map different clock signals CK1-CK3 output by the data selector, whereby a corresponding one of the clock signals can be allocated for each sub-period of time T1-T3 and used to trigger the counter CNT to count. In this embodiment, only three leds of the primary colors red, green and blue are used, so that the cycle period t=t1+t2+t3, and the three states of different channel selection signals, such as high-order data, are mapped to the data selector to output three different clock signals.
Referring to fig. 15, the embodiment is also designed to satisfy the time length of each sub-period to be counted by the clock signal trigger counter matched with the sub-period: the first sub-period T1 is counted by the clock signal CK1 triggering the counter CNT, the second sub-period T2 is counted by the clock signal CK2 triggering the counter CNT, and the third sub-period T3 is counted by the clock signal CK3 triggering the counter CNT. The generation mechanism of the pulse width modulated signal in this embodiment is different from that of fig. 4. The specified low bit data Q < M > -Q <0> within the first sub-period T1 is reordered according to the low to high weight rule to obtain inverted data Q <0> -Q < M >. It is understood that the original weight of the low bit data Q [ M:0] is ordered from high to low but the reverse order data is Q [0:M ] if reordered according to the rule of weights from low to high. Taking the lower data of the eight-bit data 01001010 as an example, its weight is from high to low, but if reordered according to the rule of weight from low to high, so-called reverse order data 01010010 can be obtained. Taking the four-bit low-bit data 1010 as an example, its original weight is from high to low but if reordered according to the rule of weight from low to high, the reverse order data 0101 is obtained. The low bit data Q < M >, Q < M-1>, Q < M-2>, … … Q <0>, i.e., Q [ M:0], may be considered to be reordered according to the reverse order rule to obtain reverse order data Q <0>, Q <1>, Q <2>, … … Q < M-1>, Q < M > denoted as Q [0:M ], according to the low to high weight rule.
Referring to fig. 15, the data comparator CMP10 carried by the corresponding first pulse width modulation module PWM1 compares the gray-scale data R [ M:0] matched to the red light emitting diode paired with PWM1 during the first sub-period T1 with the reverse-order data Q [0:M ] during the first sub-period T1: this results in the first pulse width modulated signal DR having an active logic value, such as a high level, when the inverted data Q [0:M ] is lower than the gray data R [ M:0] of the red light source, otherwise the first pulse width modulated signal DR is a low level of inactive logic. Since the reverse order data Q [0:M ] does not grow as well as low order data is from small to large, the reverse order data Q [0:M ] may have larger values and smaller values over time. In other words, with the clock signal CK1 counted up to a few, the inverted data Q [0:M ] may be higher than the gray-scale data of the red light source as well as lower than the gray-scale data of the red light source, such that the effective logic value of the first pulse width modulated signal DR naturally appears as a discrete distribution within the corresponding first sub-period T1.
Referring to fig. 15, the gray data G [ M:0] matched with the green light emitting diode paired with PWM2 is compared with the reverse data Q [0:M ] in the second sub-period T2 by the data comparator CMP20 carried by the corresponding second pulse width modulation module PWM2 in the second sub-period T2: this results in the second pulse width modulation signal DG having an active logic value, e.g. high, when the inverted data Q0:M is lower than the gray data gm: 0 of the green light source, otherwise the second pulse width modulation signal DG is not active logic low. With the clock signal CK2 counted up to a few, the inverted data Q0:M may be higher than the gray data of the green light source and lower than the gray data of the green light source, and the effective logic value of the second pulse width modulation signal DG in the second sub-period T2 naturally appears as a discrete distribution.
Referring to fig. 15, the gray data B [ M:0] matched with the blue light emitting diode paired with PWM3 is compared with the reverse data Q [0:M ] in the third sub-period T3 by the data comparator CMP30 carried by the corresponding third pulse width modulation module PWM3 in the third sub-period T3: this may result in the third pulse width modulation signal DB having an active logic value such as a high level when the reverse order data Q0:M is lower than the gray data G M0 of blue light emission, otherwise the third pulse width modulation signal DB is a low level of inactive logic. With the clock signal CK3 counted up to a few, the inverted data Q0:M may be higher than both the gray data of the blue light source and the gray data of the blue green light source, and the effective logic value of the third pulse width modulated signal DB in the third sub-period T3 naturally appears as a discrete distribution.
Referring to fig. 15, according to this embodiment, the effective logic values of the first pulse width modulation signal DR in T1 may be arranged in a scattered/scattered manner, and the effective logic values of the second pulse width modulation signal DG in T2 may be arranged in a scattered/scattered manner, and the effective logic values of the third pulse width modulation signal DB in T3 may be arranged in a scattered/scattered manner. The discrete waveforms of the pulse width modulated signal are similar to those of fig. 14 but the implementation mechanism is different.
Referring to FIG. 15, the driving circuit includes one of PWM modules PWM1-PWM3, wherein the PWM module PWM1 generates a corresponding PWM signal DR according to gray-scale data R [ M:0] of the LED, such as red light source. Claims to discard PWM2-PWM3 and discard blue light sources and green light sources. A pulse width modulated signal such as DR may be used to drive the red light source for display control. The pulse width modulation module PWM1 is configured with a counter such as CNT in the figure and a data comparator such as CMP10 in the figure. In this example there is only a first period T1 but no second and third periods and the loop period t=t1 is assumed. The counter is triggered by a clock signal such as CK1 to count and obtain a count value Q [ M:0] for the first time period T1. The original count value Q [ M:0] is reordered according to the rule of weight from low to high to obtain the reverse order data Q [0:M ]. The pulse width modulation module PWM1 sends the gray data R [ M:0] matched with the light source and the reverse sequence data Q [0:M ] into the data comparator CMP10 for comparison: the pulse width modulation signal DR is a high logic value when the reverse order data Q0:M is lower than the gray scale data RM: 0, otherwise the pulse width modulation signal DR has a low inactive logic value. The count value is also called count data. The effective logic value at this point appears as a number of discrete high levels.
Referring to fig. 16, according to the embodiment of fig. 15, assuming that the number of clocks of the clock signal CK2 in the second sub-period T2 is 256 from 0 to 255, that is, the preset value of the clock signal in the second sub-period T2 is 256, m=7 and each sub-period is counted 256 times in total, the gradation data has the inverted data Q [0:7] of the comparison object. In the first embodiment, when the gray scale data of the green light source is G [7:0] =00000010, the actual waveform of the second pulse width modulation signal DG1 is shown as the second pulse width modulation signal has an effective logic value only when Q [0:7] =000000000000 or Q [0:7] =00000001, and Q [0:7] has 256 values in total, and Q [0:7] is not lower than G [7:0] in the remaining other 254 values of Q [0:7]. In the second embodiment, when the gray scale data of the green light source is G [7:0] = 00011101, the second pulse width modulation signal DG2 is a valid logic value when Q [0:7] is lower than G [7:0], and otherwise the second pulse width modulation signal is a non-valid logic value. In the third embodiment, when the gray scale data of the green light source is G [7:0] =01001111, the second pulse width modulation signal DG3 is a valid logic value when Q [0:7] is lower than G [7:0], and the second pulse width modulation signal is a non-valid logic value otherwise. In the fourth embodiment, when the gray scale data of the green light source is G [7:0] =01111111, the second pulse width modulation signal DG4 is a valid logic value when Q [0:7] is lower than G [7:0], and the second pulse width modulation signal is a non-valid logic value otherwise. In the fifth embodiment, when the gray scale data of the green light source is G [7:0] =11101000, Q [0:7] is lower than G [7:0], the second pulse width modulation signal DG5 is a valid logic value, and otherwise the second pulse width modulation signal is a non-valid logic value. According to this embodiment, the effective logic values of the second pulse width modulation signals DG1-DG5 generated by the second pulse width modulation module PWM2 are shown as discrete distribution in the corresponding second sub-period T2.
Referring to fig. 17, each pulse width modulation module outputs a dithering signal having an effective logic value once every several cycle periods, whereby the duty cycle average value of each pulse width modulation signal in several of the cycle periods is adjusted by the dithering signal. For example, the pulse width modulation module PWM1 outputs the dither signal RD having an effective logic value once every time TX, the time TX is equal to a number of cycle periods T, for example, the time TX is equal to 4 or 8 or 16 cycle periods T. The DITHER technique is attributed to the functionality of the DITHER digital pulse width modulation DPWM. The pulse width modulation module PWM2 outputs the dither signal GD having an effective logic value once every time TX, and the pulse width modulation module PWM3 outputs the dither signal BD having an effective logic value once every time TX. Whereby the average value of the duty cycle of each pwm signal over a number of cycles is adjusted by the dither signal. The average value of the duty cycle of the first pulse width modulation signal DR in the time TX is adjusted by the dithering signal RD, the average value of the duty cycle of the second pulse width modulation signal DG in the time TX is adjusted by the dithering signal GD, and the average value of the duty cycle of the third pulse width modulation signal DB in the time TX is adjusted by the dithering signal BD.
Referring to fig. 17, the above is that the effective logic values of each pulse width modulation signal in a corresponding one of the sub-periods are arranged in a continuous manner. The effective logic values in the examples of fig. 5-7 and 13, for example, are arranged in a continuous manner. Any pulse width modulation module outputs a dither signal: if the effective logic values of the pulse width modulation signals are arranged in a continuous mode, the jitter signals are output immediately after the effective logic values of the pulse width modulation signals generated by any pulse width modulation module are finished. In an alternative example, when the effective logic value RH of the first pulse width modulation signal DR in the T1 is over, the pulse width modulation module PWM1 outputs the jitter signal RD immediately after the effective logic value RH of the first pulse width modulation signal DR is over, the jitter signal RD is also distributed in the first sub-period T1, and the time length of the jitter signal RD may be set to be equal to the cycle time of one clock signal CK1 itself. In an alternative example, the pulse width modulation module PWM2 outputs the wobble signal GD immediately after the second pulse width modulation signal DG has an active logic value GH at T2, the wobble signal GD is distributed in the second sub-period T2 and the period of the wobble signal GD is set to be equal to the period of the clock signal CK2 itself. When the effective logic value BH of the third pulse width modulation signal DB in T3 is over, the pulse width modulation module PWM3 outputs the jitter signal BD immediately after the effective logic value BH of the pulse width modulation signal DB is over, and the jitter signal BD is distributed in the third sub-period T3, and the time length of the jitter signal BD is equal to the cycle time of the clock signal CK3 itself. In an alternative example there is a predefined number of several cycles T within the time TX. In the example of fig. 17, only the first cycle T within the time TX has a dither signal and the remaining other cycles T do not output any dither signal.
Referring to fig. 18, each pulse width modulation module outputs a dithering signal having an effective logic value once every several cycle periods, whereby the duty cycle average value of each pulse width modulation signal in several of the cycle periods is adjusted by the dithering signal. For example, the pulse width modulation module PWM1 outputs the dither signal RD having an effective logic value once every time TX, the time TX is equal to a number of cycle periods T, for example, the time TX is equal to 4 or 8 or 16 cycle periods T. The PWM module PWM2 outputs the jitter signal GD with an effective logic value once every time TX, and the PWM module PWM3 outputs the jitter signal BD with an effective logic value once every time TX. Whereby the average value of the duty cycle of each pulse width modulation signal in a plurality of the cycle periods is adjusted by the dithering signal. For example, the duty cycle average of the first pulse width modulation signal DR in the time TX is adjusted by the dithering signal RD, the duty cycle average of the second pulse width modulation signal DG in the time TX is adjusted by the dithering signal GD, and the duty cycle average of the third pulse width modulation signal DB in the time TX is adjusted by the dithering signal BD. Fig. 18 shows a pulse width modulated signal combination dither signal with discrete active logic values, and a pulse width modulated signal combination dither signal with continuous active logic values, as compared to fig. 17.
Referring to fig. 18, the above is that the effective logic values of each pulse width modulated signal in a corresponding one of the sub-periods are arranged in a scattered or discrete manner. The effective logic values are arranged in a discrete manner as in the examples of fig. 12 and 14-16. The pulse width modulation module outputs a dithering signal: if the effective logic values of the pulse width modulation signals are distributed in a scattered manner, the last effective logic value in the pulse width modulation signals generated by the pulse width modulation module outputs a dithering signal immediately after the last effective logic value is finished. The first pulse width modulation signal DR has a plurality of effective logic values RH in T1, and the pulse width modulation module PWM1 outputs the jitter signal RD immediately after the last effective logic value RH of the first pulse width modulation signal DR is finished, where the jitter signal RD is distributed in the first sub-period T1, and the time length of the jitter signal RD can be set to be equal to the cycle time of one clock signal CK1 itself. In an alternative example, the second pulse width modulation signal DG has a plurality of valid logic values GH in T2, and the pulse width modulation module PWM2 outputs the jitter signal GD immediately after the last valid logic value GH of the second pulse width modulation signal DG is finished, where the jitter signal GD is distributed in the second sub-period T2, and the period of time of the jitter signal GD may be set to be equal to the period time of one clock signal CK 2. The third pulse width modulation signal DB has a plurality of valid logic values BH in T3 and the pulse width modulation module PWM3 outputs the wobble signal BD immediately after the last valid logic value BH of the third pulse width modulation signal DB it generates is ended, the wobble signal BD is distributed in the third sub-period T3 and the time length of the wobble signal BD can be set to be equal to the period time of one clock signal CK 3. In the embodiment of fig. 18, the dither signal is present only in the first cycle period T within the time TX, and no dither signal is output in the remaining other cycle periods within the time TX. Dithering techniques allow a greater number of colors to be simulated with a smaller number of colors.
Referring to fig. 19, the core function of the current source module PCS is to provide high accuracy and stable output current delivery to a target object having constant current requirements. The current source module PCS is explained for the moment with a circuit architecture based on a linear regulator as an alternative embodiment. The power regulating transistors of the constant current source part of the current source module PCS mainly operate in a linear state or non-switching state. The power adjustment transistor TQ has a first end and a second end and a control end, and if the power adjustment transistor employs a mosfet, three terminals of the power adjustment transistor are commonly referred to as drain and source and gate control ends, and if the power adjustment transistor employs a bipolar junction transistor, three terminals are commonly referred to as collector and emitter and base control ends. The power adjusting transistor TQ has a first terminal coupled to the power receiving terminal VI and a second terminal coupled to the node NT where the voltage is to be sampled. The voltage at node NT is sampled with a feedback network and the first terminal receives the input voltage and the potential reference terminal VR or ground is the current output of the constant current source. The resistors R1 and R2 connected in series between the node NT of the sampled voltage and the potential reference terminal VR belong to a feedback network, also called feedback resistor, and the interconnection node ND of the two is regarded as the voltage feedback node of the feedback network. The feedback voltage provided at the interconnection node ND is coupled to the inverting terminal of the error amplifier AP, and the reference voltage VB0 provided by the bandgap reference source BG0 is coupled to the non-inverting terminal of the error amplifier AP. The error amplifier AP compares and amplifies the reference voltage VB0 with the feedback voltage at the feedback node while the output of the error amplifier AP is also coupled to the control terminal of the power adjustment transistor TQ and operates the power adjustment transistor to operate in the linear region. Thereby maintaining the voltage at node NT stable. A load resistor RL is connected between the potential reference terminal VR and the node NT based on a demand for forming a stable output current. The voltage across the load resistor RL is determined and the current flowing through it is also determined, according to which it is ensured that the current flowing at the potential reference terminal VR is a constant current and meets the requirement that the constant current source is able to provide a stable output current. The voltage stabilizing diode ZD with the negative electrode connected to the power receiving end VI and the positive electrode connected to the potential reference end VR plays a role in overvoltage protection.
Referring to fig. 19, the constant current source including the power adjusting transistor TQ and the error amplifier AP and the load resistor RL even the feedback network has the capability of providing a stable output current, and if the current source module is simply constructed with this circuit, it is clearly considered that the output current flowing from the constant current source is fixed and difficult to be modified online. Attempting to flexibly adjust the output current of the constant current source requires changing the resistance value of the resistor R1 or R2 in the feedback network or changing the resistance value of the load resistor RL or changing the voltage value for the reference voltage VB 0. Considering that the actual application scene of the PCS of the current source module is often a circuit board or a similar component carrier, the disadvantages of complex operation, high cost and the like exist when components are directly replaced on the carrier. Preferably, the programmable constant current source should be designed in a mode of adjustable output current to replace the constant current source with fixed output current, so that the output current flowing out of the constant current source is not fixed any more but can be programmed on line. When the current source module PCS is designed as a current source chip in the form of an integrated circuit, the action of changing the component parameters inside the integrated circuit chip is more complicated. In this case, the current source module PCS is additionally provided with a data transmission module DAT2 which has a decoder and can decode the input serial data according to a predetermined communication protocol, and the data transmission module DAT2 decodes the current regulation data from the received communication data, so that the current source module PCS can adjust the magnitude of the output current of the programmable constant current source on line according to the current regulation data. The meaning of the current regulation data is to change the output current of the constant current source, and typically, for example, the resistance value of the resistor R1 or R2 in the feedback network can be finely tuned according to the current regulation data, and the voltage value of the reference voltage VB0 and even the resistance value of the load resistor RL can be finely tuned according to the current regulation data. Any such on-line adjustment or programming action causes the magnitude of the output current from the constant current source to be adjusted.
Referring to fig. 19, although the current source module PCS uses a linear modulator architecture as an illustrative example, the circuit architecture of the current source module PCS is not unique in nature, and any current source module capable of providing a stable output current can alternatively maintain the total input current of the driving circuit at a predetermined value. For example, a three-terminal programmable shunt regulator may be applied in the alternative to the current source module PCS: the constant current source of the alternative current source module PCS is based on a bipolar junction transistor and a three-terminal programmable shunt regulator and load circuit RL, with the cathode of the three-terminal programmable shunt regulator being connected to the control terminal of the power regulator transistor and the anode of the three-terminal programmable shunt regulator being connected to the potential reference terminal VR, and the reference terminal of the three-terminal programmable shunt regulator being connected to the illustrated node NT location. The load circuit RL sets the constant current source in a mode of fixed output current without trimming. An alternative to trimming the resistance value of the load circuit RL using the data transfer module DAT2 is to set the programmable constant current source in an output current adjustable mode. The current source module PCS, in other alternative types of alternatives, is as follows: the power regulating transistor TQ is a bipolar junction transistor and removes the bandgap reference source and the error amplifier directly, the cathode of the three-terminal programmable shunt regulator is connected to the control terminal of the power regulating transistor and the anode of the three-terminal programmable shunt regulator is connected to the potential reference terminal VR, a non-illustrated resistor is connected between the first terminal and the control terminal of the power regulating transistor TQ, and the reference terminal of the three-terminal programmable shunt regulator, which is not illustrated in the drawing, is connected to the node ND in the feedback network that is left. The constant current source is set in a mode of fixed output current without trimming the resistance R1 or R2 of the load circuit RL and the feedback network, and if the resistance of the resistance R1 or R2 with a series relation in the feedback network is trimmed or even the resistance of the load circuit RL is trimmed by using the data transmission module DAT2, the programmable constant current source is set in a mode of adjustable output current instead. The constant current source of the alternative current source module PCS is based on a bipolar junction transistor and a three-terminal programmable shunt regulator and a load circuit RL and a feedback network. It is easily known that the mentioned solutions of current source modules with constant current sources or current source chips with constant current sources are diversified, as long as the output current generated by them is capable of maintaining the total input current of the drive circuit at a predetermined value or within a predetermined range.
Referring to fig. 20, the current source module PCS does not need the data transfer module DAT2 functioning as a communication at all if the constant current source is set in the output current fixed mode, whereas the data transfer module DAT2 is indispensable if the programmable constant current source is set in the output current adjustable mode. The data transmission modules DAT1-DAT2 have two situations that data needs to be forwarded and data does not need to be forwarded. The current source module PCS receives the communication data alone without forwarding the data, and participates in a cascade relationship with the driving circuit in the case of forwarding the data. In an alternative embodiment, the decoder 210 and the data forwarding module 220 are provided as examples to illustrate the working mechanism of the data transmission module for receiving communication data and forwarding data. The signal input terminal DI receives communication data provided from outside, and the typical data transmitting terminal such as a server or a microprocessor can output communication data conforming to the precoding rule. The decoder 210 decodes or decodes the data information carried in the communication data. Communication data encoded using, for example, manchester encoding and decoding techniques or return-to-zero encoding and decoding techniques, requires that the data in these formats be correctly decoded by decoder 210. The data transmission module can be regarded as a serial interface or a serial interface circuit. The meaning of data decoding is that data with a pre-encoded format that cannot be directly distinguished can be restored to the most conventional binary code that is easily recognized and executed, such as manchester encoding, which characterizes a 1 or 0 with a high-low level jump, while zeroing code distinguishes a 1 or 0 with a high-level time width. The decoded binary code is temporarily stored in register 230 and additional buffer space or latches 250 are used to store the decoded data, taking into account that the data refresh rate of register 230 is typically updated when it is relatively fast. The decoding process of the communication data can select to detect the ending instruction code or the resetting instruction in the data to judge whether the data is transmitted and received. Taking the return-to-zero code as an example, the long and low levels with longer duration are used for representing the reset instruction, no matter the return-to-zero code is 1 code or 0 code, the pre-defined coding cycle time exists, the duration of the high level of the return-to-zero code in the coding cycle time is different, and the time length of the reset instruction is far longer than the single coding cycle time of the conventional 1 code and 0 code. The long low level representing the RESET command RESET can be monitored by a long low level detection circuit, not shown in the figure, which will cause the current source module to RESET and use the current regulation data from latch 250 for trimming and overwriting the resistance value of resistor R2.
Referring to fig. 20, the number of bits of the current adjustment data of the correction resistor R2 is a natural number U, which corresponds to a series of trimming resistors RA0-RAU of which the number is U selected from among the series of trimming resistors and is equivalent to the resistor R2. A selection switch is connected between two ends of each selected trimming resistor, so that each trimming resistor is connected in parallel with one selection switch, for example, two ends of each trimming resistor are respectively connected in parallel with selection switches BS0-BSQ. The current adjustment data B < U > to B <0> are used to control whether or not the selection control switch connected in parallel with each trimming resistor is turned on, respectively. Assuming B < U > as an example is 1, the parallel selector switch BSU of the trimming resistor RAU controlled by the symbol is turned on and causes the resistance value of the resistor R2 to decrease. As another alternative example, assume again that B <1> is 0 and the shunt selector switch BS1 of the trimming resistor RA1 controlled by the symbol is turned off so as to cause the total resistance value of the resistor R2 to increase. The current regulation data can cause the output current flowing out of the constant current source to be regulated by changing the resistance value of the resistor R2. According to the same principle, it is easy to understand that the magnitude of the output current flowing from the constant current source can be adjusted by alternatively changing the resistance value of the resistor R1 by using the current adjustment data, or even changing the voltage value of the reference voltage VB0 by using the binary current adjustment data, even though not illustrated in the figure.
Referring to fig. 20, the foregoing description of the manner in which the current source module PCS and the driving circuit are allowed to be cascade-connected to communicate communication data based on the single-wire communication protocol is the simplest communication scheme. Manchester encoding belongs to the phase encoding and characterizes a 1 or 0 with high-low level transitions present during each data encoding period, while zeroing codes represent a 1 code with a longer high level duration and a 0 code with a shorter high level duration during each encoding period, which are commonly applied to single-wire communication protocol codecs but not the only codec schemes. For example, even the difference of the times of high level in a single coding period can be used to distinguish that 1 code or 0 code if high level indicates 1 twice and high level indicates 0 once, so that all single-wire communication protocols which can transmit data by using a single data line can be applied to the application. The functions of data reproduction or data transfer are performed in the current source module PCS by the data transfer module 220, which performs data transmission tasks such as transferring communication data to the rear driving circuit. The simplest forwarding mode of the data forwarding module 220 is transparent transmission, i.e. it allows the data forwarding module to forward and output the communication data received from the signal input terminal DI directly from the signal output terminal DO, and then the driving circuit or the current source module PCS connected in cascade extracts the communication data which matches the address of the data forwarding module from the single data line according to the address allocation rule. However, in practical applications, the number of cascaded driving circuits is very large, symbol errors are very easy to be generated in long-distance data transmission, parasitic or load capacitance and other parameters existing at the input and output ports of the data signals inevitably induce attenuation of transmission data, and cascading attenuation effects are accumulated. Taking the return-to-zero code protocol as an example, the high level of each bit experiences more or less partial loss during any one forwarding, and moreover, the pixel rule number required by the display system is quite huge, so that the more cascaded chips are, the more data distortion situation is serious, and even the chips cannot normally identify code elements, so that the number of the cascaded chips is limited. The first forwarding path Sel1 of alternative transparent transmission needs to cooperate with counting whether the total number of bits of the current adjustment data B <0> to B < U > belonging to the current source module PCS is completely received, and the implementation means of counting the number of bits is various, such as using a counter, which is most commonly used. Once the current regulation data belonging to the current source module PCS has been decoded and completely received by it, an enable signal ENB is generated, which, when active, for example, is active high, triggers the data forwarding module 220 to enable the data forwarding function and to forward the communication data received at the signal input DI from its signal output DO, in which case the data forwarding module 220 plays the role of a switch whether the received communication data is allowed to be output. In addition to the data forwarding module 220 acting as a switch, in fact, in order to address the suspected effects of data cascading attenuation, the data forwarding module 220 should reconstruct each bit so that its transmission loss is trimmed to recover the standard transmission code. Taking the return-to-zero code as an example, in view of the problem that the high level of each bit undergoes retransmission with partial loss, for example, the data forwarding module 220 can properly lengthen the high level duration of the 1 code to a recognizable ground when detecting that the high level duration of the 1 bit is too short, and can properly lengthen the high level duration of the 0 code when detecting that the high level duration of the 0 bit is too short, but the lengthening operation cannot cause the high level duration to be excessively prolonged to prevent the erroneous recognition as the 1 code. The data forwarding module 220 may thereby reconstruct the bits of each return-to-zero code format to its standard transmission encoding. Essentially, the data forwarding module 220 should reconstruct each bit regardless of the predetermined coding format of the communication data, such that the transmission loss of each bit is trimmed to recover a standardized transmission code that is easily recognizable and conforms to the predetermined coding format. Counter 260 may be used to count whether the total number of bits of current regulation data B <0> through B < U > is fully received, and counter 260 generates a valid enable signal ENB when the current regulation data belonging to the current source module is decoded and fully received.
Referring to fig. 20, the second forwarding path Sel2 is slightly different from the first forwarding path Sel1, in that the communication data is decoded by the decoder 210 of the data transmission module DAT2, and the data forwarding module 220 performs a switching role to determine whether to allow the decoded data to be forwarded under the control of the enable signal ENB, in which case the decoding and the data reconstruction are almost synchronously completed. A number of clock signals having a predetermined number, as provided by a local clock circuit not illustrated by the data transmission module DAT2, may be used to detect the length of time of the high level of each return-to-zero code bit. In consideration that the high level duration of 1 code is longer than the high level duration of 0 code in each encoding period, the decoding process may detect the high level time length in each encoding period with a predetermined number of clock signals, the decoding result is 0 code if the high level of the return-to-zero code bit has ended in advance on the premise that the predetermined number of clock signals have not ended, and the decoding result is 1 code if the high level of the return-to-zero code bit has not ended on the contrary. The decoder 210 outputs the reconstructed data in addition to intuitively reflecting the decoding result: when the high level rising edge of the zeroing code bit of the communication data arrives, the serial clock signal with the preset number starts to sample the bit, and the high level of the zeroing code bit is sampled by the first clock in the preset number of serial clock signals, the decoder 210 starts to output the high level and is forwarded by the data forwarding module 220. Selecting a ordered specified clock signal, such as the ordered second clock signal, from among a predetermined number of serial clock signals continues to sample the high level of the return-to-zero code bit, and if the ordered specified clock signal samples low, the decoder 210 begins switching from output high level to output low level and the output sync is forwarded by the data forwarding module 220, and conversely, if the ordered specified clock signal samples high, the decoder 210 still outputs high level and is forwarded by the data forwarding module 220. The decoder 210 is triggered to return to an output low level and be forwarded low by the headend module 220 at the end of a predetermined number of serial clock signals, regardless of whether the return-to-zero code bit is high. Through the explanation of decoding and data reconstruction, the data forwarding is equivalent to the process of decoding and recoding input data and then forwarding the input data, and the communication data is completely restored into the coded data with the preset coding format under the sampling of clock resources of the data transmission module and is transmitted to a data receiver cascaded with the coded data.
Referring to fig. 20, slightly different from the first forwarding path Sel1 and the second forwarding path Sel2, an alternative implementation of data forwarding is a recoding technique, i.e., a third forwarding path Sel3. The data transmission module DAT2 implements the re-encoding purpose with an additionally configured encoder 240. In contrast to the foregoing several forwarding modes, the communication data is temporarily stored in the storage space of the data transmission module DAT2 after being decoded, and then the temporary storage data is recoded and output by the encoder 240 capable of recoding binary data, and the relay effect of decoding, storing and recoding output according to the preset coding format ensures that the data can be transferred smoothly. The aim of the data trimming or data shaping means is to forward the trimmed correct data to the data receiver at the lower stage, so that the communication data is ensured not to be distorted in the transmission and forwarding stage, the data transmission attenuation distortion mentioned above does not catch the cascade connection quantity of the data receivers on the elbow single-wire transmission line any more, and the data receivers can be in infinite cascade connection theoretically apart from the data refresh rate factor. It should be emphasized that although the communication data transfer process is described by taking a single-wire communication as an example, a substantially alternative multi-wire communication is also suitable for the present application for transferring the communication data to the current source module PCS and the driving circuit. The display technology is commonly used for realizing the transmission of cascade signals by adopting four or other transmission lines, the clock signal line and the data signal line work simultaneously with the loading signal line and the output enabling signal line, communication data are respectively transmitted serially in sequence, and the control of each cascade data receiver is realized by the coordination of four-line signals. Communication protocols using three lines, a data line and a clock line, and a latch line, are also the dominant communication schemes for display technologies. When the pixel point distance is larger, double-line transmission is adopted, and the double-line transmission of the data line and the clock line is a compromise between the number of data lines and the transmission rate. The two-wire protocol such as IIC and SMBUS, which are common, requires slaves to be connected in parallel, while the one-wire protocol has the advantage that only a single signal line is required for data transmission. The first to third forwarding paths Sel1 to Sel3 and the so-called transparent or even multi-line communication may optionally be one of the communication schemes as data transmission modules DAT1 to DAT 2. If a single cascade transmission line is adopted for serial cascade signals to sequentially connect all data receivers, the transmission process does not need to consider the time sequence coordination of cascade signals, so that the transmission process of cascade signals is simpler, the transmission failure rate is low, the use amount of cables is reduced, and the cost is saved.
Referring to FIG. 21, a cascade of driver chips IC1 through ICK (natural number K.gtoreq.1) is illustrated as representing a K-stage driver circuit or driver. The data transmitting end transmits communication data GSD to each level of driving chips, and the data transmitting end can use a server or a microprocessor MCU and the like, and the driving chips are also called display control chips.
Referring to fig. 21, the cascade driving circuits are arranged in one or more columns on the power supply path. The power supply input IN of the first driving circuit IN each column as the head of the column, e.g. driving chip IC1, is coupled to the positive supply VCC and the potential reference OUT of the last driving circuit IN the tail of the column, e.g. driving chip ICK, is coupled to the negative supply VCC. The power input terminal of the latter driving circuit is also arranged in each column to be coupled to the potential reference terminal of the former driving circuit. IN an alternative example, for example, IN the first column CL1, the power input terminal IN of the subsequent driving chip IC2 is coupled to the potential reference terminal OUT of the adjacent previous driving chip IC1, and the power input terminal IN of the subsequent driving chip IC3 is coupled to the potential reference terminal OUT of the previous driving chip IC2, etc. The power supply is analogized to the point where the power input IN of the last driving circuit of the column tail, e.g. the driving chip ICK, is coupled to the potential reference OUT of its neighboring previous driving circuit, i.e. the K-1 st driving chip, etc. The power input end of the rear driving circuit is coupled to the potential reference end of the adjacent front driving circuit in each column of the power supply system until all driving circuits in each column are connected in series or overlapped between the positive pole and the negative pole of the power supply or between the positive pole and the ground end of the power supply. A capacitor CZ may be provided between the power input terminal IN and the potential reference terminal OUT of each driving circuit as a voltage stabilizing option. The total output current of the previous drive circuit can be considered as the total input current of the next drive circuit in each row. In an alternative example a current source module PCS is arranged on the supply line of each column driver circuit, e.g. IC1-ICK, to maintain the total input current of each driver circuit in this column at a predetermined value. IN the first column CL1, a driving circuit such as an IC1-ICK and a current source module PCS is connected IN series between the positive and negative poles of the power supply, and the power supply input terminal IN of the driving chip IC1 is not directly coupled to the positive pole of the power supply but indirectly coupled to the positive pole of the power supply through the current source module PCS. The power receiving terminal VI of the set current source module is connected to the positive pole of the power VCC and the potential reference terminal VR thereof is connected to the power input terminal IN of the driving chip IC 1. The total input current of any one of the column driving circuits is equal to the output current of the current source module.
Referring to fig. 21, in a stage that each driving circuit receives the previous frame communication data and refreshes the next frame communication data to adjust the respective gray-scale data of the plurality of light emitting diodes, the current adjustment data received by the current source module PCS is refreshed by frames so that the output current of the current source module PCS is refreshed by frames and flows to the driving circuit, and the total input current of each driving circuit is updated from the preset value corresponding to the previous frame current adjustment data to the preset value corresponding to the next frame current adjustment data. Note that the previous frame of current regulation data is decoded from the previous frame of communication data and the next frame of current regulation data is decoded from the next frame of communication data. The foregoing technical features are that the driving circuit and the current source module PCS are described with columns as basic units, and it is also permissible to configure the current source module PCS and the driving circuit without columns as basic units. A typical application of a single driver circuit and its current manager current source module PCS combination as a single pixel or point source is a breathing lamp. Therefore, whether a single driving circuit or a column is taken as a basic unit, the current regulation data received by the current source module PCS is refreshed according to frames, and the total input current of the driving circuit is updated from a preset value corresponding to the current regulation data of the previous frame to a preset value corresponding to the current regulation data of the next frame. Even if a single current source module PCS is matched with a single driving circuit to serve as a point light source, the current flowing out of the current source module PCS is still equal to the total input current of the driving circuit. Furthermore, IN this embodiment, if a plurality of driving circuits are connected IN series IN a row, the driving circuits are all arranged IN parallel, that is, the power input terminal IN of each driving circuit is coupled to the positive electrode of the power VCC, and the potential reference terminal OUT of each driving circuit is coupled to the negative electrode GND, but IN this case, the voltage of the power supply is reduced adaptively to satisfy the voltage withstanding degree of the driving circuits.
Referring to fig. 21, the foregoing solves the power supply problem of the cascade driving chips IC 1-ICK. The signal input end of the rear stage driving circuit is coupled to the signal output end of the front stage driving circuit. Typically, the signal input terminal DI of the driver IC2 is coupled to the signal output terminal DO of the driver IC1, and the signal input terminal DI of the driver IC3 is coupled to the signal output terminal DO of the driver IC2, and so on. The signal input terminal DI of the last stage in the cascade connection, such as the driver chip ICK, is coupled to the signal output terminal DO of its neighboring previous stage driver circuit, i.e. the K-1 stage driver chip, etc. It will be appreciated from the description of this embodiment that each frame of communication data is transferred from head to tail, i.e., from IC1 to ICK. The signal input of the optional post driver circuit may be coupled to the signal output of the pre driver circuit via a coupling capacitor C. For example, the signal input terminal DI of the driver chip IC2 of the subsequent stage may be coupled to the signal output terminal of the driver chip IC1 through the capacitor C, and the signal input terminal DI of the driver chip IC3 may be further configured to be coupled to the signal output terminal of the driver chip IC2 through the capacitor C. The signal input terminal DI of the current source module PCS with the data forwarding function receives the communication data, and the signal output terminal DO of the current source module PCS forwarding the data is coupled to the signal input terminal DI of the first-stage driving chip IC1 through the capacitor C. The current source module and the driving circuit with the data forwarding function can forward communication data to the other side.
Referring to fig. 21, the cascade driving chips IC1-ICK are in a manner of transferring serial data from head to tail, i.e., serial data is first given to IC1 and second to IC2 and third to IC3 to be last given to ICK. This direction of transfer of serial data can also be modified as: the serial data is first given to the ICK at the column tail, the second is the last to last driver chip of the K-1 stage, and the third is the last to last driver chip of the K-2 stage before being given to IC1. The serial data is considered to be passed back from the tail to the head of the column, i.e., from the ICK to IC1. Therefore, the connection relationship between the signal receiving and transmitting ends in fig. 21 needs to be modified as follows: the signal input terminal DI of the final driver chip IC1 is coupled to the signal output terminal DO of the preceding driver chip IC2 and the signal input terminal DI of the succeeding driver chip IC2 is coupled to the signal output terminal DO of the driver chip IC3 of its preceding stage up to a single line communication mode and so on, and the signal output terminal DO of the first stage in the cascade relationship, such as the driver chip ICK, is coupled to the signal input terminal DI of the driving circuit of its succeeding stage, i.e., the K-1 st stage. The signal input DI of the current source module is coupled to the signal output DO of the final drive chip IC1 via a capacitor C. It can be known from the description of this embodiment that each frame of gradation data is transferred from the column tail to the column head. Also, the signal input terminal of the rear stage driving circuit may be coupled to the signal output terminal of the front stage driving circuit through a coupling capacitor. Whether serial data is transferred from the head to the tail or from the tail to the head among the driver chips IC1-ICK, it is possible to arrange that their column driving circuits are connected IN series with a current source module PCS that provides a constant current source, which maintains the current flowing from the power input terminal IN of each of the driver chips among the column driver chips IC1-ICK to its potential reference terminal OUT at a predetermined value. The specific position of the current source module can be adjusted from the position between the power input end and the power anode of the IC1-ICK to the position between the potential reference end and the power cathode of the ICK, the power receiving end VI of the current source module is connected to the potential reference end OUT of the driving chip ICK, and the potential reference end VR of the current source module is connected to the power cathode GND. Or the current source module is arranged between any two adjacent driving chips, namely between the potential reference end of the previous driving chip and the power input end of the adjacent next driving chip in each column driving chip, for example, the power receiving end VI of the current source module is connected to the potential reference end of the driving chip IC2, and the potential reference end VR of the current source module is connected to the power input end of the driving chip IC 3.
Referring to fig. 21, the foregoing is a display system that characterizes cascade-connected multi-level driving circuits with single-column cascade driving chips IC1-ICK but is actually constructed with multiple-column driving chips can display more complicated contents. The multi-stage driving circuit is arranged in a plurality of columns and the second column driving chip CL2 is also part of the multi-stage driving circuit in addition to the first column CL1 of the driving chips IC1-ICK, and no more columns are shown in the space restriction diagram. The essentially cascaded multi-stage drive circuit may be divided into more columns than the two shown, just for the moment taking two columns as an example. The second column driver chip CL2 and the first column driver chip CL1 are not greatly different in power supply manner and in communication, and therefore, it is not repeated but it should be emphasized that each driving circuit in the second column driver chip CL2 is connected in series with a plurality of current source modules PCS providing a constant current source. The current source module PCS maintains a current flowing from the power input terminal IN of each of the second column driving chips CL2 to the potential reference terminal OUT thereof at a predetermined value. The specific location of each current source module may be between the power supply input of IC1-ICK and the power supply anode or between the potential reference terminal of ICK and the power supply cathode, or in the second column driver chip the current source module is arranged between any adjacent two driver chips, i.e. between the potential reference terminal of the preceding driver chip and the power supply input of the adjacent following driver chip.
Referring to fig. 21, the two column driving circuits of the first column driving chip CL1 and the second column driving chip CL2 are partial parts of the entire cascade driving circuit, and serial data needs to be transferred from the first column driving chip to the second column driving chip or from the second column driving chip to the first column driving chip. Each frame of communication data may be transferred from the head or tail of any one column driver circuit to the head or tail of another column driver circuit. Each frame of communication data is transferred from the head of the column of the first column driver chip CL1, such as the driver chip IC1, to the head of the column driver chip IC1 of the second column driver chip CL2 or to the tail of the column driver chip ICK of the second column driver chip CL 2. The signal output terminal of the driver chip IC1 of the first column driver circuit CL1 is coupled to the signal input terminal of the driver chip IC1 of the second column driver chip CL2 or the signal output terminal of the column head driver chip IC1 of the first column driver circuit CL1 is coupled to the column tail ICK signal input terminal of the second column driver chip CL 2. If the first or the second column driver chip CL2 is not a driver chip but a current source module PCS, then the change is made such that each frame of communication data is transferred from the first column driver chip CL1, for example, the driver chip IC1, to the current source module of the first column driver chip CL2 or to the current source module of the second column driver chip CL 2.
Referring to fig. 21, in an alternative example, each frame of communication data may be transferred from the column tail driver IC in the first column driver CL1 to the column head driver IC1 in the second column driver CL2, and each frame of communication data may also be transferred from the column tail driver IC in the first column driver CL1 to the column tail IC in the second column driver CL 2. In this case, the signal output terminal of the driver chip ICK in the first column driver chip CL1 may be configured to be connected to the signal input terminal of the driver chip IC1 at the head of the column in the second column driver chip CL2 through coupling capacitive coupling, or to the signal input terminal of the driver chip ICK at the tail of the column in the second column driver chip CL2 through coupling capacitive coupling. If the first or the second column driver chip is not a driver chip but an alternative current source module PCS, each frame of communication data is transferred from the column tail of the first column driver chip CL1, for example, the driver chip ICK, to the current source module of the first column driver chip CL2 or to the current source module of the column tail of the driver chip CL2 of the second column. It is of course also allowed that each frame of communication data is reversely transferred from the second column driver chip CL2 to the first column driver chip CL1.
Referring to fig. 21, the communication data GSD of the display system or the independent pixel point is displayed according to frames, and each frame of communication data is used to set the output current of the constant current source by the current regulation data of the current source module PCS, and each frame of communication data is used to set the constant current provided by the constant current unit by the constant current regulation data of the driving circuit. The constant current regulation data to the driving circuit may be referred to as first current regulation data, and the current regulation data to the PCS of the current source module may be referred to as second current regulation data. The driving circuit can adjust the magnitude of constant current provided by the constant current unit in the driving circuit according to the first current adjustment data, and the current source module PCS can adjust the magnitude of output current of the programmable constant current source in the current source module according to the second current adjustment data. When the first current regulation data and the second current regulation data are set under the same frame of communication data, the first current regulation data sent to the driving device should preferably be used for setting the constant current provided by the constant current unit in each frame of communication data, the second current regulation data sent to the current source module is used for setting the output current of the constant current source, and when the first current regulation data and the second current regulation data are set, the current flowing through any one light emitting diode is limited not to exceed the output current of the constant current source in the current source module.
Referring to fig. 21, first to third light emitting diodes LED1 to LED3 are exemplified. The current regulation data allocated to the current source module PCS are claimed to be used for setting the output current IT generated by the constant current source of the current source module PCS, and the constant current regulation data allocated to the driving circuit are claimed to be used for setting the values of the constant currents I1-I3 provided by the constant current units CC1-CC3 respectively in the same frame of communication data. The currents that each of the first to third light emitting diodes LED1 to LED3 respectively flows by driving of the driving circuit are denoted as I1 and I2 and I3. The first current regulation data and the second current regulation data are designed such that the current I1 or I2 or I3 flowing through the three LEDs 1 to 3, respectively, does not exceed the output current IT of the constant current source of the current source module. This applies to the embodiment of a combined point light source of a single drive circuit and a single current source module, as well as to embodiments of a number of drive circuits and current source modules configured in a column basis. In view of the fact that the result of the nor operation performed by the multiple pulse width modulation signals is regarded as the control signal DX of one bypass module connected in parallel with the multiple light emitting diodes LED1-LED3, the bypass module is turned on and the shunt is implemented when the control signal DX is at a valid logic value. The shunt current at the shunt of the known bypass module is determined by a constant current unit such as CC1 of fig. 9-10 or CC5 of fig. 11. When the first and second current adjustment data are set, the shunt current or the shunt current value flowing through the bypass module is limited to not exceed the output current of the constant current source in the current source module, that is, the shunt current provided by CC1 flowing through the resistor RX or the LED5 in fig. 9-10 does not exceed the output current IT of the constant current source, or the shunt current provided by CC5 flowing through the resistor RX in fig. 11 does not exceed the output current IT of the constant current source. Considering that the currents supplied by the constant current cells CC1 and CC5 allow the driving circuit to be modified on line by the received communication data, it is easy to define the shunt current not to exceed the output current of the constant current source.
Referring to fig. 21, the same portion as before is that a current source module PCS with a constant current source is also provided on a line supplying power to the driving circuits and is used to maintain the total input current of the driving circuits at a preset value, and the output current of the constant current source, that is, the output current of the current source module PCS, flows to each driving circuit, and the total input current of each driving circuit is equal to the output current flowing from the current source module. But instead of setting the programmable constant current source in the output current adjustable mode, the constant current source is set in the output current fixed mode. In this case the current source module PCS may not use decoding and data forwarding functions, and the output current provided by the constant current source of the current source module PCS is fixed without having to be programmable but still clamps the total input current of the driving circuit. In order to illustrate the differences and not to cause confusion of terms, the constant current unit of the driving circuit can be defined as a first constant current module, the constant current source of the current source module PCS can be defined as a second constant current module, the constant current regulation data sent to the driving circuit can be defined as first current regulation data, and the current regulation data sent to the current source module PCS can be defined as second current regulation data. In addition, it can be observed that the number of current source modules used by the two column driving circuits of the first column driving chip CL1 and the second column driving chip CL2 of the display system is allowed to be different, and of course, the same number of current source modules can be used, but when the supply voltages of different columns are different, different numbers of current source modules can be introduced to balance the voltage difference. The supply lines providing the power supply have distributed parasitic resistances and further lead to slightly different supply voltages for different columns, columns with a larger supply voltage using a larger number of current source modules and columns with a smaller supply voltage using a smaller number of current source modules, so-called introducing a different number of current source modules to balance such supply voltage differences between different columns.
The foregoing description and drawings set forth exemplary embodiments of the specific structure of the embodiments, and the foregoing invention provides presently preferred embodiments, without being limited to the precise details. Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above description. It is therefore intended that the following appended claims be interpreted as covering all alterations and modifications as fall within the true spirit and scope of the invention. Any and all equivalent ranges and contents within the scope of the claims should be considered to be within the intent and scope of the present invention.

Claims (10)

1. A driving device for driving a light emitting diode, comprising:
the pulse width modulation module forms a corresponding pulse width modulation signal according to the gray data matched with the light emitting diode;
the pulse width modulation signal is used for driving the light emitting diode to perform display control;
the pulse width modulation module is configured with a counter and a data comparator;
triggering the counter to count by a clock signal and obtaining a count value;
the count value is reordered according to the rule from low weight to high weight to obtain reverse order data;
the pulse width modulation module sends the gray data and the reverse order data into the data comparator for comparison:
The pulse width modulation signal has a valid logic value when the reverse order data is lower than the gray data;
based on a plurality of pulse width modulation modules, each pulse width modulation module forms a corresponding pulse width modulation signal according to gray data matched with one light emitting diode matched with the pulse width modulation module, and a plurality of light emitting diodes correspond to a plurality of pulse width modulation signals;
further comprises:
each path of constant current unit is connected with one path of light emitting diode in series;
whether any one light-emitting diode flows through constant current provided by a constant current unit connected in series or not is controlled by one pulse width modulation signal corresponding to the any one light-emitting diode;
the common cycle period of each path of pulse width modulation signal is divided into a plurality of sub-time periods, the effective logic value of each path of pulse width modulation signal is distributed in a corresponding sub-time period, and a plurality of paths of light emitting diodes are sequentially lighted in a time-sharing manner in the cycle period;
each sub-time period is allocated with a clock signal and the number of the clock signals of each sub-time period is a preset value;
determining the time length of each sub-time period according to the number of clock signals distributed by each sub-time period and the clock signals in a clock counting mode;
The frequencies of the plurality of clock signals allocated for the plurality of sub-periods of each cycle period are set to be the same or different.
2. The drive device according to claim 1, wherein:
the pulse width modulation modules are provided with a counter, the multi-bit counting data output by the counter comprises specified high-bit data and specified low-bit data, and the number of sub-time periods in each cycle period is determined by the bit number of the specified high-bit data;
the time length of each sub-time period is counted by a counter triggered by a clock signal matched with the sub-time period, and the preset value of the number of the clock signals in each sub-time period is determined by the bit number of the designated low-order data.
3. The drive device according to claim 2, wherein:
setting the bit number Z of the appointed high-order data and the bit number F of the appointed low-order data as natural numbers larger than zero;
the number of sub-periods per cycle period does not exceed 2 Z And the preset value in each sub-period is 2 F 。
4. The drive device according to claim 2, wherein:
the counter is configured with a data selector, a plurality of clock signals distributed for a plurality of sub-time periods are input to a plurality of data input ends of the data selector, and the appointed high-order data are regarded as channel selection signals of the data selector;
In each cycle period, the appointed low-order data triggers the appointed high-order data to carry once after each counting is full, and then triggers the data selector to switch and output different clock signals;
the different channel select signals map the different clock signals output by the data selector, thereby assigning a clock signal to each sub-period and for triggering the counter to count.
5. The drive device according to claim 1, wherein:
the LED driving circuit comprises a shunt module connected with a plurality of LEDs in parallel and used for stabilizing the input voltage supplied to the driving device;
the LED and constant current unit are coupled in series between the power input end and the potential reference end, and the shunt module is also coupled between the power input end and the potential reference end;
the shunt module comprises an adjustable parallel voltage reference circuit, wherein the cathode of the adjustable parallel voltage reference circuit is coupled to the power input end through a resistor or not, the anode of the adjustable parallel voltage reference circuit is coupled to the potential reference end, and a resistor voltage divider is arranged between the power input end and the potential reference end;
the reference terminal of the adjustable parallel type voltage reference circuit is coupled to the voltage dividing node of the resistor divider.
6. The drive device according to claim 1, wherein:
the bypass module is connected with the multiple light emitting diodes in parallel, a result obtained by performing NOR logic operation on the multiple pulse width modulation signals is regarded as a control signal of the bypass module, and the bypass module is triggered to split the total input current of the driving device when the control signal has an effective logic value.
7. The drive device according to claim 6, wherein:
the load and one path of constant current unit of the bypass module are connected in series;
each path of light emitting diode and load are respectively provided with a constant current unit, when the pulse width modulation signal corresponding to any path of light emitting diode has an effective logic value, the constant current unit connected in series is started, and when the control signal has an effective logic value, the constant current unit connected in series is started; or alternatively
The multiple light emitting diodes and the load share a common constant current unit, when the pulse width modulation signal corresponding to any one light emitting diode has an effective logic value, the pulse width modulation signal is switched to be connected in series with the common constant current unit, and when the control signal has an effective logic value, the load is switched to be connected in series with the common constant current unit.
8. The drive device according to claim 1, wherein:
A current source module with a constant current source is arranged on a line for supplying power to the driving device and is used for maintaining the total input current of the driving device at a preset value;
the constant current source is set in a mode in which the output current is fixed or the programmable constant current source is set in a mode in which the output current is adjustable.
9. The drive device according to claim 1, wherein:
the effective logic values of each pulse width modulation signal in a corresponding sub-period are arranged in a continuous manner; or alternatively
The effective logic values of each pulse width modulated signal within a corresponding one of the sub-periods are arranged in a decentralized manner.
10. The drive device according to claim 1, wherein:
at least a plurality of light emitting diodes with three primary colors of red, green and blue are provided, the gray data of each light emitting diode is adjusted under the condition of mixed color of the three primary colors, and different colors are obtained by the change of the gray data matched with each light emitting diode.
CN202111025175.4A 2019-08-14 2019-08-14 Driving device, display control chip, display device and display control method Active CN113707078B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111025175.4A CN113707078B (en) 2019-08-14 2019-08-14 Driving device, display control chip, display device and display control method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910749350.0A CN112397015B (en) 2019-08-14 2019-08-14 Driving device, display control chip, display device and display control method
CN202111025175.4A CN113707078B (en) 2019-08-14 2019-08-14 Driving device, display control chip, display device and display control method

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN201910749350.0A Division CN112397015B (en) 2019-08-14 2019-08-14 Driving device, display control chip, display device and display control method

Publications (2)

Publication Number Publication Date
CN113707078A CN113707078A (en) 2021-11-26
CN113707078B true CN113707078B (en) 2024-02-27

Family

ID=74601386

Family Applications (2)

Application Number Title Priority Date Filing Date
CN202111025175.4A Active CN113707078B (en) 2019-08-14 2019-08-14 Driving device, display control chip, display device and display control method
CN201910749350.0A Active CN112397015B (en) 2019-08-14 2019-08-14 Driving device, display control chip, display device and display control method

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201910749350.0A Active CN112397015B (en) 2019-08-14 2019-08-14 Driving device, display control chip, display device and display control method

Country Status (1)

Country Link
CN (2) CN113707078B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI714392B (en) * 2019-12-13 2020-12-21 點晶科技股份有限公司 Display module adjustment method of mobile device and led array driving system
CN113207209B (en) * 2021-04-30 2022-08-30 深圳市美矽微半导体有限公司 Data transmission method of single-wire cascade circuit and LED chip cascade system
CN113692088A (en) * 2021-08-13 2021-11-23 广州腾龙健康实业股份有限公司 LED lamp system and LED lamp control method for reducing instantaneous power
CN115424594B (en) * 2022-09-16 2023-03-28 北京显芯科技有限公司 Data transmission method and controller
CN115603713B (en) * 2022-12-01 2023-04-04 深圳市恒运昌真空技术有限公司 Pulse signal processing method and device and matching circuit

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101114440A (en) * 2007-08-27 2008-01-30 重庆大学 Automatic brightness control device of outdoor full color LED big screen display screen and method thereof
CN102157130A (en) * 2011-04-14 2011-08-17 苏州和迈微电子科技有限公司 Pulse width modulating method for LED driving integrated circuit
CN102193191A (en) * 2010-03-11 2011-09-21 株式会社理光 Pixel clock generating device and image forming apparatus
JP2012186441A (en) * 2011-02-14 2012-09-27 New Japan Radio Co Ltd Led drive method and led drive circuit
CN103347337A (en) * 2013-07-02 2013-10-09 苏州和迈微电子技术有限公司 Pulse width modulation method of LED driving integrated circuit
CN104159355A (en) * 2014-06-13 2014-11-19 矽力杰半导体技术(杭州)有限公司 LED drive circuit, and control circuit and control method of LED drive circuit
WO2014187004A1 (en) * 2013-05-20 2014-11-27 深圳市华星光电技术有限公司 Led backlight driving circuit, backlight module, and liquid crystal display apparatus

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070076019A1 (en) * 2005-09-30 2007-04-05 Randall Martin J Modulating images for display
US20150061522A1 (en) * 2013-08-27 2015-03-05 Texas Instruments Incorporated Method and apparatus for calculating an average value of an inaccessible current from an acessible current
JP6681550B2 (en) * 2014-09-30 2020-04-15 パナソニックＩｐマネジメント株式会社 Lighting device
CN107507557B (en) * 2016-06-14 2019-10-11 深圳市富满电子集团股份有限公司 A kind of LED driving pulse width dividing method and system
CN106251806B (en) * 2016-09-29 2019-04-02 北京集创北方科技股份有限公司 LED display and its driving method
CN109147653B (en) * 2018-10-09 2020-04-10 中国电子科技集团公司第五十八研究所 LED driving chip display control OS-PWM method

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101114440A (en) * 2007-08-27 2008-01-30 重庆大学 Automatic brightness control device of outdoor full color LED big screen display screen and method thereof
CN102193191A (en) * 2010-03-11 2011-09-21 株式会社理光 Pixel clock generating device and image forming apparatus
JP2012186441A (en) * 2011-02-14 2012-09-27 New Japan Radio Co Ltd Led drive method and led drive circuit
CN102157130A (en) * 2011-04-14 2011-08-17 苏州和迈微电子科技有限公司 Pulse width modulating method for LED driving integrated circuit
WO2014187004A1 (en) * 2013-05-20 2014-11-27 深圳市华星光电技术有限公司 Led backlight driving circuit, backlight module, and liquid crystal display apparatus
CN103347337A (en) * 2013-07-02 2013-10-09 苏州和迈微电子技术有限公司 Pulse width modulation method of LED driving integrated circuit
CN104159355A (en) * 2014-06-13 2014-11-19 矽力杰半导体技术(杭州)有限公司 LED drive circuit, and control circuit and control method of LED drive circuit

Also Published As

Publication number Publication date
CN112397015A (en) 2021-02-23
CN112397015B (en) 2021-12-14
CN113707078A (en) 2021-11-26

Similar Documents

Publication Publication Date Title
CN113192457B (en) Drive circuit, drive chip, display system and display method
CN113707078B (en) Driving device, display control chip, display device and display control method
US9936546B2 (en) Methods and apparatuses for operating groups of high-power LEDs
CN106851901B (en) Control the integrated circuit of the power supply to multiple light emitting diodes statements based on collusion electricity
CN211457461U (en) Light emitting diode driving chip
US20130134900A1 (en) System and method for adjusting color temperature
CN110784962B (en) Cascaded lighting system and lighting method
CN212183780U (en) Drive circuit and lamp
CN110868773B (en) Three-primary-color display unit, three-primary-color lamp bead and three-primary-color mixing method
TWI550575B (en) Light emitting device control circuit and control method thereof
JP2006041043A (en) Led drive circuit
TW201325314A (en) An apparatus and a method for driving LEDs
CN113891523B (en) Driving circuit, driving chip, driving system and driving method suitable for pulsating voltage
CN202454226U (en) Brightness control circuit, chip and device
US9320095B2 (en) Controller system, integrated circuit and method therefor
CN113891524B (en) Driving circuit, driving chip, driving system and driving method supporting wide voltage input
US20140111565A1 (en) Display driving circuit and display driving system
CN108541105B (en) LED driving system and method
CN114664229B (en) Display system, display method, driving device and driving chip
CN114724494B (en) Display screen, display algorithm, display data processing method and current adjusting method
CN217470332U (en) Single-wire three-channel constant-current driving circuit capable of continuous transmission at break point
CN117275390A (en) Driving device, driving chip, driving method and display system
CN114374312A (en) Driving device, method for adjusting self current of driving device and system based on driving device
CN111511075A (en) Drive circuit and lamp
CN114679811A (en) Light source driving circuit, method, luminaire and computer readable storage medium

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant