CN115567144A - Demodulation method and system of reference time 1PPS in IRIG-B code - Google Patents
Demodulation method and system of reference time 1PPS in IRIG-B code Download PDFInfo
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- CN115567144A CN115567144A CN202211514691.8A CN202211514691A CN115567144A CN 115567144 A CN115567144 A CN 115567144A CN 202211514691 A CN202211514691 A CN 202211514691A CN 115567144 A CN115567144 A CN 115567144A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0617—Systems characterised by the synchronising information used the synchronising signal being characterised by the frequency or phase
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- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/24—Acquisition or tracking or demodulation of signals transmitted by the system
- G01S19/30—Acquisition or tracking or demodulation of signals transmitted by the system code related
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention relates to the technical field of data communication, and provides a method and a system for demodulating reference time 1PPS in an IRIG-B code. The demodulation method of the reference time 1PPS in the IRIG-B code comprises the following steps of S10, synthesizing a first frequency signal and a second frequency signal through a local frequency synthesis unit; s20, performing first demodulation operation on the first frequency signal through a first demodulation unit; s30, performing first demodulation operation on the second frequency signal through a first demodulation unit; s40, synthesizing a third frequency signal through a local frequency synthesis unit; and S50, performing second demodulation operation through a second demodulation unit. According to the invention, the local frequency is synthesized by the local frequency synthesis unit, the original reference code element in the IRIG-B code signal is extracted by the first demodulation unit and the second demodulation unit, the demodulation precision is improved, a foundation is laid for the high-precision synchronization application of the IRIG-B code signal, and the requirement of time synchronization precision is met.
Description
Technical Field
The invention relates to the technical field of data communication, in particular to a method and a system for demodulating reference time 1PPS in an IRIG-B code.
Background
With the development of modern electronic technology, time synchronization is increasingly used. The time code IRIG-B is an important time synchronization transmission mode, and becomes a preferred standard code pattern of time-domain equipment with its actually outstanding performance, and is widely applied to important industries or departments such as telecommunications, electric power, military and the like.
At present, time management equipment generally gives priority to Beidou, GPS and other satellite navigation synchronization, wei Dao output time service information generally serves as two independent signals of reference time 1PPS and time information TOD, and IRIG-B (DC) code time service has the advantages of few transmission channels, distributed time service, convenience in layout and the like, has a certain application prospect in the field of time synchronization, and has important significance for developing research of high-precision demodulation 1 PPS.
However, when the IRIG-B (DC) code is used, since the coding method is adopted to code the reference time 1PPS and the time information TOD in the same signal, the user cannot use the code directly, and the time synchronization can be performed only by decoding and demodulating the independent 1PPS and TOD information. At present, because the running clock of a single chip microcomputer is low, an IRIG-B (DC) code decoder based on the single chip microcomputer cannot process a plurality of data sources in parallel, the problems of low decoding precision and poor working stability exist, and the precision requirement of current information transmission on synchronous time cannot be met.
Disclosure of Invention
The present invention has been made to solve at least one of the problems occurring in the related art. Therefore, the invention provides a demodulation method and a demodulation system for reference time 1PPS in IRIG-B codes, which can improve demodulation precision and stability and meet the requirement of time synchronization precision.
The invention provides a demodulation method of reference time 1PPS in IRIG-B codes, which comprises the following steps:
s10, synthesizing a first frequency signal and a second frequency signal through a local frequency synthesis unit, wherein the frequency reference parameters of the first frequency signal and the second frequency signal are the same as the frequency reference parameters of an IRIG-B code signal;
s20, receiving the first frequency signal through the first demodulation unit, judging the high level state of the IRIG-B code signal when the frequency is at the falling edge, further identifying all positions in the frame of the IRIG-B code signal and identifying bit code elements, and meanwhile identifying and marking the reference code element position of the IRIG-B code signal;
s30, receiving the second frequency signal through the first demodulation unit, setting the rising edge of the second frequency signal as an on signal of the IRIG-B code signal and the falling edge of the second frequency signal as an off signal of the IRIG-B code signal at the mark position obtained in the step S20, and demodulating all position mark bit symbols and reference symbols in a frame of the IRIG-B code signal to obtain a first demodulation signal;
s40, receiving the marking information in the step S20 through a local frequency synthesis unit, and further synthesizing 11 paths of third frequency signals with the frequency of 1 Hz;
s50, receiving the first demodulation signal and 11 paths of third frequency signals with the frequency of 1Hz through a second demodulation unit, judging the high level state of the first demodulation signal at the frequency falling edge, and further identifying and marking position information of a reference code element in a frame of an IRIG-B code signal;
and S60, receiving the second frequency signal through the second demodulation unit, taking the rising edge of the second frequency signal as an opening signal for gating the first demodulation signal and taking the falling edge of the second frequency signal as a closing signal of the first demodulation signal at the mark position obtained in the step S50, and further demodulating a reference time 1PPS signal for obtaining the IRIG-B code signal.
According to the demodulation method of the reference time 1PPS in the IRIG-B code provided by the invention, in the step S10, the frequencies of the first frequency signal and the second frequency signal are both the same as the frequency of the IRIG-B code signal, and the phases of the first frequency signal and the second frequency signal are the same.
According to the demodulation method of the reference time 1PPS in the IRIG-B code, in the step S10, the periods of the first frequency signal and the second frequency signal are both T0, the phase of the first frequency signal and the phase of the second frequency signal are advanced by the time period of the IRIG-B code signal and are T, wherein T is more than or equal to T0/100 and less than or equal to T0/10.
According to the method for demodulating reference time 1PPS in IRIG-B codes, in the step S10, the high-level pulse width of the first frequency signal is Pusle _ H1, and Pusle _ H1 is less than or equal to 8ms and less than or equal to 8ms + T;
the high level pulse width of the second frequency signal is Pusle _ H2, and 8ms < T < Pusle _ H2 < T0.
According to the demodulation method of the reference time 1PPS in the IRIG-B code provided by the invention, in the step S40, the phase of the third frequency signal is advanced by T from the IRIG-B code signal time period.
According to the method for demodulating the reference time 1PPS in the IRIG-B code, in the step S40, the high-level pulse width of the third frequency signal is Pusle _ H3, and T + T0 < Pusle _ H3 < T + T0+8ms.
According to the demodulation method of the reference time 1PPS in the IRIG-B code, provided by the invention, the local frequency synthesis unit comprises a frequency reference source and an FPGA circuit, wherein a standard frequency signal is output through the frequency reference source, and the first frequency signal, the second frequency signal and the third frequency signal are synthesized through the FPGA circuit based on a clock frequency division and phase shift method.
According to the demodulation method of the reference time 1PPS in the IRIG-B code, provided by the invention, the frequency reference source comprises a rubidium clock, a constant temperature crystal oscillator or a chip type common crystal oscillator.
According to the demodulation method of the reference time 1PPS in the IRIG-B code, provided by the invention, the demodulation methods of the first demodulation unit and the second demodulation unit are realized based on an FPGA circuit.
The invention also provides a demodulation system of the reference time 1PPS in the IRIG-B code, which is used for executing the demodulation method of the reference time 1PPS in the IRIG-B code, and comprises a local frequency synthesis unit, a first demodulation unit and a second demodulation unit, wherein the local frequency synthesis unit is respectively electrically connected with the first demodulation unit and the second demodulation unit, is used for receiving the IRIG-B code signal and synthesizing a first frequency signal, a second frequency signal and a third frequency signal;
the first demodulation unit is used for receiving an IRIG-B code signal, a first frequency signal and a second frequency signal, demodulating the IRIG-B code signal and outputting a first demodulation signal;
the second demodulation unit is used for receiving the second frequency signal, the third frequency signal and the first demodulation signal, demodulating and outputting a reference time 1PPS signal.
One or more technical solutions in the embodiments of the present invention have at least one of the following technical effects:
the invention provides a demodulation method and a system of reference time 1PPS in IRIG-B codes, which comprises the following steps: s10, synthesizing a first frequency signal and a second frequency signal through a local frequency synthesis unit, wherein the reference parameters of the first frequency signal and the second frequency signal are the same as the frequency reference parameters of an IRIG-B code signal; s20, receiving the first frequency signal through the first demodulation unit, judging the high level state of the IRIG-B code signal when the frequency is at the falling edge, further identifying all positions in the frame of the IRIG-B code signal and identifying bit code elements, and meanwhile identifying and marking the reference code element position of the IRIG-B code signal; s30, receiving the second frequency signal through the first demodulation unit, setting the rising edge of the second frequency signal as an on signal of the IRIG-B code signal and the falling edge of the second frequency signal as an off signal of the IRIG-B code signal at the mark position obtained in the step S20, and demodulating all position mark bit symbols and reference symbols in a frame of the IRIG-B code signal to obtain a first demodulation signal; s40, receiving the marking information in the step S20 through a local frequency synthesis unit, and further synthesizing 11 paths of third frequency signals with the frequency of 1 Hz; s50, receiving the first demodulation signal and 11 paths of third frequency signals with the frequency of 1Hz through a second demodulation unit, judging the high level state of the first demodulation signal at a frequency falling edge, and further identifying and marking position information of a reference code element in a frame of an IRIG-B code signal; and S60, receiving the second frequency signal through the second demodulation unit, taking the rising edge of the second frequency signal as an opening signal for gating the first demodulation signal and taking the falling edge of the second frequency signal as a closing signal of the first demodulation signal at the mark position obtained in the step S50, further demodulating to obtain a reference time 1PPS signal of the IRIG-B code signal, synthesizing the local frequency through the local frequency synthesis unit, extracting an original reference code element in the IRIG-B code signal by the first demodulation unit and the second demodulation unit, improving demodulation precision, laying a foundation for high-precision synchronization application of the IRIG-B code signal, and meeting the requirement of time synchronization precision.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
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In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a block diagram illustrating a flow of a method for demodulating reference time 1PPS in an IRIG-B code according to the present invention;
FIG. 2 is a schematic diagram of a synthesized frequency of a local frequency synthesis unit in the demodulation method of reference time 1PPS in an IRIG-B code provided by the present invention;
FIG. 3 is a schematic diagram of a demodulation flow of a first demodulation unit in the method for demodulating reference time 1PPS in an IRIG-B code according to the present invention;
fig. 4 is a schematic diagram of a demodulation flow of the second demodulation unit in the method for demodulating the reference time 1PPS in the IRIG-B code provided by the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
In the description of the embodiments of the present invention, it should be noted that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the embodiments of the present invention and simplifying the description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the embodiments of the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the embodiments of the present invention, it should be noted that, unless explicitly stated or limited otherwise, the terms "connected" and "connected" are to be interpreted broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; may be directly connected or indirectly connected through an intermediate. Specific meanings of the above terms in the embodiments of the present invention may be understood as specific cases by those of ordinary skill in the art.
In embodiments of the invention, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of an embodiment of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
The following describes a demodulation method of reference time 1PPS in an IRIG-B code according to the present invention with reference to fig. 1 to 4, including the following steps:
s10, synthesizing a first frequency signal and a second frequency signal through a local frequency synthesis unit, wherein the frequency reference parameters of the first frequency signal and the second frequency signal are the same as the frequency reference parameters of an IRIG-B code signal;
s20, receiving a first frequency signal through a first demodulation unit, wherein the first frequency signal is used as a frequency reference, judging the high level state of the IRIG-B code signal when the frequency is in a falling edge, further identifying all positions in a frame of the IRIG-B code signal and identifying bit code elements, and meanwhile identifying and marking the reference code element positions of the IRIG-B code signal;
s30, receiving a second frequency signal through a first demodulation unit, wherein the second frequency signal serves as a frequency reference, setting the rising edge of the second frequency signal as an on signal of the IRIG-B code signal and the falling edge of the second frequency signal as an off signal of the IRIG-B code signal at the marked position obtained in the step S20, and demodulating all position marking bit symbols and reference symbols in the frame of the IRIG-B code signal to obtain a first demodulation signal;
s40, receiving the marking information in the step S20 through a local frequency synthesis unit, and further synthesizing 11 paths of third frequency signals with the frequency of 1 Hz;
s50, receiving the first demodulation signal and 11 paths of third frequency signals with the frequency of 1Hz through a second demodulation unit, judging the high level state of the first demodulation signal at a frequency falling edge, and further identifying and marking position information of a reference code element in a frame of an IRIG-B code signal;
and S60, receiving the second frequency signal through the second demodulation unit, wherein the second frequency signal is used as a frequency reference, and at the mark position obtained in the step S50, taking the rising edge of the second frequency signal as an opening signal for gating the first demodulation signal, taking the falling edge of the second frequency signal as a closing signal for the first demodulation signal, and further demodulating to obtain a reference time 1PPS signal of the IRIG-B code signal.
According to the demodulation method of the reference time 1PPS in the IRIG-B code provided by the invention, in the step S10, the frequencies of the first frequency signal and the second frequency signal are both the same as the frequency of the IRIG-B code signal, and the phases of the first frequency signal and the second frequency signal are the same.
According to the demodulation method of the reference time 1PPS in the IRIG-B code, in the step S10, the periods of the first frequency signal and the second frequency signal are both T0, the phase of the first frequency signal and the phase of the second frequency signal are advanced by the time period of the IRIG-B code signal and are T, wherein T is more than or equal to T0/100 and less than or equal to T0/10.
According to the method for demodulating reference time 1PPS in IRIG-B codes, in the step S10, the high-level pulse width of the first frequency signal is Pusle _ H1, and Pusle _ H1 is less than or equal to 8ms and less than or equal to 8ms + T;
the high level pulse width of the second frequency signal is Pusle _ H2, and 8ms + T < Pusle _ H2 < T0.
According to the demodulation method of the reference time 1PPS in the IRIG-B code provided by the invention, in the step S40, the phase of the third frequency signal is advanced by T from the IRIG-B code signal time period.
According to the method for demodulating the reference time 1PPS in the IRIG-B code, in the step S40, the high-level pulse width of the third frequency signal is Pusle _ H3, and T + T0 < Pusle _ H3 < T + T0+8ms.
According to the demodulation method of the reference time 1PPS in the IRIG-B code, provided by the invention, the local frequency synthesis unit comprises a frequency reference source and an FPGA circuit, wherein a standard frequency signal is output through the frequency reference source, and the first frequency signal, the second frequency signal and the third frequency signal are synthesized through the FPGA circuit based on a clock frequency division and phase shift method.
According to the demodulation method of the reference time 1PPS in the IRIG-B code, provided by the invention, the frequency reference source comprises a rubidium clock, a constant temperature crystal oscillator or a chip type common crystal oscillator.
According to the demodulation method of the reference time 1PPS in the IRIG-B code, provided by the invention, the demodulation methods of the first demodulation unit and the second demodulation unit are realized based on an FPGA circuit so as to ensure the high precision of the demodulation result.
The following describes a demodulation system of the reference time 1PPS in the IRIG-B code provided by the present invention, and the demodulation system of the reference time 1PPS in the IRIG-B code described below and the demodulation method of the reference time 1PPS in the IRIG-B code described above can be referred to correspondingly.
The invention also provides a demodulation system of the reference time 1PPS in the IRIG-B code, which is used for executing the demodulation method of the reference time 1PPS in the IRIG-B code, and comprises a local frequency synthesis unit, a first demodulation unit and a second demodulation unit, wherein the local frequency synthesis unit is respectively electrically connected with the first demodulation unit and the second demodulation unit, is used for receiving the IRIG-B code signal and synthesizing a first frequency signal, a second frequency signal and a third frequency signal;
the first demodulation unit is used for receiving an IRIG-B code signal, a first frequency signal and a second frequency signal, demodulating the IRIG-B code signal and outputting a first demodulation signal;
the second demodulation unit is used for receiving the second frequency signal, the third frequency signal and the first demodulation signal, demodulating and outputting a reference time 1PPS signal.
The following explains the specific embodiment of the demodulation method and system for the reference time 1PPS in the IRIG-B code provided by the present invention in detail, wherein the specific embodiment explains the IRIG-B (DC) signal.
As shown in fig. 1, the demodulation system for reference time 1PPS in an IRIG-B code according to an embodiment of the present invention includes a local frequency synthesis unit, a first demodulation unit, i.e., a first-stage demodulation unit shown in fig. 1, and a second demodulation unit, i.e., a second-stage demodulation unit shown in fig. 1. In this embodiment, the FPGA circuit performs frequency division and phase shift on a standard frequency output by the reference frequency scale device according to a phase of an input IRIG-B (DC) code signal, so as to realize local synthesis of a plurality of paths of frequency signals, and provide a frequency reference for the first demodulation unit and the second demodulation unit to perform high-precision demodulation of 1PPS of the IRIG-B (DC) code signal; the first demodulation unit demodulates a first demodulation signal to be used as an input signal of the second demodulation unit according to the signal characteristics of the position identification bit code elements P0-P9 and the reference code element Pr in the IRIG-B (DC) code signal frame, and the second demodulation unit realizes the high-precision demodulation of 1PPS of the IRIG-B (DC) code signal according to the signal characteristics difference of the position identification bit code elements P0-P9 and the reference code element Pr.
The method for demodulating the reference time 1PPS in the IRIG-B code provided by the embodiment of the invention specifically comprises the following steps:
s10, as shown in FIG. 2, the FPGA circuit synthesizes 2 frequency signals with the frequency of 100Hz, namely a first frequency signal Freq1 and a second frequency signal Freq2, namely frequency information 1 and frequency information 2 in FIG. 1, by using a local reference frequency, wherein the phases of Freq1 and Freq2 are consistent, the phase is advanced by 0.1ms of an IRIG-B (DC) code signal input signal, the high-level pulse width of Freq1 is 8ms, the high-level pulse width of Freq2 is 9ms, and the Freq1 and Freq2 are output as the frequency references of a first demodulation unit and a second demodulation unit;
s20, as shown in FIG. 3, the first demodulation unit judges the high level state of the IRIG-B (DC) code signal when the frequency is down by using the frequency signal Freq1 synthesized by the local frequency synthesis unit, further identifies and marks the position information of all position identification bit code elements P0-P9 and the reference code element Pr in the frame of the IRIG-B (DC) code signal, marks the position information as mark information 1, and outputs the mark information 1 to the local frequency synthesis unit;
s30, continuing to refer to FIG. 3, the first demodulation unit demodulates all position identification bit code elements P0-P9 and reference code elements Pr in a frame of the IRIG-B (DC) code signal by using the frequency signal Freq2 synthesized by the local frequency synthesis unit as an on signal of the gated IRIG-B (DC) code signal and using a falling edge of the frequency signal as an off signal of the gated IRIG-B (DC) code signal at the mark information 1, and outputs the first demodulated signal as an input signal of the second demodulation unit; it should be noted that the first demodulated signal is the first-stage demodulated information in fig. 1, fig. 3, and fig. 4;
s40, as shown in FIG. 2, the local frequency synthesis unit synthesizes 11 paths of 1Hz third frequency signals by using the mark information 1, and the signals are recorded as Freq 3-Freq 13, namely, as shown in FIG. 1, the frequency information 3-frequency information 13 is shown, the phase of the 11 paths of signals is 0.1ms ahead of the phase of the frame signal at the corresponding position of the IRIG-B (DC) code signal, and the high-level pulse width is 18ms;
s50, as shown in FIG. 4, the second demodulation unit receives the first demodulation signal output by the first demodulation unit, and utilizes 11 paths of third frequency signals Freq 3-Freq 13, the high level state of the first demodulation signal output by the first demodulation unit is judged at the frequency falling edge, the position information of the reference code element Pr in the frame of the IRIG-B (DC) code signal is identified and marked, and the position information is marked as mark information 2;
s60, with reference to fig. 4, the second demodulating unit demodulates, at the position of the mark information 2, the reference symbol Pr information in the frame of the IRIG-B (DC) code signal, that is, the reference time 1PPS information included in the IRIG-B (DC) code signal, by using the frequency signal Freq2 synthesized by the local frequency synthesizing unit, and using the rising edge of the frequency signal as an on signal for gating the first demodulated signal output by the first demodulating unit, and the falling edge signal as an off signal, and outputs the reference symbol Pr information.
One or more technical solutions in the embodiments of the present invention have at least one of the following technical effects:
the invention provides a demodulation method and a system of reference time 1PPS in IRIG-B code, comprising the following steps: s10, synthesizing a first frequency signal and a second frequency signal through a local frequency synthesis unit, wherein frequency reference parameters of the first frequency signal and the second frequency signal are the same as those of an IRIG-B code signal; s20, receiving the first frequency signal through the first demodulation unit, judging the high level state of the IRIG-B code signal when the frequency is at the falling edge, further identifying all positions in the frame of the IRIG-B code signal and identifying bit code elements, and meanwhile identifying and marking the reference code element position of the IRIG-B code signal; s30, receiving the second frequency signal through the first demodulation unit, setting the rising edge of the second frequency signal as an on signal of the IRIG-B code signal and the falling edge of the second frequency signal as an off signal of the IRIG-B code signal at the mark position obtained in the step S20, and demodulating all position mark bit symbols and reference symbols in a frame of the IRIG-B code signal to obtain a first demodulation signal; s40, receiving the marking information in the step S20 through a local frequency synthesis unit, and further synthesizing 11 paths of third frequency signals with the frequency of 1 Hz; s50, receiving the first demodulation signal and 11 paths of third frequency signals with the frequency of 1Hz through a second demodulation unit, judging the high level state of the first demodulation signal at the frequency falling edge, and further identifying and marking position information of a reference code element in a frame of an IRIG-B code signal; and S60, receiving the second frequency signal through the second demodulation unit, taking the rising edge of the second frequency signal as an opening signal for gating the first demodulation signal and taking the falling edge of the second frequency signal as a closing signal of the first demodulation signal at the mark position obtained in the step S50, further demodulating to obtain a reference time 1PPS signal of the IRIG-B code signal, synthesizing the local frequency through the local frequency synthesis unit, extracting an original reference code element in the IRIG-B code signal by the first demodulation unit and the second demodulation unit, improving demodulation precision, laying a foundation for high-precision synchronization application of the IRIG-B code signal, and meeting the requirement of time synchronization precision.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A demodulation method of reference time 1PPS in IRIG-B code is characterized by comprising the following steps:
s10, synthesizing a first frequency signal and a second frequency signal through a local frequency synthesis unit, wherein the frequency reference parameters of the first frequency signal and the second frequency signal are the same as the frequency reference parameters of an IRIG-B code signal;
s20, receiving the first frequency signal through the first demodulation unit, judging the high level state of the IRIG-B code signal when the frequency is at the falling edge, further identifying all positions in the frame of the IRIG-B code signal and identifying bit code elements, and meanwhile identifying and marking the reference code element position of the IRIG-B code signal;
s30, receiving the second frequency signal through the first demodulation unit, setting the rising edge of the second frequency signal as an on signal of the IRIG-B code signal and the falling edge of the second frequency signal as an off signal of the IRIG-B code signal at the mark position obtained in the step S20, and demodulating all position mark bit symbols and reference symbols in a frame of the IRIG-B code signal to obtain a first demodulation signal;
s40, receiving the marking information in the step S20 through a local frequency synthesis unit, and further synthesizing 11 paths of third frequency signals with the frequency of 1 Hz;
s50, receiving the first demodulation signal and 11 paths of third frequency signals with the frequency of 1Hz through a second demodulation unit, judging the high level state of the first demodulation signal at a frequency falling edge, and further identifying and marking position information of a reference code element in a frame of an IRIG-B code signal;
and S60, receiving the second frequency signal through the second demodulation unit, taking the rising edge of the second frequency signal as an opening signal for gating the first demodulation signal and taking the falling edge of the second frequency signal as a closing signal for the first demodulation signal at the mark position obtained in the step S50, and further demodulating to obtain a reference time 1PPS signal of the IRIG-B code signal.
2. The method according to claim 1, wherein in the step S10, the frequencies of the first frequency signal and the second frequency signal are both the same as the frequency of the IRIG-B code signal, and the phases of the first frequency signal and the second frequency signal are the same.
3. The method for demodulating reference time 1PPS in IRIG-B code according to claim 2, wherein in the step S10, the periods of the first frequency signal and the second frequency signal are both T0, the phases of the first frequency signal and the second frequency signal are advanced by the period of time T of the IRIG-B code signal, and T0/100 ≦ T0/10.
4. The method for demodulating reference time 1PPS in IRIG-B code according to claim 3, characterized in that in step S10, the high level pulse width of the first frequency signal is Pusle _ H1, and Pusle _ H1 is less than or equal to 8ms and is < 8ms + T;
the high level pulse width of the second frequency signal is Pusle _ H2, and 8ms + T < Pusle _ H2 < T0.
5. The method for demodulating IRIG-B code with reference time 1PPS according to claim 3, wherein in the step S40, the phase of the third frequency signal is advanced by the time period T of the IRIG-B code signal.
6. The method for demodulating reference time 1PPS in an IRIG-B code according to claim 5, wherein in the step S40, a high-level pulse width of the third frequency signal is Pusle _ H3, and T + T0 < Pusle _ H3 < T + T0+8ms.
7. The method for demodulating reference time 1PPS in an IRIG-B code according to claim 1, wherein the local frequency synthesis unit includes a frequency reference source and an FPGA circuit, wherein a standard frequency signal is output by the frequency reference source, and the first frequency signal, the second frequency signal and the third frequency signal are synthesized by the FPGA circuit based on a clock frequency division and phase shift method.
8. The method of demodulating reference time 1PPS in an IRIG-B code according to claim 7, wherein the frequency reference source includes a rubidium clock, a constant temperature crystal, or a chip-type common crystal.
9. The method for demodulating IRIG-B code reference time 1PPS according to claim 1, wherein the demodulation method of the first demodulation unit and the demodulation method of the second demodulation unit are implemented based on FPGA circuit.
10. A system for demodulating reference time 1PPS in an IRIG-B code, configured to perform the method for demodulating reference time 1PPS in an IRIG-B code according to any one of claims 1 to 9, comprising a local frequency synthesis unit, a first demodulation unit and a second demodulation unit, wherein the local frequency synthesis unit is electrically connected to the first demodulation unit and the second demodulation unit, respectively, and configured to receive an IRIG-B code signal and synthesize a first frequency signal, a second frequency signal and the third frequency signal;
the first demodulation unit is used for receiving an IRIG-B code signal, a first frequency signal and a second frequency signal, demodulating the IRIG-B code signal and outputting a first demodulation signal;
the second demodulation unit is used for receiving the second frequency signal, the third frequency signal and the first demodulation signal, demodulating and outputting a reference time 1PPS signal.
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