CN105763199A

CN105763199A - FPGA-based IRIG-B(DC) fast decoding method

Info

Publication number: CN105763199A
Application number: CN201610227361.9A
Authority: CN
Inventors: 李孟阳; 唐立君; 张林山; 杨映春
Original assignee: Guangzhou Zhixun Information Science & Technology Co Ltd; Electric Power Research Institute of Yunnan Power System Ltd
Current assignee: Guangzhou Zhixun Information Science & Technology Co Ltd; Electric Power Research Institute of Yunnan Power System Ltd
Priority date: 2016-04-13
Filing date: 2016-04-13
Publication date: 2016-07-13

Abstract

An FPGA-based IRIG-B(DC) fast decoding method is disclosed and the method comprises an IRIG-B(DC) fast decoding step and a step of sending decoding messages via serial ports after the decoding messages are packeted. According to the FPGA-based IRIG-B(DC) fast decoding method, via use of FPGA technologies, on-line data monitoring technologies, serial port communication technologies and the like, defects of a conventional IRIG-B code time unification system developed via use of discrete elements can be address, wherein the defects of the conventional IRIG-B code time unification system is are circuit complexity, low integration level, difficult-to-debug characteristic, large size, high cost, low confidentiality and the like; most requirements for precision can also be met by the FPGA-based IRIG-B(DC) fast decoding method.

Description

A kind of IRIG-B (DC) fast decoding method based on FPGA

Technical field

The invention belongs to a kind of IRIG-B (DC) fast decoding method technical field based on FPGA

Background technology

At present with discrete component exploitation and the IRIG-B code timing system developed have that circuit is complicated, integrated level is low, The shortcomings such as debugging difficulty, volume is big, cost is high, confidentiality is low, and along with information technology revolution and the at full speed of computer technology are sent out Exhibition, programmable logic technology has evolved into ripe.In order to reach IRIG-B code and the precise synchronization of time signal, stable performance, collection One-tenth volume is little, low cost of manufacture, it is proposed that realize, based on FPGA, the method that IRIG-B (DC) code quickly decodes.The method achieve IRIG-B (DC) code demodulates 1pps signal and clock message, and clock message carries out packet transmission by serial ports.

Summary of the invention

The purpose of the present invention is precisely in order to overcome defect that above-mentioned prior art exists and provide a kind of precise synchronization, performance Stablize, integrated volume is little, IRIG-B (DC) fast decoding method based on FPGA of low cost of manufacture.

It is an object of the invention to realize by following technical solution.

A kind of IRIG-B (DC) fast decoding method based on FPGA, present invention is characterized in that IRIG-B (DC) decoding and The packet serial ports transmission of decoding message realizes process and all uses hardware description language based on FPGA to realize.

In IRIG-B of the present invention (DC) 100Hz clock serial code, the demodulation of 2ms, 5ms, 8ms pulse width signal uses with 10kHz On the basis of clock counting 2ms, 5ms, 8ms pulse width signal, if the symbol width counted to get is 75～85, this code element is 8ms pulsewidth；If the symbol width counted to get is 45～55, this code element is 5ms pulsewidth；If the symbol width counted to get is 15 ～25, this code element is 2ms pulsewidth.

Identification IRIG-B (DC) 100Hz clock serial code start bit of the present invention is to use 8ms pulse width signal rolling counters forward, By 2ms, 5ms pulse width signal phase or afterwards as this counter O reset end mode.

The present invention use finite state machine level high and low to 5ms pulse width signal carry out detection obtain data bit 1,0 composition time Clock message.

Beneficial effects of the present invention

Can be fully completed under one piece of fpga chip because IRIG-B (DC) code quickly decodes, and function used all uses Hardware description language realizes, and quickly decodes have IRIG-B code and time signal so using FPGA to realize IRIG-B (DC) code The advantages such as precise synchronization, stable performance, little, the low cost of manufacture of integrated volume..Meanwhile, utilize existing FPGA to ASIC hardware Duplication technology (such as the HardCopy technology of altera corp), can be by designed power and energy for the IRIG-B of specialty (DC) decoding chip, has saved hardware resource redundancy issue.

Accompanying drawing explanation

Fig. 1 is IRIG-B (DC) code schematic diagram；

Fig. 2 IRIG-B (DC) code quickly decodes and realizes principle；

Fig. 3 IRIG-B (DC) code data parsing sequential chart；

Fig. 4 serial ports sends byte data sequential chart.

Detailed description of the invention

Below in conjunction with accompanying drawing, the embodiment of the present invention is further described, in detail below implementation content and Fig. 2 IRIG-B (DC) code quickly decodes and realizes schematic diagram and will include protection scope of the present invention in.

IRIG-B (DC) code (being called for short B code) is a kind of BCD serial time code, and each symbol width is 10ms, compiles for pulsewidth Code is (as it is shown in figure 1, pulsewidth 2ms, 5ms and 8ms represent binary system " 0 ", " 1 " and time frame reference mark P respectively_ROr location recognition Mark P).When one, the frame period includes 100 code elements, and " on time " reference point of code element is its pulse front edge, from time frame with reference to mark Will P_RStarting to count, every 10 code elements have a location recognition mark P, and they pulsewidths are 8ms.Therefore, continuous two pulsewidths The beginning in frame period when representing for 8ms pulse, if from second 8ms code element (i.e. time frame reference mark P_R) start coding, then Element position is respectively P0, P1, P2 ..., P99.If the coded format of IRIG-B code is written as:

<sync>sS:MM:HH:DDD:YY:<control><binary seconds>, wherein the definition of each field is such as Under:

■<sync>: time synchronized mark (element position P0)；

■ SS: the second (element position P1～P4 be second position, P6～P8 be the second ten, scope 00～59, when leap second occurs May be 60)；

■ MM: divide (element position P10～P13 is to divide ten for a point individual position, P15～P17, scope 00～59)；

■ HH: time (when when element position P20～P23 is, a position, P25～P26 are ten, scope 00～23)；

■ DDD: day (element position P30～P33 be day position, P35～P38 be day ten, P40～P41 be day hundred, Scope 00～366)；

■ YY: year (element position P50～P53 be year position, P55～P58 be Nian Shiwei, scope 00～99)；

■<control>: binary system control bit；

■<binary seconds>: the number of seconds (SBS straight binary second-of-day) in a day.

IRIG-B (DC) fast decoding method based on FPGA, quickly decoding and decoding message including IRIG-B (DC) Packet serial ports sends, and its functional realiey principle is as shown in Figure 2.

In fig. 2, the effect of pulsewidth identification module is to demodulate 2ms, 5ms, the 8ms in IRIG-B (DC) serial time code Pulse width signal.When its principle is B code (IRIG-B (DC) code abbreviation) rising edge to be detected, respectively at 2ms, 5ms, 8ms holding wire Upper output low level, resets and starts the enumerator with 10KHz as clock signal；When the trailing edge of B code, stop counter counts Number, then Counter Value is judged, if Counter Value is 75～85, then on 8ms holding wire, export high level；If enumerator Value is 45～55, then export high level on 5ms holding wire；If Counter Value is 15～25, then output height on 2ms holding wire Level.Here the value of enumerator does not select to be because B code after transmission or interference it may happen that wave distortion with definite value, is intended to Redundancy Design is considered when differentiating symbol width.

IRIG-B (DC) 100Hz clock serial code start bit identification module uses 8ms pulse width signal rolling counters forward, by 2ms, 5ms pulse width signal phase or afterwards as this counter O reset end mode.Its principle is to 8ms signal-count, with 5ms or 2ms Signal resets, and when 2 8ms marking signals of continuous print being detected, i.e. have found the frame head of B code, exports reset signal.

To B code cell count during the effect of 0～99 symbol counter, resolve 1pps signal.In symbol counter, when clearly Zero pulse signal arrives and (P i.e. detected_R) time by clear for symbol counter 0, put 1pps holding wire is high level simultaneously；Work as enumerator When counting down to 49, putting 1pps holding wire is high level.

Data resolution module is made up of baud rate time block and data acquisition module, and its effect is to resolve in B code to be taken The temporal information of band, and output it or store.The design uses a 100Hz clock offset to detect 5ms marking signal Method resolve temporal information.Its principle is: 10kHz clock signal frequency dividing is one by first baud rate time block The clock signal of 100Hz, (i.e. IRIG-B (DC) code upper of the rising edge clock signal of this 100Hz relatively reset signal rising edge Rise edge) step back about 3/ (4*bps) (wherein 1/bps is the cycle of each code element), just at 5ms pulsewidth marking signal high level Centre, such as Fig. 3.The value of 5ms pulsewidth marking signal is detected between 100Hz clock signal high period, if 1, then according to now Carving the value of cell count in data acquisition module, putting corresponding data bit is 1；If 0, then according to this moment data acquisition module The value of middle cell count, putting corresponding data bit is 0.Owing to B code temporal information is stored between specific code element, so, the time Output information signal line only connects and stores the data bit of temporal information.

In Fig. 2 the effect of time message packet transmission control module be by the year comprised in temporal information, sky, time, minute, second Information splits into 5 bytes respectively, controls serial ports sending module and sends successively.

Serial ports sending module is sent control module by baud rate time block and byte and forms, and its effect is to send out according to serial ports Send timing protocols, send a byte data.Baud rate time block produces timing and sends a signal to byte transmission control module, This control module will be according to this beat by one one sends of data.Assume that the baud rate that I configures is 9600bps, then every 0.000104166666666667s, baud rate time block will produce a high impulse to byte Sending control module, frame data have 11, then baud rate time block needs to produce 12 timings, such as Fig. 4.

Host computer data parsing for convenience, we add 0xFFFF in time message packet transmission original position, upper Machine is being consecutively detected two 0xFF, starts to resolve data, synchronizes host computer clock.

Claims

1. IRIG-B (DC) fast decoding method based on FPGA, it is characterised in that: IRIG-B (DC) decodes and decodes report The packet serial ports transmission of literary composition realizes process and all uses hardware description language based on FPGA to realize.

2. in IRIG-B (DC) fast decoding method based on FPGA, it is characterised in that: IRIG-B (DC) 100Hz clock string In row code, the demodulation of 2ms, 5ms, 8ms pulse width signal uses and carries out 2ms, 5ms, 8ms pulse width signal on the basis of 10kHz clock Counting, if the symbol width counted to get is 75～85, this code element is 8ms pulsewidth；If the symbol width counted to get be 45～ 55, this code element is 5ms pulsewidth；If the symbol width counted to get is 15～25, this code element is 2ms pulsewidth.

3. in IRIG-B (DC) fast decoding method based on FPGA, it is characterised in that: when identifying IRIG-B (DC) 100Hz Clock serial code start bit is to use 8ms pulse width signal rolling counters forward, by 2ms, 5ms pulse width signal phase or afterwards as this enumerator Clear terminal mode.

4. in IRIG-B (DC) fast decoding method based on FPGA, it is characterised in that: use finite state machine to 5ms arteries and veins The high and low level of bandwidth signals carries out detection and obtains data bit 1,0 composition clock message.