CN115547919A - Fdsoi混合区域的外延生长方法 - Google Patents

Fdsoi混合区域的外延生长方法 Download PDF

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CN115547919A
CN115547919A CN202110723559.7A CN202110723559A CN115547919A CN 115547919 A CN115547919 A CN 115547919A CN 202110723559 A CN202110723559 A CN 202110723559A CN 115547919 A CN115547919 A CN 115547919A
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fdsoi
epitaxial growth
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陈勇跃
颜强
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Abstract

本发明公开了一种FDSOI混合区域的外延生长方法，包括：步骤一、提供一FDSOI衬底结构并形成硬掩膜层；步骤二、在整个混合区域形成沟槽，沟槽的底部表面位于半导体主体层的顶部表面之下；步骤三、进行氧化在暴露的半导体主体层和半导体顶层表面形成第一氧化层；步骤四、对第一氧化层进行全面刻蚀在沟槽的侧面自对准形成由保留的第一氧化层组成的内侧墙；步骤五、进行外延生长在沟槽中形成和半导体主体层相接触的半导体外延层。本发明能消除在混合区域边界处产生半导体外延层的凸起缺陷，提高半导体外延层表面的平坦性，还能使工艺得到整体改善。

Description

FDSOI混合区域的外延生长方法
技术领域
本发明涉及一种半导体集成电路制造方法，特别涉及一种全耗尽型绝缘体上硅(Fully Depleted Semiconductor On Insulator,FDSOI)混合(Hybrid)区域的外延生长方法。
背景技术
随着集成电路的持续飞速发展，电路中器件关键尺寸持续缩小，对应组成元器件的薄膜厚度也在持续减薄，FDSOI成为一种克服短沟道效应的选择，同时对制作工艺中的缺陷要求越来越高，最终实现缺陷零容忍。
FDSOI工艺中，衬底结构包括半导体主体层，介质埋层和半导体顶层，介质埋层形成于半导体主体层表面，半导体顶层形成于介质埋层表面；通常，半导体主体层和半导体顶层的材料采用Si。半导体顶层通常称为SOI层，半导体顶层具有超薄结构，利用超薄的半导体顶层形成半导体器件能得到超薄晶体管，从能很好的控制晶体管的短沟道效应，进而可以降低供电电压。
FDSOI工艺中，除了需要在半导体顶层中形成超薄晶体管如CMOS器件外，有时还需要形成和底部的半导体主体层相接触的无源器件和引出结构(pickup)。为了形成这些和底部的半导体主体层相接触的无源器件和引出结构，需要在FDSOI中形成直接和底部的所述半导体主体层直接接触且顶部表面和半导体顶层的顶部表面相平的半导体外延硅，这就需要单独定义混合区域来形成和半导体主体层直接接触的半导体外延层。现有FDSOI混合区域的外延生长方法中，由于外延工艺本身的性质，在生长半导体外延如硅外延过程中，由于混合区域和混合区域外的SOI区域的边界处的半导体顶层也会产生附加外延，这会导致在Hybrid区域的半导体外延层的生长模式受到干扰，最终在边界处形成凸起缺陷，改善生长工艺能减弱这种缺陷到能接受的程度，但无法完全消除。
如图1所示，是现有FDSOI混合区域的外延生长方法完成后的器件结构示意图；FDSOI衬底包括半导体主体层101，介质埋层102和半导体顶层103。为了定义出混合区域，还会在半导体顶层103的顶部形成硬掩膜层104；之后采用光刻工艺打开混合区域，对混合区域的硬掩膜层104、半导体顶层103和介质埋层102进行刻蚀形成沟槽，沟槽的底部表面1051需要保证半导体主体层101的表面露出。之后，在露出的半导体主体层101的表面上形成半导体外延层106。但是，在半导体外延层106的生长过程中，沟槽的侧面1052处露出的半导体顶层103也会生长外延层，最后会使得对整个半导体外延层106的生长产生干扰并会形成凸起缺陷1061。
发明内容
本发明所要解决的技术问题是提供一种FDSOI混合区域的外延生长方法，能消除混合区域边界处的半导体外延层的凸起缺陷，改善工艺。
为解决上述技术问题，本发明提供的FDSOI混合区域的外延生长方法包括如下步骤：
步骤一、提供一FDSOI衬底结构，所述FDSOI衬底包括半导体主体层，介质埋层和半导体顶层，所述介质埋层形成于所述半导体主体层表面，所述半导体顶层形成于所述介质埋层表面；在所述半导体顶层表面形成硬掩膜层。
步骤二、在整个混合区域形成沟槽，所述沟槽内的所述硬掩膜层、所述半导体顶层和所述介质埋层全部被去除，所述沟槽的底部表面位于所述半导体主体层的顶部表面之下并将所述半导体主体层的表面暴露出来，所述沟槽的侧面将所述沟槽深度范围内的所述硬掩膜层、所述半导体顶层、所述介质埋层和所述半导体主体层侧面暴露。
步骤三、进行氧化在暴露的所述半导体主体层和所述半导体顶层表面形成第一氧化层。
步骤四、对所述第一氧化层进行全面刻蚀将所述沟槽的底部表面的所述第一氧化层全部去除以及在所述沟槽的侧面自对准形成由保留的所述第一氧化层组成的内侧墙。
步骤五、进行外延生长在所述沟槽中形成和所述半导体主体层相接触的半导体外延层。
进一步的改进是，所述半导体主体层的材料包括硅或锗。
进一步的改进是，所述介质埋层的材料包括氧化硅，高介电常数材料。
进一步的改进是，所述半导体顶层的材料包括硅或锗。
进一步的改进是，所述半导体外延层的材料包括硅或锗。
进一步的改进是，所述硬掩膜层由第一氧化硅层和第二氮化硅层叠加而成。
进一步的改进是，步骤二中，通过光刻工艺定义出所述混合区域，通过刻蚀工艺形成所述沟槽，所述沟槽的刻蚀工艺将所述混合区域中的所述硬掩膜层、所述半导体顶层和所述介质埋层全部去除，所述沟槽的刻蚀工艺对所述半导体主体层的不刻蚀或者部分刻蚀。
进一步的改进是，步骤三中，形成的所述第一氧化层的厚度为
Figure BDA0003137554590000031
进一步的改进是，所述半导体顶层的厚度达12nm以下。
进一步的改进是，步骤四中采用干法刻蚀工艺对所述第一氧化层进行全面刻蚀。
进一步的改进是，步骤五中外延生长完成后所述半导体外延层的顶部表面和所述半导体顶层的顶部表面相平。
进一步的改进是，步骤五中，采用RPCVD工艺进行所述半导体外延层的外延生长。
进一步的改进是，所述混合区域的所述半导体外延层的表面用于形成需要和所述半导体主体层相连的无源器件或引出结构。
进一步的改进是，所述混合区域外的所述半导体顶层中用于形成CMOS器件。
进一步的改进是，所述CMOS器件包括PMOS器件和NMOS器件。
本发明在进行混合区域的沟槽形成之前以及外延生长之前，增加的氧化工艺以及对氧化形成的第一氧化层进行全面刻蚀工艺在沟槽的侧面形成内侧墙，内侧墙能消除从暴露在沟槽中的半导体顶层的侧面处生长外延层也即能保证外延生长为严格的从底部往顶部生长，从而能消除在混合区域边界处产生半导体外延层的凸起缺陷，最后提高半导体外延层表面的平坦性。
另外，由于氧化工艺仅对暴露的半导体主体层进行氧化从而能使第一氧化层自对准形成在半导体顶层和半导体主体层表面上且能使第一氧化层的厚度控制到很薄，使得形成的内侧墙不会占据额外空间并从而不会改变半导体外延层的形貌，不会影响外延生长的从底部向顶部生长的模式，所以，本发明的内侧墙的形成工艺不会对外延生长产生新的不利影响，最后能使工艺得到整体改善。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细的说明：
图1是现有FDSOI混合区域的外延生长方法完成后的器件结构示意图；
图2是本发明实施例FDSOI混合区域的外延生长方法的流程图；
图3A-图3E是本发明实施例FDSOI混合区域的外延生长方法的各步骤中的器件结构示意图。
具体实施方式
如图2所示，是本发明实施例FDSOI混合区域的外延生长方法的流程图；如图3A至图3E所示，是本发明实施例FDSOI混合区域的外延生长方法的各步骤中的器件结构示意图；本发明实施例FDSOI混合区域的外延生长方法包括如下步骤：
步骤一、如图3A所示，提供一FDSOI衬底结构，所述FDSOI衬底包括半导体主体层201，介质埋层202和半导体顶层203，所述介质埋层202形成于所述半导体主体层201表面，所述半导体顶层203形成于所述介质埋层202表面；在所述半导体顶层203表面形成硬掩膜层204。
本发明实施例中，所述半导体主体层201的材料为硅。在其他实施例中也能为：所述半导体主体层201的材料为锗或者为锗和硅的组合。
所述介质埋层202的材料包括氧化硅，高介电常数材料。
所述半导体顶层203的材料包括硅。在其他实施例中也能为：所述半导体顶层203的材料为锗或者为锗和硅的组合。
所述半导体顶层203的厚度达12nm以下。
所述硬掩膜层204由第一氧化硅层和第二氮化硅层叠加而成。
步骤二、如图3B所示，在整个混合区域形成沟槽，所述沟槽内的所述硬掩膜层204、所述半导体顶层203和所述介质埋层202全部被去除，所述沟槽的底部表面2051位于所述半导体主体层201的顶部表面之下并将所述半导体主体层201的表面暴露出来，所述沟槽的侧面2052将所述沟槽深度范围内的所述硬掩膜层204、所述半导体顶层203、所述介质埋层202和所述半导体主体层201侧面暴露。
本发明实施例中，通过光刻工艺定义出所述混合区域，通过刻蚀工艺形成所述沟槽，所述沟槽的刻蚀工艺将所述混合区域中的所述硬掩膜层204、所述半导体顶层203和所述介质埋层202全部去除，所述沟槽的刻蚀工艺对所述半导体主体层201的不刻蚀或者部分刻蚀；例如：当所述沟槽的底部表面2051和所述半导体主体层201的顶部表面相平时，所述沟槽的刻蚀工艺就不需要对所述半导体主体层201的进行刻蚀；当所述沟槽的底部表面2051低于所述半导体主体层201的顶部表面时，所述沟槽的刻蚀工艺就需要对所述半导体主体层201的进行刻蚀。
步骤三、如图3C所示，进行氧化在暴露的所述半导体主体层201和所述半导体顶层203表面形成第一氧化层，位于所述沟槽的底部表面2051的所述第一氧化层单独用标记2061标出，位于所述沟槽的侧面2052的所述第一氧化层单独用标记2062标出。
由图3C所示，由于在所述沟槽的底部表面2051暴露的区域全部是所述半导体主体层201的表面，故在所述沟槽的底部表面2051会被全部氧化。所述沟槽的侧面2052仅会在暴露的所述半导体主体层201和所述半导体顶层203的表面会被氧化。
本发明实施例中，形成的所述第一氧化层的厚度为
Figure BDA0003137554590000051
步骤四、如图3D所示，对所述第一氧化层进行全面刻蚀将所述沟槽的底部表面2051的所述第一氧化层2061全部去除以及在所述沟槽的侧面2052自对准形成由保留的所述第一氧化层2062组成的内侧墙。
本发明实施例中，采用干法刻蚀工艺对所述第一氧化层进行全面刻蚀。
步骤五、如图3E所示，进行外延生长在所述沟槽中形成和所述半导体主体层201相接触的半导体外延层207。
本发明实施例中，所述半导体外延层207的材料包括硅。在其他实施例中也能为：所述半导体外延层207的材料为锗或者为锗和硅的组合。
步骤五中外延生长完成后所述半导体外延层207的顶部表面和所述半导体顶层203的顶部表面相平。较佳为，采用RPCVD工艺进行所述半导体外延层207的外延生长。
所述混合区域的所述半导体外延层207的表面用于形成需要和所述半导体主体层201相连的无源器件或引出结构。
所述混合区域外的所述半导体顶层203中用于形成CMOS器件。所述CMOS器件包括PMOS器件和NMOS器件。由于所述半导体顶层203为超薄层，故能改善PMOS器件和NMOS器件的短沟道效应，能提高PMOS器件和NMOS器件的性能。
本发明实施例在进行混合区域的沟槽形成之前以及外延生长之前，增加的氧化工艺以及对氧化形成的第一氧化层进行全面刻蚀工艺在沟槽的侧面2052形成内侧墙，内侧墙能消除从暴露在沟槽中的半导体顶层203的侧面处生长外延层也即能保证外延生长为严格的从底部往顶部生长，从而能消除在混合区域边界处产生半导体外延层207的凸起缺陷，最后提高半导体外延层207表面的平坦性。
另外，由于氧化工艺仅对暴露的半导体主体层201进行氧化从而能使第一氧化层自对准形成在半导体顶层203和半导体主体层201表面上且能使第一氧化层的厚度控制到很薄，使得形成的内侧墙不会占据额外空间并从而不会改变半导体外延层207的形貌，不会影响外延生长的从底部向顶部生长的模式，所以，本发明实施例的内侧墙的形成工艺不会对外延生长产生新的不利影响，最后能使工艺得到整体改善。
以上通过具体实施例对本发明进行了详细的说明，但这些并非构成对本发明的限制。在不脱离本发明原理的情况下，本领域的技术人员还可做出许多变形和改进，这些也应视为本发明的保护范围。

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1.一种FDSOI混合区域的外延生长方法，其特征在于，包括如下步骤：
步骤一、提供一FDSOI衬底结构，所述FDSOI衬底包括半导体主体层，介质埋层和半导体顶层，所述介质埋层形成于所述半导体主体层表面，所述半导体顶层形成于所述介质埋层表面；在所述半导体顶层表面形成硬掩膜层；
步骤二、在整个混合区域形成沟槽，所述沟槽内的所述硬掩膜层、所述半导体顶层和所述介质埋层全部被去除，所述沟槽的底部表面位于所述半导体主体层的顶部表面之下并将所述半导体主体层的表面暴露出来，所述沟槽的侧面将所述沟槽深度范围内的所述硬掩膜层、所述半导体顶层、所述介质埋层和所述半导体主体层侧面暴露；
步骤三、进行氧化在暴露的所述半导体主体层和所述半导体顶层表面形成第一氧化层；
步骤四、对所述第一氧化层进行全面刻蚀将所述沟槽的底部表面的所述第一氧化层全部去除以及在所述沟槽的侧面自对准形成由保留的所述第一氧化层组成的内侧墙；
步骤五、进行外延生长在所述沟槽中形成和所述半导体主体层相接触的半导体外延层。
2.如权利要求1所述的FDSOI混合区域的外延生长方法，其特征在于：所述半导体主体层的材料包括硅或锗。
3.如权利要求1所述的FDSOI混合区域的外延生长方法，其特征在于：所述介质埋层的材料包括氧化硅，高介电常数材料。
4.如权利要求1所述的FDSOI混合区域的外延生长方法，其特征在于：所述半导体顶层的材料包括硅或锗。
5.如权利要求2所述的FDSOI混合区域的外延生长方法，其特征在于：所述半导体外延层的材料包括硅或锗。
6.如权利要求1所述的FDSOI混合区域的外延生长方法，其特征在于：所述硬掩膜层由第一氧化硅层和第二氮化硅层叠加而成。
7.如权利要求1所述的FDSOI混合区域的外延生长方法，其特征在于：步骤二中，通过光刻工艺定义出所述混合区域，通过刻蚀工艺形成所述沟槽，所述沟槽的刻蚀工艺将所述混合区域中的所述硬掩膜层、所述半导体顶层和所述介质埋层全部去除，所述沟槽的刻蚀工艺对所述半导体主体层的不刻蚀或者部分刻蚀。
8.如权利要求1所述的FDSOI混合区域的外延生长方法，其特征在于：步骤三中，形成的所述第一氧化层的厚度为
Figure FDA0003137554580000021
9.如权利要求1所述的FDSOI混合区域的外延生长方法，其特征在于：所述半导体顶层的厚度达12nm以下。
10.如权利要求1所述的FDSOI混合区域的外延生长方法，其特征在于：步骤四中采用干法刻蚀工艺对所述第一氧化层进行全面刻蚀。
11.如权利要求1所述的FDSOI混合区域的外延生长方法，其特征在于：步骤五中外延生长完成后所述半导体外延层的顶部表面和所述半导体顶层的顶部表面相平。
12.如权利要求1所述的FDSOI混合区域的外延生长方法，其特征在于：步骤五中，采用RPCVD工艺进行所述半导体外延层的外延生长。
13.如权利要求1所述的FDSOI混合区域的外延生长方法，其特征在于：所述混合区域的所述半导体外延层的表面用于形成需要和所述半导体主体层相连的无源器件或引出结构。
14.如权利要求1所述的FDSOI混合区域的外延生长方法，其特征在于：所述混合区域外的所述半导体顶层中用于形成CMOS器件。
15.如权利要求14所述的FDSOI混合区域的外延生长方法，其特征在于：所述CMOS器件包括PMOS器件和NMOS器件。
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