CN115132645A - 一种fdsoi的制作方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 76
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 76
- 239000010703 silicon Substances 0.000 claims abstract description 76
- 239000012212 insulator Substances 0.000 claims abstract description 36
- 238000005530 etching Methods 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 28
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000004528 spin coating Methods 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 239000002131 composite material Substances 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 8
- 230000007547 defect Effects 0.000 description 4
- 230000003667 anti-reflective effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
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- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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Abstract
本发明提供一种FDSOI的制作方法,提供半导体结构,该半导体结构包括硅基底;位于硅基底上的埋氧层;位于埋氧层上的绝缘体上硅;位于绝缘体上硅的硬掩模层;在硬掩模层上旋涂光刻胶并曝光显影,形成体硅区;等离子各向异性刻蚀体硅区,打开部分埋氧层;之后进行各向同性刻蚀,绝缘体上硅在水平方向上形成内缩;等离子各向异性刻蚀,将埋氧层刻穿,形成体硅区沟槽;去除光刻胶及刻蚀残余物;在体硅区沟槽中进行硅外延生长。相对于现有技术中的FDSOI制作方法,本发明的绝缘体上硅形成内缩,体硅区沟槽形成后绝缘体上硅仍然内缩,绝缘体上硅的表面没有***,工艺窗口得到控制。
Description
技术领域
本发明涉及半导体技术领域,特别是涉及一种FDSOI的制作方法。
背景技术
现有22nm FDSOI衬底的体硅区硅外延生长(Si-Epi)时,硅外延结束之后最终形成一个高于SOI表面的***,这一缺陷造成硅片表面不平坦,不仅对后续的光刻、等离子刻蚀等工艺造成影响,还会形成图形连接,降低了FDSOI工艺窗口。
因此,需要提出一种新的制作FDSOI的方法来解决上述问题。
发明内容
鉴于以上所述现有技术的缺点,本发明的目的在于提供一种FDSOI的制作方法,用于解决现有技术中由于FDSOI制作过程中硅外延后形成表面***,从而降低工艺窗口的问题。
为实现上述目的及其他相关目的,本发明提供一种FDSOI的制作方法,至少包括以下步骤:
步骤一、提供半导体结构,该半导体结构包括:硅基底;位于所述硅基底上的埋氧层;位于所述埋氧层上的绝缘体上硅;位于所述绝缘体上硅的硬掩模层;
步骤二、在所述硬掩模层上旋涂光刻胶并曝光显影,形成体硅区;
步骤三、等离子各向异性刻蚀所述体硅区,打开部分所述埋氧层;之后进行各向同性刻蚀,所述绝缘体上硅在水平方向上形成内缩;
步骤四、等离子各向异性刻蚀,将所述埋氧层刻穿,形成体硅区沟槽;
步骤五、去除光刻胶及刻蚀残余物;
步骤六、在所述体硅区沟槽中进行硅外延生长。
优选地,步骤一中的所述硬掩模层为氮化硅或由氧化硅层和氮化硅层构成的复合层,该复合层中氮化硅层位于氧化硅层之上。
优选地,步骤二中的所述光刻胶包含减反射层。
优选地,步骤五中去除光刻胶及刻蚀残余物的方法包括湿法去除法或湿法去除和干法去除组合的方法。
优选地,步骤六中进行硅外延生长后的硅表面与所述绝缘体上硅的上表面齐平。
如上所述,本发明的FDSOI的制作方法,具有以下有益效果:相对于现有技术中的FDSOI制作方法,本发明的绝缘体上硅形成内缩,体硅区沟槽形成后绝缘体上硅仍然内缩,绝缘体上硅的表面没有***,工艺窗口得到控制。
附图说明
图1显示为本发明中将半导体结构刻蚀打开部分埋氧层后的结构示意图;
图2显示为本发明各向同性刻蚀后绝缘体上硅形成内缩的结构示意图;
图3显示为本发明中刻蚀形成体硅区沟槽的结构示意图;
图4显示为本发明中在所述体硅区沟槽中进行硅外延生长形成硅外延层的结构示意图;
图5显示为本发明中进行硅外延生长后的硅表面与绝缘体上硅上表面齐平的结构示意图;
图6显示为本发明中FDSOI的制作方法流程图。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式,本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用,本说明书中的各项细节也可以基于不同观点与应用,在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1至图6。需要说明的是,本实施例中所提供的图示仅以示意方式说明本发明的基本构想,遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制,其实际实施时各组件的型态、数量及比例可为一种随意的改变,且其组件布局型态也可能更为复杂。
本发明提供一种FDSOI的制作方法,如图6所示,图6显示为本发明中FDSOI的制作方法流程图,该方法至少包括以下步骤:
步骤一、提供半导体结构,该半导体结构包括:硅基底;位于所述硅基底上的埋氧层;位于所述埋氧层上的绝缘体上硅;位于所述绝缘体上硅的硬掩模层。
本发明进一步地,本实施例的步骤一中的所述硬掩模层为氮化硅或由氧化硅层和氮化硅层构成的复合层,该复合层中氮化硅层位于氧化硅层之上。本实施例中的所述硬掩模层为氮化硅,在其他实施例中,所述硬掩模层也可以为氮化硅层构成的复合层,并且该复合层中氮化硅层位于氧化硅层之上。
步骤二、在所述硬掩模层上旋涂光刻胶并曝光显影,形成体硅区;本发明进一步地,本实施例的步骤二中的所述光刻胶包含减反射层。
步骤三、等离子各向异性刻蚀所述体硅区,打开部分所述埋氧层;之后进行各向同性刻蚀,所述绝缘体上硅在水平方向上形成内缩;如图1所示,图1显示为本发明中将半导体结构刻蚀打开部分埋氧层后的结构示意图。该半导体结构包括硅基底01;位于所述硅基底01上的埋氧层02;位于所述埋氧层02上的绝缘体上硅03;位于所述绝缘体上硅03的硬掩模层04。该步骤三采用等离子各向异性刻蚀所述体硅区,将所述埋氧层02打开,并保留一部分所述埋氧层,形成凹槽。之后进行各向同性刻蚀,形成的结构如图2所示,图2显示为本发明各向同性刻蚀后绝缘体上硅形成内缩的结构示意图。形成各向同性刻蚀后,所述绝缘体上硅03在水平方向上形成内缩。
步骤四、等离子各向异性刻蚀,将所述埋氧层刻穿,形成体硅区沟槽;如图3所示,图3显示为本发明中刻蚀形成体硅区沟槽的结构示意图。该步骤四进行等离子各向异性刻蚀形成体硅区沟槽A。
步骤五、去除光刻胶及刻蚀残余物;本发明进一步地,本实施例的步骤五中去除光刻胶及刻蚀残余物的方法包括湿法去除法或湿法去除和干法去除组合的方法。本实施例中去除光刻胶及残留物的方法为湿法去除法,在其他实施例中也可以利用湿法去除和干法去除组合的方法去除光刻胶和残留物。
步骤六、在所述体硅区沟槽中进行硅外延生长。如图4所示,图4显示为本发明中在所述体硅区沟槽中进行硅外延生长形成硅外延层的结构示意图。形成的硅外延层与所述基底01在图4中形成一个整体。图4中进行硅外延生长后的硅表面低于所述绝缘体上硅。
本发明进一步地,本实施例的步骤六中进行硅外延生长后的硅表面与所述绝缘体上硅的上表面齐平。如图5所示,图5显示为本发明中进行硅外延生长后的硅表面与绝缘体上硅上表面齐平的结构示意图。
综上所述,本案可以实现FDSOI工艺中无***且硬掩模缺失得到控制的硅外延层,从而降低工艺缺陷,扩大FDSOI工艺窗口,提高器件性能及产品良率。所以,本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效,而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下,对上述实施例进行修饰或改变。因此,举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变,仍应由本发明的权利要求所涵盖。
Claims (10)
1.一种FDSOI的制作方法,其特征在于,至少包括以下步骤:
步骤一、提供半导体结构,该半导体结构包括:硅基底;位于所述硅基底上的埋氧层;位于所述埋氧层上的绝缘体上硅;位于所述绝缘体上硅的硬掩模层;
步骤二、在所述硬掩模层上旋涂光刻胶并曝光显影,形成体硅区;
步骤三、等离子各向异性刻蚀所述体硅区,打开部分所述埋氧层;之后进行各向同性刻蚀,所述绝缘体上硅在水平方向上形成内缩;
步骤四、等离子各向异性刻蚀,将所述埋氧层刻穿,形成体硅区沟槽;
步骤五、去除光刻胶及刻蚀残余物;
步骤六、在所述体硅区沟槽中进行硅外延生长。
2.根据权利要求1所述的FDSOI的制作方法,其特征在于:步骤一中的所述硬掩模层为氮化硅或由氧化硅层和氮化硅层构成的复合层,该复合层中氮化硅层位于氧化硅层之上。
6.根据权利要求1所述的FDSOI的制作方法,其特征在于:步骤二中的所述光刻胶包含减反射层。
9.根据权利要求1所述的FDSOI的制作方法,其特征在于:步骤五中去除光刻胶及刻蚀残余物的方法包括湿法去除法或湿法去除和干法去除组合的方法。
10.根据权利要求1所述的FDSOI的制作方法,其特征在于:步骤六中进行硅外延生长后的硅表面与所述绝缘体上硅的上表面齐平。
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