CN115541955B - Oscilloscope capable of realizing analog triggering - Google Patents
Oscilloscope capable of realizing analog triggering Download PDFInfo
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- CN115541955B CN115541955B CN202211522766.7A CN202211522766A CN115541955B CN 115541955 B CN115541955 B CN 115541955B CN 202211522766 A CN202211522766 A CN 202211522766A CN 115541955 B CN115541955 B CN 115541955B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R13/00—Arrangements for displaying electric variables or waveforms
- G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
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- G01R13/0254—Circuits therefor for triggering, synchronisation
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
- G01R29/027—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values
- G01R29/0276—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values the pulse characteristic being rise time
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Abstract
The invention relates to an oscilloscope for realizing analog triggering, wherein a triggering module in the oscilloscope comprises a triggering pulse expansion circuit and a digital TDC circuit, the triggering pulse expansion circuit is used for converting an analog triggering signal into a triggering pulse signal, and because the pulse width of the triggering pulse signal comprises the time difference between the triggering edge of the analog triggering signal and the clock edge of the clock signal and the period of a fixed number of clock signals, the digital TDC circuit determines the time difference between the triggering edge of the analog triggering signal and the clock edge of the clock signal according to the pulse width of the triggering pulse signal and the number of clock signal periods of the oscilloscope contained in the pulse width of the triggering pulse signal, thereby, based on the time difference, a compensation module can adjust the triggering edge of the analog triggering signal so as to synchronize the triggering edge of the analog triggering signal and the clock edge of the clock signal, and the problem of waveform jitter sampled during analog triggering is solved.
Description
Technical Field
The invention relates to the technical field of digital oscilloscopes, in particular to an oscilloscope for realizing analog triggering.
Background
At present, in order to be compatible with the prior analog oscilloscope and the channel expansion, the digital oscilloscope also reserves an analog trigger channel, namely an external trigger channel; since digital oscilloscopes belong to discrete systems, while analog triggers belong to continuous signal triggers, there is an uncertainty in the time difference from the trigger edge of the analog trigger signal to the clock edge of the digital clock signal from frame to frame, resulting in jitter in the waveform sampled by the analog trigger. Therefore, to stabilize the waveform sampled by the analog trigger, the time difference needs to be measured to compensate for waveform jitter problems caused by the misalignment of the trigger edge and the clock edge.
Disclosure of Invention
The invention mainly solves the technical problem of how to determine the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal under the analog trigger.
In one embodiment, an oscilloscope for implementing analog triggering is provided, comprising:
the data acquisition module is used for acquiring data of the signals input by the signal channel;
the analog trigger channel is used for acquiring a trigger input signal and comparing the trigger input signal with a preset trigger level to obtain an analog trigger signal;
the trigger module comprises a trigger pulse expansion circuit and a digital TDC circuit;
the trigger pulse expansion circuit is used for carrying out delay adjustment on the trigger edge of the analog trigger signal after starting to carry out data acquisition on the signal input by the signal channel, so as to obtain a third trigger synchronous signal, wherein the trigger edge of the third trigger synchronous signal is synchronous with the clock edge of the clock signal of the oscilloscope; the trigger pulse expansion circuit is further used for generating a trigger pulse signal according to the trigger edge of the analog trigger synchronous signal and the trigger edge of the third trigger synchronous signal, wherein the rising edge of the trigger pulse signal is the trigger edge of the analog trigger synchronous signal, and the falling edge of the trigger pulse signal is the trigger edge of the third trigger synchronous signal;
the digital TDC circuit is used for acquiring the pulse width of the trigger pulse signal and the number of clock signal periods of the oscilloscope contained in the pulse width of the trigger pulse signal, and determining the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal based on the pulse width of the trigger pulse signal and the number of clock signal periods of the oscilloscope contained in the pulse width of the trigger pulse signal;
and the compensation module is used for adjusting the triggering edge of the analog triggering signal based on the time difference between the triggering edge of the analog triggering signal and the clock edge of the clock signal so as to synchronize the triggering edge of the analog triggering signal with the clock edge of the clock signal.
According to the oscilloscope for realizing analog triggering of the embodiment, the triggering module in the oscilloscope comprises the triggering pulse expansion circuit and the digital TDC circuit, the triggering pulse expansion circuit is used for converting an analog triggering signal into a triggering pulse signal, and because the pulse width of the triggering pulse signal comprises the time difference between the triggering edge of the analog triggering signal and the clock edge of the clock signal and the period of the clock signal with a fixed number, the digital TDC circuit determines the time difference between the triggering edge of the analog triggering signal and the clock edge of the clock signal according to the pulse width of the triggering pulse signal and the number of the clock signal periods of the oscilloscope contained in the pulse width of the triggering pulse signal, and therefore, based on the time difference, the compensation module can adjust the triggering edge of the analog triggering signal so as to enable the triggering edge of the analog triggering signal to be synchronous with the clock edge of the clock signal, and the problem of waveform jitter sampled during analog triggering is solved.
Drawings
FIG. 1 is a schematic diagram of measuring the time difference from a trigger edge of an analog trigger signal to a clock edge of a clock signal by an analog TDC technique;
FIG. 2 is a schematic diagram of measuring the time difference from a trigger edge of an analog trigger signal to a clock edge of a clock signal by a high-speed clock multi-phase sampling technique;
FIG. 3 is a schematic diagram of a trigger module of an oscilloscope according to an embodiment;
fig. 4 is a schematic diagram of a clock signal, an analog trigger signal w, a first trigger synchronization signal w1, a second trigger synchronization signal w2, a third trigger synchronization signal w3, and a trigger pulse signal p;
FIG. 5 is a schematic diagram of a digital TDC circuit according to one embodiment;
FIG. 6 is a schematic diagram of the metastable state existence principle;
FIG. 7 is a schematic diagram of another embodiment of a digital TDC circuit;
FIG. 8 is a decoding timing diagram;
FIG. 9 is a schematic diagram of a clock signal, signals of respective delay taps, and valid1 signal;
FIG. 10 is a schematic diagram of a clock signal, signals of respective delay taps, and valid2 signal;
fig. 11 is a schematic waveform diagram of an oscilloscope under an analog trigger.
Detailed Description
The invention will be described in further detail below with reference to the drawings by means of specific embodiments. Wherein like elements in different embodiments are numbered alike in association. In the following embodiments, numerous specific details are set forth in order to provide a better understanding of the present application. However, one skilled in the art will readily recognize that some of the features may be omitted, or replaced by other elements, materials, or methods in different situations. In some instances, some operations associated with the present application have not been shown or described in the specification to avoid obscuring the core portions of the present application, and may not be necessary for a person skilled in the art to describe in detail the relevant operations based on the description herein and the general knowledge of one skilled in the art.
Furthermore, the described features, operations, or characteristics of the description may be combined in any suitable manner in various embodiments. Also, various steps or acts in the method descriptions may be interchanged or modified in a manner apparent to those of ordinary skill in the art. Thus, the various orders in the description and drawings are for clarity of description of only certain embodiments, and are not meant to be required orders unless otherwise indicated.
The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning. The terms "coupled" and "connected," as used herein, are intended to encompass both direct and indirect coupling (coupling), unless otherwise indicated.
Referring to fig. 1, fig. 1 shows an example of measuring a time difference from a trigger edge of an analog trigger signal to a clock edge of a clock signal by using an analog TDC technique, and a programmable logic device (FPGA) in an oscilloscope sends a pulse 1clk with a clock width to an analog TDC circuit to widen, so as to obtain T1; then, sending the pulse 2clk with two clock widths to an analog TDC circuit for stretching to obtain T2; assuming that the analog TDC circuit is linear and the stretching coefficient is a, one clock signal is divided into a parts, each part having a width t= (T2-T1)/a. As shown in fig. 1, the time difference from the trigger edge of the analog trigger signal to the clock edge of the clock signal is Δt, and the pulse signal composed of the analog trigger signal and the analog trigger synchronization signal is sent to the analog TDC circuit for stretching to obtain Δt, and the distance from the analog trigger signal to the clock edge can be calculated according to T. However, this approach requires additional hardware analog circuitry to support, and components in the analog circuitry are susceptible to temperature, affecting the final output result.
Referring to fig. 2, fig. 2 shows an example of measuring a time difference from a trigger edge of an analog trigger signal to a clock edge of a clock signal by a high-speed clock multi-phase sampling technique, if clock 1 is an FPGA master clock, the analog trigger signal may be sampled by a higher-speed clock 2, and if clock 1 and clock 2 have a certain relationship, and if 1:2 are assumed, then the sampling result of clock 2 can distinguish whether the analog trigger signal is in the first half period or the second half period of clock 1, which may increase the sampling frequency and sample the analog trigger signal by using multiple phases, and analyze the distance from the trigger edge of the analog trigger signal to the clock edge according to the obtained result. However, since the sampling frequency of 1G has a resolution of 1ns, assuming a 20ps resolution is required, the sampling clock requires a 50G speed, which cannot be supported by FPGAs.
Based on the above problems, the embodiment of the invention converts the analog trigger signal into the trigger pulse signal, determines the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal based on the pulse width of the trigger pulse signal and the number of the periods of the clock signal contained in the trigger pulse signal, realizes the analog trigger function through the digital circuit, and integrates the digital circuit into the FPGA chip of the oscilloscope without needing additional hardware analog circuits.
The embodiment of the invention provides an oscilloscope for realizing analog triggering, which is hereinafter referred to as an oscilloscope, and comprises: the system comprises a data acquisition module, an analog trigger channel, a trigger module and a compensation module, wherein the data acquisition module is used for acquiring data of signals input by the signal channel; the analog trigger channel is used for acquiring a trigger input signal, and comparing the trigger input signal with a preset trigger level to obtain an analog trigger signal; the trigger module is used for determining the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal; the compensation module is used for adjusting the trigger edge of the analog trigger signal based on the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal so as to synchronize the trigger edge of the analog trigger signal with the clock edge of the clock signal.
Referring to fig. 3, fig. 3 is a schematic diagram of a trigger module according to an embodiment, where the trigger module includes a T-trigger 101, a first one-out-of-two switch 102, a trigger pulse extension circuit 103, a second one-out-of-two switch 104, and a digital TDC circuit 105, which are described in detail below.
The T flip-flop 101 is configured to clear an output when data acquisition starts on a signal input to the signal channel, and to receive and output an analog trigger signal after the pre-trigger depth is full. The D pin of the T trigger 101 is connected with a power supply VCC, the C pin (input pin) of the T trigger 101 is used for receiving an analog trigger signal, the CE pin of the T trigger 101 is used for acquiring a pre-trigger signal, the RS pin of the T trigger 101 is used for acquiring an acquisition start signal, and the acquisition start signal is used for representing a data acquisition module of an oscilloscope to start data acquisition.
In this embodiment, the analog trigger signal is output through an analog comparator, where the analog comparator includes a normal phase input end and an inverted phase input end, the normal phase input end is used to obtain an externally input trigger input signal, the inverted phase input end is used to obtain a preset trigger level, and the analog comparator is used to compare the trigger input signal with the preset trigger level and output the analog trigger signal.
The first two-in-one switch 102 includes a first end, a second end and a third end, the first end of the first two-in-one switch 102 is used for obtaining an analog trigger signal output by the T trigger, the second end of the first two-in-one switch 102 is used for obtaining a digital trigger signal, the third end of the first two-in-one switch 102 is connected with an input end of the trigger pulse expanding circuit, and the third end is used for outputting an analog trigger signal or a digital trigger signal under the trigger of the trigger selection signal, i.e. the first two-in-one switch 102 is used for switching the trigger mode of analog trigger and digital trigger.
The trigger pulse expansion circuit 103 is configured to delay and adjust a trigger edge of the analog trigger signal after starting data acquisition on a signal input by the signal channel, so as to obtain a third trigger synchronization signal; wherein the trigger edge of the third trigger synchronization signal is synchronized with the clock edge of the clock signal of the oscilloscope. Note that, the clock signal of the oscilloscope refers to a local clock signal for sampling by the oscilloscope, which is generated by the FPGA.
In addition, the trigger pulse expanding circuit 103 is further configured to generate a trigger pulse signal according to the trigger edge of the analog trigger synchronization signal and the trigger edge of the third trigger synchronization signal, where the rising edge of the trigger pulse signal is the trigger edge of the analog trigger synchronization signal, and the falling edge of the trigger pulse signal is the trigger edge of the third trigger synchronization signal.
The second alternative switch 104 comprises a first end, a second end and a third end, the first end of the second alternative switch 104 is used for acquiring a trigger pulse signal, the second end of the second alternative switch 104 is used for acquiring a calibration sequence signal, the third end of the second alternative switch 104 is connected with the input end of the digital TDC circuit, and the third end is used for correcting the trigger pulse signal under the triggering of the correction selection signal.
The digital TDC circuit 105 is configured to acquire a pulse width of the trigger pulse signal and the number of clock signal cycles of the oscilloscope included in the pulse width of the trigger pulse signal, and determine a time difference between a trigger edge of the analog trigger signal and a clock edge of the clock signal based on the pulse width of the trigger pulse signal and the number of clock signal cycles of the oscilloscope included in the pulse width of the trigger pulse signal.
The trigger module provided by the embodiment of the invention can be directly integrated in the FPGA of the oscilloscope, an external analog circuit is not needed to measure the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal, the measurement accuracy is higher, and the influence of environmental factors such as temperature and the like is avoided.
The trigger pulse extension circuit 103 and the digital TDC circuit 105 are described in detail below.
In an embodiment, the delay adjustment of the trigger edge of the analog trigger signal by the trigger pulse extension circuit 103, to obtain a third trigger synchronization signal includes: acquiring the period of a clock signal of a trigger edge of an analog trigger signal, and taking a clock signal corresponding to the acquired period of the clock signal as a synchronous clock signal; generating a first trigger synchronizing signal based on a synchronizing clock signal, wherein a trigger edge of the first trigger synchronizing signal is synchronous with a clock edge of the synchronizing clock signal; generating a second trigger synchronous signal based on the first trigger synchronous signal, wherein the trigger edge of the second trigger synchronous signal is delayed by one period of a clock signal relative to the trigger edge of the first trigger synchronous signal; based on the second trigger synchronization signal, a third trigger synchronization signal is generated, the trigger edge of which is delayed by one period of the clock signal with respect to the trigger edge of the second trigger synchronization signal.
Referring to fig. 4, fig. 4 is a timing diagram of the clock signal, the analog trigger signal w, the first trigger synchronization signal w1, the second trigger synchronization signal w2, the third trigger synchronization signal w3, and the trigger pulse signal p. Because the analog trigger signal and the clock signal of the oscilloscope are asynchronous, the embodiment firstly carries out asynchronous signal synchronization on the analog trigger signal w, and sequentially generates a first trigger synchronization signal w1, a second trigger synchronization signal w2 and a third trigger synchronization signal w3 so that the obtained third trigger synchronization signal w3 is synchronous with the clock edge of the clock signal, then takes the trigger edge of the analog trigger signal w as a rising edge, takes the trigger edge of the third trigger synchronization signal w3 as a falling edge, and forms a trigger pulse signal p, wherein the expression p= | w3& w of the trigger pulse signal p represents logical AND, |! Representing a logical negation.
It should be noted that, for the clock signal, there is a hold time window on the clock edge of the clock signal, and if the trigger edge of the analog trigger signal falls within the hold time window on the clock edge, it can be considered to be synchronous with the clock edge of the clock signal, where the hold time window on the clock edge is a preset time range centered on the clock edge. In fig. 4, the trigger edge of the third trigger synchronization signal is not perfectly aligned with the clock edge of the clock signal, and the time difference between the trigger edge and the clock edge is T4, but considering the hold time window of the clock edge, the trigger edge of the third trigger synchronization signal is considered to be synchronized with the clock edge of the clock signal, and similarly, T3 is the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal, considering the hold window time, and thus, T3 is not the complete time difference between the trigger edge and the clock edge. In addition, the T time interval in fig. 4 represents an interval in which an analog trigger signal may occur.
In summary, synchronizing the trigger edge of the third trigger synchronization signal with the clock edge of the clock signal of the oscilloscope comprises: the trigger edge of the third trigger synchronous signal is in a holding time window of the clock edge of the clock signal of the oscilloscope; the step of synchronizing the trigger edge of the first trigger synchronous signal with the clock edge of the synchronous clock signal comprises the following steps: the trigger edge of the first trigger synchronization signal is within a hold time window of the clock edge of the synchronization clock signal.
It should be noted that, the trigger pulse extension circuit 103 provided in this embodiment may be implemented by a digital circuit, for example, may be implemented by three D flip-flops, where the first trigger synchronization signal is a signal output through one D flip-flop, the second trigger synchronization signal is a signal output through two D flip-flops, and the third trigger synchronization signal is a signal output through three D flip-flops.
In one embodiment, referring to FIG. 5, the digital TDC circuit 105 includes a delay chain 1051, a plurality of D flip-flops 1052, and a first thermometer code decoder 1053, as described in detail below.
The input terminal of the delay chain 1051 is connected to the third terminal of the second alternative switch 104, and is configured to receive the signal output from the third terminal of the second alternative switch 104.
the delay tap 1 is used for performing delay operation of delay time t on the signal received by the delay chain 1051;
delay tap 2 is used to delay the signal received by delay chain 1051 by a delay time of 2 t;
…
delay tap n is used to delay the signal received by delay chain 1051 by a delay time nt.
Each D flip-flop 1052 is configured to receive the signal output by the corresponding delay tap, and output an effective level signal when the signal received by the delay chain 1051 is a trigger pulse signal; otherwise, an invalid level signal is output. That is, when the delay chain 1051 does not receive the trigger pulse signal, all D flip-flops output the inactive level signal, after the delay chain 1051 receives the trigger pulse signal, since the pulse width of the trigger pulse signal is limited, some D flip-flops 1052 output the active level signal, and the width of the trigger pulse signal can be obtained according to the number of D flip-flops corresponding to the output active level signals and the delay time of the corresponding connected delay taps, and in another embodiment, if the number of D flip-flops 1052 matches the pulse width of the trigger pulse signal, it is also possible that all D flip-flops 1052 output the active level signal.
The first thermometer code decoder is used for receiving the level signals output by the D triggers and outputting a corresponding first decoding value sequence, wherein the first decoding value sequence comprises a plurality of first decoding values, and each first decoding value corresponds to the level signal output by the D trigger one by one; the first thermometer code decoder determines the pulse width of the trigger pulse signal according to the number of valid decoding values in the first decoding value sequence.
In one embodiment, the number of clock signal cycles of the oscilloscope contained in the pulse width of the trigger pulse signal is 2; then, determining a time difference between a trigger edge of the analog trigger signal and a clock edge of the clock signal based on the pulse width of the trigger pulse signal and the number of clock signal cycles of the oscilloscope contained in the pulse width of the trigger pulse signal includes: subtracting two clock signal periods from the pulse width of the trigger pulse signal to obtain the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal.
Referring to fig. 6, when the analog trigger signal falls within the hold time window of the clock edge due to the metastable state, the analog trigger signal may be synchronized by the current clock edge to be the synchronization signal 1 or by the next clock edge to be the synchronization signal 2, that is, the trigger pulse expanding circuit 103 may have two clock signal periods or three clock signal periods between the obtained third trigger synchronization signal and the analog trigger signal when performing delay adjustment on the trigger edge of the analog trigger signal. If the number of clock cycles of the oscilloscope included in the pulse width of the trigger pulse signal is taken as 2, the waveform displayed by the oscilloscope may have jitter of one clock cycle, and in order to avoid the metastable state, the digital TDC circuit shown in fig. 5 is improved, please refer to fig. 7, where the digital TDC circuit further includes: a second thermometer code decoder 1054, and gate logic 1055, and a counter 1056.
The first thermometer code decoder 1053 is also configured to receive signals output by respective delay taps of the delay chain and output a first decoded value when first data other than 0 is detected. The second thermometer code decoder 1054 is configured to receive the inverse of the signal output by each delay tap of the delay chain and output a second decoded value when the first data other than 0 is detected. Referring to fig. 8, fig. 8 shows a decoding sequence, wherein valid1 is a first decoding value, valid2 is a second decoding value, data1 is an original code signal output by a delay chain, and data2 is an inverse code signal of the original code signal.
The and logic circuit 1055 is configured to obtain the inverse code values of the first decoding value and the second decoding value, and perform a subtraction operation on the first decoding value and the second decoding value to obtain a first signal.
The counter 1056 is configured to receive the first signal and count the first signal to obtain a count value, where the count value is the number of clock signal cycles of the oscilloscope included in the pulse width of the trigger pulse signal.
In this embodiment, if the first signal is k, the number k= | valid2& valid1, the signal k is counted, and the count value is s, then: tedge1= (s-2) Tclk+T3-T4, wherein Tedge1 is the trigger edge and of the analog trigger signal after eliminating metastable state; a time difference between clock edges of the clock signal; if the third trigger synchronization signal w3 is completely aligned with the clock edge, that is, t4=0, the final time difference Tfinal after eliminating the metastable state is: tfinal= (s-2) ×tclk+t3.
Referring to fig. 9, if a trigger pulse signal is input to the delay chain, D (0), D (1) … … D (n-1) represents signals of respective delay taps, each clock signal samples signals on the delay chain, and after a first value other than 0 is detected on the taps, valid1 is pulled high, and the value is output, and detection is not continued later.
Referring to fig. 10, if the trigger pulse signal is input to the delay chain, D (0) ', D (1) ' … … D (n-1) ' represents the inverse code signal of each delay tap, each clock signal samples the signal on the delay chain, and after the first value other than 0 is detected on the tap, the valid2 signal is pulled high, and the value is output, and the detection is not continued later.
As can be seen from a comparison of fig. 9 and 10, the code reversal detection timing is to detect by converting the falling edge of the trigger pulse signal p into the rising edge. The metastable state of the analog trigger signal w exists, the third trigger synchronous signal w3 is a steady state signal, the logic relationship is available, and 2 complete clock signal periods exist between the rising edge and the falling edge of the trigger pulse signal p, so that the time difference from the analog trigger signal to the clock edge can be calculated.
The invention widens the trigger edge of the analog trigger signal into the trigger pulse signal, and then carries out AND gate logic calculation, so that the principle of converting calculation to eliminate metastable state is to avoid detecting which delay tap position of the trigger edge in a delay chain, but to detect the relative position, and the relative position of the trigger edge is not changed when metastable state occurs, but is divided into different clock periods, and thus the delay value with metastable state can be combined to the next clock calculation by detecting the relative position.
Referring to fig. 11, fig. 11 is a schematic waveform diagram of an oscilloscope under analog triggering, a test signal with a fixed phase difference between 20000 times and a clock signal is sent, a sample standard deviation σ=0.9lsb=16.6ps is calculated, LSB represents that the resolution of actual measurement is 18.5ps, and as can be seen from fig. 11, the jitter peak-to-peak value of the waveform is about 300ps, which is greatly improved compared with the jitter performance of the prior art.
The foregoing description of the invention has been presented for purposes of illustration and description, and is not intended to be limiting. Several simple deductions, modifications or substitutions may also be made by a person skilled in the art to which the invention pertains, based on the idea of the invention.
Claims (8)
1. An oscilloscope for implementing analog triggering, comprising:
the data acquisition module is used for acquiring data of the signals input by the signal channel;
the analog trigger channel is used for acquiring a trigger input signal and comparing the trigger input signal with a preset trigger level to obtain an analog trigger signal;
the trigger module comprises a trigger pulse expansion circuit and a digital TDC circuit;
the trigger pulse expansion circuit is used for carrying out delay adjustment on the trigger edge of the analog trigger signal after starting to carry out data acquisition on the signal input by the signal channel, so as to obtain a third trigger synchronous signal, wherein the trigger edge of the third trigger synchronous signal is synchronous with the clock edge of the clock signal of the oscilloscope; the trigger pulse expansion circuit is further configured to generate a trigger pulse signal according to a trigger edge of the analog trigger signal and a trigger edge of the third trigger synchronous signal, wherein a rising edge of the trigger pulse signal is a trigger edge of the analog trigger signal, and a falling edge of the trigger pulse signal is a trigger edge of the third trigger synchronous signal;
the digital TDC circuit is used for acquiring the pulse width of the trigger pulse signal and the number of clock signal periods of the oscilloscope contained in the pulse width of the trigger pulse signal, and determining the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal based on the pulse width of the trigger pulse signal and the number of clock signal periods of the oscilloscope contained in the pulse width of the trigger pulse signal;
the compensation module is used for adjusting the trigger edge of the analog trigger signal based on the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal so as to synchronize the trigger edge of the analog trigger signal with the clock edge of the clock signal;
the digital TDC circuit includes: a delay chain, a plurality of D flip-flops, and a first thermometer code decoder;
the delay chain comprises a plurality of delay taps, the delay taps are in one-to-one correspondence with the D triggers, and each delay tap is connected with an input pin of the corresponding D trigger; each delay tap is used for carrying out delay operation of different delay time on signals received by the delay chain, wherein:
the delay tap 1 is used for carrying out delay operation of delay time t on signals received by the delay chain;
the delay tap 2 is used for carrying out delay operation of delay time 2t on the signal received by the delay chain;
…
the delay tap n is used for carrying out delay operation of delay time nt on the signal received by the delay chain;
each D trigger is used for receiving the corresponding signal output by the delay tap and outputting an effective level signal when the received signal is the trigger pulse signal; otherwise, outputting an invalid level signal;
the first thermometer code decoder is used for receiving the level signals output by the D triggers and outputting a corresponding first decoding value sequence, wherein the first decoding value sequence comprises a plurality of first decoding values, and each first decoding value corresponds to the level signal output by the D trigger one by one; the first thermometer code decoder determines the pulse width of the trigger pulse signal according to the number of effective decoding values in the first decoding value sequence;
the digital TDC circuit further includes: the second thermometer code decoder, the AND gate logic circuit and the counter;
the first thermometer code decoder is also used for receiving signals output by each delay tap of the delay chain and outputting a first decoding value when detecting a first signal which is not 0;
the second thermometer code decoder is used for receiving the inverse code signals of the signals output by the delay taps of the delay chain and outputting a second decoding value when the first data which is not 0 is detected;
the AND gate logic circuit is used for acquiring the inverse code values of the first decoding value and the second decoding value, and subtracting the first decoding value and the second decoding value to obtain a first signal;
the counter is used for receiving the first signal and counting the first signal to obtain a count value, and the count value is the number of clock signal cycles of the oscilloscope contained in the pulse width of the trigger pulse signal.
2. The oscilloscope of claim 1 wherein said delay adjusting the trigger edge of said analog trigger signal to obtain a third trigger synchronization signal comprises:
acquiring the period of the clock signal of the trigger edge of the analog trigger signal, and taking the clock signal corresponding to the period of the acquired clock signal as a synchronous clock signal;
generating a first trigger synchronous signal based on the synchronous clock signal, wherein the trigger edge of the first trigger synchronous signal is synchronous with the clock edge of the synchronous clock signal;
generating a second trigger synchronous signal based on the first trigger synchronous signal, wherein the trigger edge of the second trigger synchronous signal is delayed by one period of a clock signal relative to the trigger edge of the first trigger synchronous signal;
and generating a third trigger synchronous signal based on the second trigger synchronous signal, wherein the trigger edge of the third trigger synchronous signal is delayed by one period of a clock signal relative to the trigger edge of the second trigger synchronous signal.
3. The oscilloscope of claim 2, wherein the synchronizing of the trigger edge of the third trigger synchronization signal with the clock edge of the clock signal of the oscilloscope comprises:
the trigger edge of the third trigger synchronous signal is in a holding time window of the clock edge of the clock signal of the oscilloscope; the clock edge holding time window is a preset time range taking the clock edge as a center;
the synchronization of the triggering edge of the first triggering synchronous signal and the clock edge of the synchronous clock signal comprises:
the trigger edge of the first trigger synchronization signal is within a hold time window of a clock edge of the synchronization clock signal.
4. The oscilloscope of claim 1 wherein the number of clock signal cycles of said oscilloscope contained in the pulse width of said trigger pulse signal is 2;
the determining the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal based on the pulse width of the trigger pulse signal and the number of clock signal cycles of the oscilloscope included in the pulse width of the trigger pulse signal includes:
subtracting two clock signal periods from the pulse width of the trigger pulse signal to obtain the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal.
5. The oscilloscope of claim 1, wherein the determining the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal based on the pulse width of the trigger pulse signal and the number of clock signal cycles of the oscilloscope contained in the pulse width of the trigger pulse signal comprises:
and subtracting the counted value from the pulse width of the trigger pulse signal to obtain the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal.
6. The oscilloscope of claim 1, wherein the trigger module further comprises: the device comprises a T trigger, a first one-out-of-two switch and a second one-out-of-two switch;
the T trigger is used for resetting the output when the signal input by the signal channel starts to be subjected to data acquisition, and receiving and outputting the analog trigger signal after the pre-trigger depth is full;
the first two-out switch comprises a first end, a second end and a third end, wherein the first end is used for acquiring the analog trigger signal output by the T trigger, the second end is used for acquiring a digital trigger signal, the third end is connected with the input end of the trigger pulse expansion circuit, and the third end is used for outputting the analog trigger signal or the digital trigger signal under the triggering of the trigger selection signal;
the second alternative switch comprises a first end, a second end and a third end, wherein the first end is used for acquiring the trigger pulse signal, the second end is used for acquiring a calibration sequence signal, the third end is connected with the input end of the digital TDC circuit, and the third end is used for correcting the trigger pulse signal under the triggering of the correction selection signal.
7. The oscilloscope of claim 1, wherein the analog trigger channel comprises:
the analog comparator comprises a normal phase input end and an opposite phase input end, wherein the normal phase input end is used for acquiring the trigger input signal, the opposite phase input end is used for acquiring a preset trigger level, and the analog comparator is used for comparing the trigger input signal with the preset trigger level and outputting the analog trigger signal.
8. The oscilloscope of claim 1, comprising:
and the trigger module is integrated in the programmable logic device.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211522766.7A CN115541955B (en) | 2022-12-01 | 2022-12-01 | Oscilloscope capable of realizing analog triggering |
| PCT/CN2023/089487 WO2024113650A1 (en) | 2022-12-01 | 2023-04-20 | Oscilloscope for realizing analog trigger |
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| CN202211522766.7A CN115541955B (en) | 2022-12-01 | 2022-12-01 | Oscilloscope capable of realizing analog triggering |
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| KR100982103B1 (en) * | 2006-02-17 | 2010-09-13 | 베리지 (싱가포르) 피티이. 엘티디. | Time-to-digital conversion with delay contribution determination of delay elements |
| US7564284B2 (en) * | 2007-03-26 | 2009-07-21 | Infineon Technologies Ag | Time delay circuit and time to digital converter |
| JP2010028600A (en) * | 2008-07-23 | 2010-02-04 | Sony Corp | Tdc circuit, pll circuit, and wireless communication apparatus |
| CN103018512B (en) * | 2011-09-23 | 2016-09-07 | 北京普源精电科技有限公司 | A kind of oscillograph with external trigger function |
| CN102435809B (en) * | 2011-10-12 | 2013-12-04 | 秦轲 | Multi-channel digital oscilloscope and signal synchronization method thereof |
| CN102830610B (en) * | 2012-09-17 | 2015-01-07 | 中国电子科技集团公司第四十一研究所 | Chronometer time automatic measurement circuit based on TDC-GP 21 and method |
| CN103092098B (en) * | 2012-12-28 | 2015-10-14 | 沈阳东软医疗***有限公司 | A kind of method and apparatus of hyperchannel sequential control |
| CN104702249B (en) * | 2013-12-10 | 2019-08-02 | 苏州普源精电科技有限公司 | A kind of signal generator with synchronizing function of bursting |
| US9294237B2 (en) * | 2014-07-30 | 2016-03-22 | Tektronix, Inc. | Method for performing joint jitter and amplitude noise analysis on a real time oscilloscope |
| CN108267628A (en) * | 2016-12-30 | 2018-07-10 | 北京普源精电科技有限公司 | Mixed signal oscillograph with equivalent sampling function |
| CN206489205U (en) * | 2017-02-16 | 2017-09-12 | 深圳市鼎阳科技有限公司 | Reduce system, digit chip and the oscillograph of oscillograph external trigger waveform shake |
| CN108982940A (en) * | 2018-06-13 | 2018-12-11 | 深圳市鼎阳科技有限公司 | A kind of external trigger device and external trigger method, oscillograph based on serial receiver |
| CN110445493A (en) * | 2019-06-27 | 2019-11-12 | 中国科学技术大学 | A kind of data collection synchronous device and method based on FPGA TDC |
| CN110749763A (en) * | 2019-12-24 | 2020-02-04 | 深圳市鼎阳科技股份有限公司 | Triggering method based on I2S signal and oscilloscope |
| CN113315521B (en) * | 2021-05-07 | 2022-12-23 | 清华大学 | Digital time converter and electronic device |
| CN115541955B (en) * | 2022-12-01 | 2023-04-28 | 深圳市鼎阳科技股份有限公司 | Oscilloscope capable of realizing analog triggering |
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