CN115499012A - Analog-to-digital converter and operation method thereof - Google Patents

Analog-to-digital converter and operation method thereof Download PDF

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CN115499012A
CN115499012A CN202110676094.4A CN202110676094A CN115499012A CN 115499012 A CN115499012 A CN 115499012A CN 202110676094 A CN202110676094 A CN 202110676094A CN 115499012 A CN115499012 A CN 115499012A
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China
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capacitance
array
capacitor
voltage
reference voltage
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林楷越
王维骏
黄诗雄
刘凯尹
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Realtek Semiconductor Corp
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Realtek Semiconductor Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors

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  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

An operation method of an analog-digital converter comprises the steps that in a first conversion period, a comparator generates a first comparison result, a first selection circuit switches and outputs voltage of a first capacitor of a group of large capacitors of a first capacitor array, a second selection circuit switches and outputs voltage of a second capacitor of the group of large capacitors of a second capacitor array, and in a second conversion period after the first conversion period, the comparator generates a second comparison result, the first selection circuit switches back and outputs voltage of a first capacitor part of the first capacitor of the group of large capacitors of the first capacitor array, and the second selection circuit switches back and outputs voltage of a first capacitor part of the second capacitor of the group of large capacitors of the second capacitor array. The first comparison result and the second comparison result are different.

Description

Analog-to-digital converter and operation method thereof
Technical Field
The present invention relates to electronic circuits, and more particularly, to an analog-to-digital converter and a method of operating the same.
Background
Analog-to-digital converters (ADCs) are devices for converting continuous signals in an analog form into discrete signals in a digital form, and are widely used in audio systems, video systems, communication systems, and various digital signal processing systems. A Successive Approximation Register (SAR) analog-to-digital converter is an analog-to-digital converter, which uses a capacitor array for analog-to-digital conversion, has a low power consumption characteristic, and is suitable for mobile devices or portable devices. However, due to the mismatch of the capacitors in the capacitor array adopted by the SAR ADC, a non-linear error of the SAR ADC may be caused, and the accuracy of the SAR ADC may be reduced.
Disclosure of Invention
Embodiments of the present invention provide a method of operating an analog-to-digital converter. The analog-to-digital converter comprises a first capacitor array, a first selection circuit, a second capacitor array, a second selection circuit, a comparator and a control logic circuit. Each group of capacitors in the first capacitor array includes a first capacitor and a second capacitor having substantially equal capacitance values. The capacitance value of the first capacitance portion of the first capacitance of the larger set of capacitances of the first capacitance array is substantially equal to the capacitance value of the first capacitance of the smaller set of capacitances of the first capacitance array. The capacitance of the first capacitance portion of the second capacitance of the set of larger capacitances of the first capacitance array is substantially equal to the capacitance of the first capacitance of the set of smaller capacitances of the first capacitance array. Each group of capacitors in the second capacitor array includes a first capacitor and a second capacitor having substantially equal capacitance values. The capacitance value of the first capacitance part of the first capacitance of the larger capacitance group of the second capacitance array is substantially equal to the capacitance value of the first capacitance of the smaller capacitance group of the second capacitance array. The capacitance value of the first capacitance portion of the second capacitance of the set of larger capacitances of the second capacitance array is substantially equal to the capacitance value of the first capacitance of the set of smaller capacitances of the second capacitance array. The first selection circuit is coupled to the first capacitor array, the second selection circuit is coupled to the second capacitor array, the comparator comprises a first input end coupled to the first capacitor array and a second input end coupled to the second capacitor array, and the control logic circuit is coupled to the first selection circuit, the second selection circuit and the comparator. The operating method includes during a first sampling period, a first selection circuit outputting a first reference voltage to a first capacitance of each group of capacitors in the first capacitor array and a second reference voltage to a second capacitance of each group of capacitors in the first capacitor array, a second selection circuit outputting the first reference voltage to the first capacitance of each group of capacitors in the second capacitor array and the second reference voltage to the second capacitance of each group of capacitors in the second capacitor array; during a first conversion period, the comparator compares the voltage of the first input end with the voltage of the second input end to generate a first comparison result, the first selection circuit outputs a second reference voltage to a first capacitor of the group of larger capacitors of the first capacitor array, and the second selection circuit outputs the first reference voltage to a second capacitor of the group of larger capacitors of the second capacitor array; and during a second transition period after the first transition period, the comparator compares the voltage of the first input terminal with the voltage of the second input terminal to generate a second comparison result, the first selection circuit outputs the first reference voltage to the first capacitance portion of the set of larger capacitances of the first capacitance array or the second capacitance portion of the set of larger capacitances of the first capacitance array, and the second selection circuit outputs the second reference voltage to the first capacitance portion of the set of larger capacitances of the second capacitance array or the first capacitance portion of the set of larger capacitances of the second capacitance array. The first comparison result and the second comparison result are different.
Drawings
Fig. 1 is a circuit diagram of an analog-to-digital converter according to an embodiment of the invention.
Fig. 2 is a flow chart of a method of operation of the analog to digital converter of fig. 1.
Detailed Description
Fig. 1 is a circuit diagram of an analog-to-digital converter 1 according to an embodiment of the present invention. The adc 1 is a 3-bit split capacitor (split capacitor) Successive Approximation Register (SAR) adc, and can convert the differential input voltage Vip, vin into digital output data Dout according to a successive approximation method (such as a binary search method). The differential input voltages Vip, vin may be provided by a first signal source and a second signal source, respectively. The digital output data Dout may comprise 3 bits. The analog-to-digital converter 1 may generate a set of digital output data Dout in each operation cycle. Each operation cycle may include a sampling phase (or referred to as an acquisition phase) and a quantization phase (or referred to as a conversion phase), in which the adc 1 may sample the differential input voltages Vip and Vin to generate a pair of sampling signals, and quantize the pair of sampling signals to generate the digital output data Dout in the quantization phase. The quantization stage may include a plurality (3) of transitions for sequentially generating a plurality (3) bits of the digital output data Dout. In multiple sampling stages, the adc 1 can be reset according to 2 voltage settings, thereby reducing the voltage error due to the mismatch of the capacitive elements, reducing the integral non-linearity (INL) error and the differential non-linearity (DNL) error thereof, and providing high speed analog-to-digital conversion.
The adc 1 may include switches SW1 and SW2, a first capacitor array 141, a first selection circuit 121, a second capacitor array 142, a second selection circuit 122, a comparator 16, and a control logic circuit 18. The first selection circuit 121 and the switch SW1 are coupled to the first capacitor array 141, and the second selection circuit 122 and the switch SW2 are coupled to the second capacitor array 142. The comparator 16 may include a first receiving terminal coupled to the first capacitor array 141, a second receiving terminal coupled to the second capacitor array 142, and an output terminal coupled to the control logic circuit 18. The control logic 18 is coupled to the first selection circuit 121 and the second selection circuit 122.
The first capacitor array 141 may include 3 sets of capacitors, and the capacitance values of the 3 sets of capacitors may be all the same, some of the same or different, and may be changed according to design requirements. In some embodiments, the capacitance values of the 3 sets of capacitors are different, each set of capacitors includes a first capacitor and a second capacitor, and the first capacitor and the second capacitor have substantially equal capacitance values. The first set of capacitors of the first capacitor array 141 may include a first capacitor C1pa and a second capacitor C1pb, the second set of capacitors may include a first capacitor C2pa and a second capacitor C2pb, and the third set of capacitors may include a first capacitor C3pa and a second capacitor C3pb. The first, second and third sets of capacitors of the first capacitor array 141 may respectively correspond to a Most Significant Bit (MSB) to a Least Significant Bit (LSB) of the digital output data Dout. The first capacitor C1pa and the second capacitor C1pb may have substantially equal capacitance values of 3C, respectively, and the first group of capacitors of the first capacitor array 141 may have a capacitance value of 6C; the first capacitor C2pa and the second capacitor C2pb may have substantially equal capacitance values 2C, respectively, and the second group of capacitors of the first capacitor array 141 may have a capacitance value of 4C; the first capacitor C3pa and the second capacitor C3pb may have substantially equal capacitance values 1C, respectively, and the third set of capacitors of the first capacitor array 141 may have capacitance values 2C. The first capacitor C1pa of the first capacitor set of the first capacitor array 141 is further divided into a first capacitor portion C1pa1 and a second capacitor portion C1pa2, and the second capacitor C1pb of the first capacitor set of the first capacitor array 141 is further divided into a first capacitor portion C1pb1 and a second capacitor portion C1pb2. The capacitors C1pa1, C1pa2, C1pb1, C1pb2, C2pa, C2pb, C3pa, and C3pb may each include an upper plate and a lower plate. The upper plates of the capacitors C1pa1, C1pa2, C1pb1, C1pb2, C2pa, C2pb, C3pa, C3pb may be coupled to the switch SW1 and the first input terminal of the comparator 16.
Similarly, the second capacitor array 142 also includes 3 sets of capacitors, each set of capacitors includes a first capacitor and a second capacitor having substantially the same capacitance, and the capacitance values of the 3 sets of capacitors are different from each other. The first set of capacitors of the second capacitor array 142 may include a first capacitor C1na and a second capacitor C1nb, the second set of capacitors may include a first capacitor C2na and a second capacitor C2nb, and the third set of capacitors may include a first capacitor C3na and a second capacitor C3nb. The first, second, and third sets of capacitors of the second capacitor array 142 may correspond to the most significant bit to the least significant bit of the digital output data Dout, respectively. The first capacitor C1na and the second capacitor C1nb may have a capacitance value of 3C, respectively, and the first group of capacitors of the second capacitor array 142 may have a capacitance value of 6C; the first capacitor C2na and the second capacitor C2nb may have substantially equal capacitance values 2C, respectively, and the second group of capacitors of the second capacitor array 142 may have capacitance values 4C; the first capacitor C3na and the second capacitor C3nb may have substantially equal capacitance values 1C, respectively, and the third group of capacitors of the second capacitor array 142 may have capacitance values 2C. The first capacitor C1na of the first group of capacitors of the second capacitor array 142 is further divided into a first capacitor portion C1na1 and a second capacitor portion C1na2, and the second capacitor C1nb of the first group of capacitors of the second capacitor array 142 is further divided into a first capacitor portion C1nb1 and a second capacitor portion C1nb2. The capacitors C1na1, C1na2, C1nb1, C1nb2, C2na, C2nb, C3na, C3nb may each include an upper plate and a lower plate. The upper plates of the capacitors C1na1, C1na2, C1nb1, C1nb2, C2na, C2nb, C3na, C3nb may be coupled to the switch SW2 and the second input terminal of the comparator 16.
The first selection circuit 121 can receive the first reference voltage V1 and the second reference voltage V2 to set 3 sets of capacitances of the first capacitor array 141, and the second selection circuit 122 can receive the first reference voltage V1 and the second reference voltage V2 to set 3 sets of capacitances of the second capacitor array 142. In some embodiments, the first reference voltage V1 may be a supply voltage, e.g., 1.8V, and the second reference voltage V2 may be a ground voltage, e.g., 0V. In other embodiments, the first reference voltage V1 may be a ground voltage and the second reference voltage V2 may be a supply voltage. The first selection circuit 121 may be coupled to the lower plates of the capacitors C1pa1, C1pa2, C1pb1, C1pb2, C2pa, C2pb, C3pa, C3pb. The second selection circuit 122 may be coupled to the lower plates of the capacitors C1na1, C1na2, C1nb1, C1nb2, C2na, C2nb, C3na, C3nb.
The first selection circuit 121 and the second selection circuit 122 may be implemented by one or more multiplexers and/or switches, but are not limited thereto. One or more multiplexers and/or switches of the first selection circuit 121 may receive selection signals from the control logic circuit 18 to select one of the first reference voltage V1 and the second reference voltage V2 to output to the capacitors C1pa1, C1pa2, C1pb1, C1pb2, C2pa, C2pb, C3pa, C3pb, respectively. The one or more multiplexers and/or switches of the second selection circuit 122 may receive selection signals from the control logic circuit 18 to select one from the first reference voltage V1 and the second reference voltage V2 to output to the lower plates of the capacitors C1na1, C1na2, C1nb1, C1nb2, C2na, C2nb, C3na, C3nb, respectively. For simplicity, the first selection circuit 121 described in the following paragraphs outputs the selected voltage to the lower plates of the capacitors in the first capacitor array 141, and the second selection circuit 122 outputs the selected voltage to the lower plates of the capacitors in the second capacitor array 142.
During the sampling phase, the switches SW1 and SW2 can be turned on, and the first capacitor array 141 and the second capacitor array 142 can sample the differential input voltages Vip and Vin, respectively. During sampling, the first selection circuit 121 and the second selection circuit 122 can output the voltages in the first voltage setting or the second voltage setting to the capacitors C1pa1, C1pa2, C1pb1, C1pb2, C2pa, C2pb, C3pa, C3pb and the capacitors C1na1, C1na2, C1nb1, C1nb2, C2na, C2nb, C3na, C3nb. Table 1 and table 2 show the first voltage setting and the second voltage setting, respectively:
table 1
Capacitor with a capacitor element C1pa1 C1pa2 C1pb1 C1pb2 C2pa C2pb C3pa C3pb
Lower plate voltage V1 V1 V2 V2 V1 V2 V1 V2
Capacitor with a capacitor element C1na1 C1na2 C1nb1 C1nb2 C2na C2nb C3na C3nb
Lower plate voltage V1 V1 V2 V2 V1 V2 V1 V2
Table 2
Capacitor with a capacitor element C1pa1 C1pa2 C1pb1 C1pb2 C2pa C2pb C3pa C3pb
Lower plate voltage V2 V2 V1 V1 V2 V1 V2 V1
Capacitor with a capacitor element C1na1 C1na2 C1nb1 C1nb2 C2na C2nb C3na C3nb
Lower plate voltage V2 V2 V1 V1 V2 V1 V2 V1
In some embodiments, the first selection circuit 121 may output a corresponding voltage of the first voltage setting to the lower plate of the capacitors C1pa1, C1pa2, C1pb1, C1pb2, C2pa, C2pb, C3pa, C3pb during the sampling period, and the switch SW1 may be turned on to transmit the differential input voltage Vip to the upper plate of the capacitors C1pa1, C1pa2, C1pb1, C1pb2, C2pa, C2pb, C3pa, C3pb, thereby establishing the voltage Vp at the first receiving end of the comparator 16; the second selection circuit 122 outputs the corresponding voltage of the first voltage setting to the lower plate of the capacitors C1na1, C1na2, C1nb1, C1nb2, C2na, C2nb, C3na, C3nb during sampling, and the switch SW2 can be turned on to transmit the differential input voltage Vin to the upper plate of the capacitors C1na1, C1na2, C1nb1, C1nb2, C2na, C2nb, C3na, C3nb, thereby establishing the voltage Vn at the second receiving end of the comparator 16. In other embodiments, the first selection circuit 121 may output a corresponding voltage of the second voltage setting to the lower plate of the capacitors C1pa1, C1pa2, C1pb1, C1pb2, C2pa, C2pb, C3pa, C3pb during the sampling period, and the switch SW1 may be turned on to transmit the differential input voltage Vip to the upper plate of the capacitors C1pa1, C1pa2, C1pb1, C1pb2, C2pa, C2pb, C3pa, C3pb, thereby establishing the voltage Vp; the second selection circuit 122 can output the corresponding voltage in the second voltage setting to the lower plates of the capacitors C1na1, C1na2, C1nb1, C1nb2, C2na, C2nb, C3na, C3nb, and the switch SW2 can be turned on to transmit the differential input voltage Vin to the upper plates of the capacitors C1na1, C1na2, C1nb1, C1nb2, C2na, C2nb, C3na, and C3nb, thereby establishing the voltage Vn.
In the quantization stage, the adc 1 performs 3 conversions on 3 bits of the digital output data Dout, the comparator 16 compares the voltages Vp and Vn to generate 3 comparison results, the control logic circuit 18 stores each comparison result as a bit value of 1 bit of the digital output data Dout, and sets the first selection circuit 121 and the second selection circuit 122 to update the voltages Vp and Vn according to each comparison result. The comparison result may be a binary "0" or a binary "1". For example, when performing the most significant bit conversion, if the voltage Vp is greater than the voltage Vn, the comparator 16 may generate a binary "1" as the comparison result, the control logic circuit 18 may store the binary "1" as the most significant bit, set the first selection circuit 121 to output the ground voltage to the lower plates of the capacitors C1pa1, C1pa2, C1pb1, C1pb2 to pull down the voltage Vp, and set the second selection circuit 122 to output the supply voltage to the lower plates of the capacitors C1na1, C1na2, C1nb1, C1nb2 to boost the voltage Vn. The updated voltage Vp is lower than the previous voltage Vp, and the updated voltage Vn is higher than the previous voltage Vn. If the voltage Vp is less than the voltage Vn, the comparator 16 may generate a binary "0" as the comparison result, the control logic circuit 18 may store the binary "0" as the most significant bit, set the first selection circuit 121 to output the supply voltage to the lower plates of the capacitors C1pa1, C1pa2, C1pb1, C1pb2 to boost the voltage Vp, and set the second selection circuit 122 to output the ground voltage to the lower plates of the capacitors C1na1, C1na2, C1nb1, C1nb2 to pull down the voltage Vn. The updated voltage Vp is higher than the previous voltage Vp, and the updated voltage Vn is lower than the previous voltage Vn. The adc 1 can sequentially compare and update the voltages Vp and Vn to generate 3-bit values of 3 bits of the digital output data Dout and output the digital output data Dout for subsequent use.
Fig. 2 is a flow chart of a method 200 of operation of the analog-to-digital converter 1. The method 200 includes steps S202 to S206. Step S202 is used to reset the first capacitor array 141 and the second capacitor array 142 during the sampling period. Steps S204 and S206 are used to switch the first capacitor array 141 and the second capacitor array 142 during the conversion period to generate the digital output data Dout. Any reasonable technical variations or step adaptations are within the scope of the present disclosure. Steps S202 to S206 are as follows:
step S202, during a first sampling period, the first selection circuit 121 outputs a first reference voltage V1 to a first capacitor of each group of capacitors in the first capacitor array 141 and outputs a second reference voltage V2 to a second capacitor of each group of capacitors in the first capacitor array 141, and the second selection circuit 122 outputs the first reference voltage V1 to the first capacitor of each group of capacitors in the second capacitor array 142 and outputs the second reference voltage V2 to the second capacitor of each group of capacitors in the second capacitor array 142;
step S204, during the first conversion period, the comparator 16 compares the voltage Vp and the voltage Vn to generate a first comparison result, the first selection circuit 121 outputs the second reference voltage V2 to the first capacitance of the set of larger capacitors of the first capacitor array 141, and the second selection circuit 122 outputs the first reference voltage V1 to the second capacitance of the set of larger capacitors of the second capacitor array 142;
in step S206, during the second conversion period, the comparator 16 compares the voltage Vp with the voltage Vn to generate a second comparison result, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitance portion of the set of larger capacitances of the first capacitance array 141 or the second capacitance portion of the set of larger capacitances of the first capacitance array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitance portion of the set of larger capacitances of the second capacitance array 142 or the second capacitance portion of the set of larger capacitances of the second capacitance array 142.
In step S206, the first comparison result and the second comparison result are different. In some embodiments, the first comparison result may indicate that the voltage Vp is greater than the voltage Vn and the second comparison result may indicate that the voltage Vp is less than the voltage Vn, and the first reference voltage V1 may be greater than the second reference voltage V2. In other embodiments, the first comparison result may indicate that the voltage Vp is less than the voltage Vn and the second comparison result may indicate that the voltage Vp is greater than the voltage Vn, and the first reference voltage V1 may be less than the second reference voltage V2. The steps of the method 200 of operation are described below in conjunction with the adc 1.
During the first sampling period, the first selection circuit 121 and the second selection circuit 122 respectively reset the first capacitor array 141 and the second capacitor array 142 using the first voltage setting shown in table 1 (step S202). If the first reference voltage V1 is the supply voltage and the second reference voltage V2 is the ground voltage, during the first conversion, if the first comparison result shows that the voltage Vp is greater than the voltage Vn, the first selection circuit 121 outputs the second reference voltage V2 to the first capacitor portion C1pa1 and the second capacitor portion C1pa2 of the first capacitor C1pa of the first group of capacitors of the first capacitor array 141, and the second selection circuit 122 outputs the first reference voltage V1 to the first capacitor portion C1nb1 and the second capacitor portion C1nb2 of the second capacitor C1nb of the first group of capacitors of the second capacitor array 142, as shown in table 3 (step S204):
table 3
Capacitor with a capacitor element C1pa1 C1pa2 C1pb1 C1pb2 C2pa C2pb C3pa C3pb
Lower plate voltage “V2” “V2” V2 V2 V1 V2 V1 V2
Capacitor with a capacitor element C1na1 C1na2 C1nb1 C1nb2 C2na C2nb C3na C3nb
Lower plate voltage V1 V1 “V1” “V1” V1 V2 V1 V2
During the second transition period, if the second comparison result shows that the voltage Vp is less than the voltage Vn, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitance section C1pa1 of the first capacitance C1pa of the first group of capacitors of the first capacitance array 141 to switch back the first capacitance section C1pa1 to its reset value (V1), and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitance section C1nb1 of the second capacitance C1nb of the first group of capacitors of the second capacitance array 142 to switch back the first capacitance section C1nb1 to its reset value (V2), as shown in table 4 (step S206):
table 4
Capacitor with a capacitor element C1pa1 C1pa2 C1pb1 C1pb2 C2pa C2pb C3pa C3pb
Lower plate voltage “V1” V2 V2 V2 V1 V2 V1 V2
Capacitor with a capacitor element C1na1 C1na2 C1nb1 C1nb2 C2na C2nb C3na C3nb
Lower plate voltage V1 V1 “V2” V1 V1 V2 V1 V2
In other embodiments, during the second conversion period, if the second comparison result shows that the voltage Vp is less than the voltage Vn, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pb1 of the second capacitor C1pb of the first group of capacitors of the first capacitor array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1na1 of the first capacitor C1na of the first group of capacitors of the second capacitor array 142, as shown in table 5 (step S206):
TABLE 5
Capacitor with a capacitor element C1pa1 C1pa2 C1pb1 C1pb2 C2pa C2pb C3pa C3pb
Lower plate voltage V2 V2 “V1” V2 V1 V2 V1 V2
Capacitor with a capacitor element C1na1 C1na2 C1nb1 C1nb2 C2na C2nb C3na C3nb
Lower plate voltage “V2” V1 V1 V1 V1 V2 V1 V2
If the first reference voltage V1 is the ground voltage and the second reference voltage V2 is the power supply voltage, during the first conversion, if the first comparison result shows that the voltage Vp is less than the voltage Vn, the first selection circuit 121 outputs the second reference voltage V2 to the first capacitor portion C1pa1 and the second capacitor portion C1pa2 of the first capacitor C1pa of the first capacitor set of the first capacitor array 141, and the second selection circuit 122 outputs the first reference voltage V1 to the first capacitor portion C1nb1 and the second capacitor portion C1nb2 of the second capacitor C1nb of the first capacitor set of the second capacitor array 142, as shown in table 3 (step S204). During the second transition period, if the second comparison result shows that the voltage Vp is greater than the voltage Vn, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pa1 of the first capacitor C1pa of the first group of capacitors of the first capacitor array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1nb1 of the second capacitor C1nb of the first group of capacitors of the second capacitor array 142, as shown in table 4 (step S206). In other embodiments, during the second transition period, if the second comparison result shows that the voltage Vp is greater than the voltage Vn, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pb1 of the second capacitor C1pb of the first group of capacitors of the first capacitor array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1na1 of the first capacitor C1na of the first group of capacitors of the second capacitor array 142, as shown in table 5 (step S206).
In other embodiments, during the first sampling period, the first selection circuit 121 and the second selection circuit 122 respectively reset the first capacitor array 141 and the second capacitor array 142 using the second voltage setting shown in table 2 (step S202). If the first reference voltage V1 is the power supply voltage and the second reference voltage V2 is the ground voltage, during the first conversion, if the first comparison result shows that the voltage Vp is greater than the voltage Vn, the first selection circuit 121 outputs the second reference voltage V2 to the first capacitor portion C1pb1 and the second capacitor portion C1pb2 of the second capacitor C1pb of the first group of capacitors of the first capacitor array 141, and the second selection circuit 122 outputs the first reference voltage V1 to the first capacitor portion C1na1 and the second capacitor portion C1na2 of the first capacitor C1na of the first group of capacitors of the second capacitor array 142, as shown in table 6 (step S204):
table 6
Capacitor with a capacitor element C1pa1 C1pa2 C1pb1 C1pb2 C2pa C2pb C3pa C3pb
Lower plate voltage V2 V2 “V2” “V2” V2 V1 V2 V1
Capacitor with a capacitor element C1na1 C1na2 C1nb1 C1nb2 C2na C2nb C3na C3nb
Lower plate voltage “V1” “V1” V1 V1 V2 V1 V2 V1
During the second conversion period, if the second comparison result shows that the voltage Vp is less than the voltage Vn, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitance section C1pb1 of the second capacitance C1pb of the first group of capacitances of the first capacitance array 141 to switch back the first capacitance section C1pb1 to its reset value (V1), and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitance section C1na1 of the first capacitance C1na of the first group of capacitances of the second capacitance array 142 to switch back the first capacitance section C1na1 to its reset value (V2), as shown in table 7 (step S206):
table 7
Capacitor with improved capacitance C1pa1 C1pa2 C1pb1 C1pb2 C2pa C2pb C3pa C3pb
Lower plate voltage V2 V2 “V1” V2 V2 V1 V2 V1
Capacitor with a capacitor element C1na1 C1na2 C1nb1 C1nb2 C2na C2nb C3na C3nb
Lower plate voltage “V2” V1 V1 V1 V2 V1 V2 V1
In other embodiments, during the second transition, if the second comparison result shows that the voltage Vp is less than the voltage Vn, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pa1 of the first capacitor C1pa of the first group of capacitors of the first capacitor array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1nb1 of the second capacitor C1nb of the first group of capacitors of the second capacitor array 142, as shown in table 8 (step S206):
table 8
Capacitor with a capacitor element C1pa1 C1pa2 C1pb1 C1pb2 C2pa C2pb C3pa C3pb
Lower plate voltage “V1” V2 V2 V2 V2 V1 V2 V1
Capacitor with a capacitor element C1na1 C1na2 C1nb1 C1nb2 C2na C2nb C3na C3nb
Lower plate voltage V1 V1 “V2” V1 V2 V1 V2 V1
If the first reference voltage V1 is the ground voltage and the second reference voltage V2 is the power supply voltage, during the first conversion, if the first comparison result shows that the voltage Vp is less than the voltage Vn, the first selection circuit 121 outputs the second reference voltage V2 to the first capacitor portion C1pb1 and the second capacitor portion C1pb2 of the second capacitor C1pb of the first group of capacitors of the first capacitor array 141, and the second selection circuit 122 outputs the first reference voltage V1 to the first capacitor portion C1na1 and the second capacitor portion C1na2 of the first capacitor C1na of the first group of capacitors of the second capacitor array 142, as shown in table 6 (step S204). During the second conversion period, if the second comparison result shows that the voltage Vp is greater than the voltage Vn, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pa1 of the second capacitor C1pb of the first group of capacitors of the first capacitor array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1na1 of the first capacitor C1na of the first group of capacitors of the second capacitor array 142, as shown in table 7 (step S206). In other embodiments, during the second transition period, if the second comparison result shows that the voltage Vp is greater than the voltage Vn, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pa1 of the first capacitor C1pa of the first group of capacitors of the first capacitor array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1nb1 of the second capacitor C1nb of the first group of capacitors of the second capacitor array 142, as shown in table 8 (step S206).
The first sampling period may belong to a first sampling stage, the first conversion period and the second conversion period may belong to a first quantization stage, and the first sampling stage and the first quantization stage may belong to a first operation cycle. After the first operation period, the adc 1 sequentially generates 3 comparison results and outputs the digital output data Dout according to the 3 comparison results. In a second operation cycle following the first operation cycle, the adc 1 may repeat steps S202 to S206 to generate 3 comparison results, and output the subsequent digital output data Dout according to the 3 comparison results.
The second operation cycle may include a second sampling phase, which may include a second sampling period, and a second quantization phase, which may include a third conversion period followed by a fourth conversion period. The third conversion period may correspond to the first conversion period for generating the higher corresponding bit of the digital output data Dout, and the fourth conversion period may correspond to the second conversion period for generating the lower corresponding bit of the digital output data Dout. The second conversion period and the fourth conversion period may not be limited to be directly consecutive to the first conversion period and the third conversion period. In some embodiments, when the adc 1 performs the third bit conversion, the second capacitance portion of the first capacitor or the second capacitance portion of the second capacitor in the first set of capacitors of the first capacitor array 141/the second capacitor array 142, i.e. the capacitors C1pa2, C1pb2, C1na2, C1nb2, may also be switched in a similar manner. In other embodiments, if the number of the capacitor arrays is large (for example, ten bits), the first capacitor and the second capacitor of the large set of capacitors of the first capacitor array 141/the second capacitor array 142 may be divided into a plurality of capacitor portions, and the capacitance values of the capacitor portions are substantially equal to the capacitance value of the first capacitor of one or more smaller capacitors, and when performing other conversions except for the maximum bit in combination with the method 200, if the comparison result is different from the maximum bit result, one of the capacitors of the large set of capacitors may be selected to be switched back to complete the conversion.
In some embodiments, during the second sampling period, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitance of each group of capacitors in the first capacitor array 141 and outputs the second reference voltage V2 to the second capacitance of each group of capacitors in the first capacitor array 141, and the second selection circuit 122 outputs the first reference voltage V1 to the first capacitance of each group of capacitors in the second capacitor array 142 and outputs the second reference voltage V2 to the second capacitance of each group of capacitors in the second capacitor array 142, as shown in table 1. During the third conversion period, the comparator 16 compares the voltage at the first input terminal with the voltage at the second input terminal to generate a third comparison result, the first selection circuit 121 outputs the second reference voltage V2 to the first capacitor C1pa of the set of larger capacitors of the first capacitor array 141, and the second selection circuit 122 outputs the first reference voltage V1 to the second capacitor C1nb of the set of larger capacitors of the second capacitor array 142, as shown in table 3. During the fourth conversion period, the comparator 16 compares the voltage of the first input terminal and the voltage of the second input terminal to generate a fourth comparison result, and the third comparison result is different from the fourth comparison result.
If the comparison results generated in the second conversion period and the fourth conversion period are different from the comparison results generated in the first conversion period and the third conversion period, respectively, the adc 1 may switch the first capacitor array 141 and the second capacitor array 142 in the second conversion period and the fourth conversion period by using a fixed switching manner, for example, one of tables 4, 5, 7, and 8 is used to switch the first capacitor array 141 and the second capacitor array 142.
In some embodiments, the adc 1 may also switch the first capacitor array 141 and the second capacitor array 142 by using an alternate switching method, such as alternately using table 4 and table 5 or alternately using table 7 and table 8 to switch the first capacitor array 141 and the second capacitor array 142.
In other embodiments, the adc 1 may also randomly output the voltage settings of tables 4 and 5 to the first capacitor array 141 and the second capacitor array 142 according to a uniform random order (uniform random) or randomly output the voltage settings of tables 7 and 8 to the first capacitor array 141 and the second capacitor array 142 according to a uniform random order. The uniform random order is a random order in which the probabilities of the voltage settings of output tables 4 and 5 are substantially the same, or the probabilities of the voltage settings of output tables 7 and 8 are substantially the same.
In other embodiments, the adc 1 can also output the voltage settings of table 4 and table 5 to the first capacitor array 141 and the second capacitor array 142 according to a uniform specific order, or output the voltage settings of table 7 and table 8 to the first capacitor array 141 and the second capacitor array 142 according to a uniform specific order. The uniform specific order may be a non-purely alternating or non-purely random order, wherein the probabilities of the voltage settings of output tables 4 and 5 are substantially the same, or the probabilities of the voltage settings of output tables 7 and 8 are substantially the same. For example, the uniform particular sequence may be that N quantization stages output the voltage settings of table 4 to the first and second capacitor arrays 141 and 142, and the subsequent N quantization stages output the voltage settings of table 5 to the first and second capacitor arrays 141 and 142. In another example, in other examples, the uniform specific sequence may be determined by whether the corresponding conversion period of the previous quantization stage needs to be switched to output the voltage setting of table 4 or table 5 to the first capacitor array 141 and the second capacitor array 142 during the current conversion period.
In some embodiments, during the second transition, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pa1 of the set of larger capacitors C1pa of the first capacitor array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1nb1 of the set of larger capacitors C1nb of the second capacitor array 142, as shown in table 4; during the fourth transition, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitance section C1pb1 of the set of larger capacitance second capacitances C1pb of the first capacitance array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitance section C1na1 of the set of larger capacitance first capacitances C1na of the second capacitance array 142, as shown in table 5.
In other embodiments, during the second transition, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitance section C1pb1 of the set of larger capacitance second capacitances C1pb of the first capacitance array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitance section C1na1 of the set of larger capacitance first capacitances C1na of the second capacitance array 142, as shown in table 5; during the fourth transition period, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pa1 of the first capacitor C1pa of the set of larger capacitors of the first capacitor array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1nb1 of the second capacitor C1nb of the set of larger capacitors of the second capacitor array 142, as shown in table 4.
In other embodiments, during the second transition, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitance section C1pb1 of the set of larger capacitance second capacitances C1pb of the first capacitance array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitance section C1nb1 of the set of larger capacitance second capacitances C1nb of the second capacitance array 142, as shown in table 9; during the fourth transition period, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pa1 of the set of larger capacitors C1pa of the first capacitor array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1na1 of the set of larger capacitors C1na of the second capacitor array 142, as shown in table 10:
table 9
Capacitor with a capacitor element C1pa1 C1pa2 C1pb1 C1pb2 C2pa C2pb C3pa C3pb
Lower plate voltage V2 V2 “V1” V2 V1 V2 V1 V2
Capacitor with a capacitor element C1na1 C1na2 C1nb1 C1nb2 C2na C2nb C3na C3nb
Lower plate voltage V1 V1 “V2” V1 V1 V2 V1 V2
Table 10
Capacitor with improved capacitance C1pa1 C1pa2 C1pb1 C1pb2 C2pa C2pb C3pa C3pb
Lower plate voltage “V1” V2 V2 V2 V1 V2 V1 V2
Capacitor with a capacitor element C1na1 C1na2 C1nb1 C1nb2 C2na C2nb C3na C3nb
Lower plate voltage “V2” V1 V1 V1 V1 V2 V1 V2
In other embodiments, during the second transition, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pa1 of the set of larger capacitors C1pa of the first capacitor array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1na1 of the set of larger capacitors C1na of the second capacitor array 142, as shown in table 10; during the fourth transition, the first selection circuit 121 outputs the first reference voltage V1 to the first capacitor portion C1pb1 of the set of larger second capacitors C1pb of the first capacitor array 141, and the second selection circuit 122 outputs the second reference voltage V2 to the first capacitor portion C1nb1 of the set of larger second capacitors C1nb of the second capacitor array 142, as shown in table 9.
The method 200 employs a partial capacitance trick of back-cutting larger capacitances to reduce differential non-linearity errors and integral non-linearity errors generated by capacitance mismatch between different sets of capacitances in the first capacitor array 141 and the second capacitor array 142.
In some embodiments, if the first capacitor array 141 and the second capacitor array 142 are both configured with 10-bit binary weighted capacitors, each group of capacitors has random drift with a standard deviation of two percent of capacitance, the method 200 is used to operate when the group of capacitors with larger capacitance is operated using the method 200 during the second transition and other subsequent transitions, the differential nonlinear error is reduced from 0.37LSB to 0.31LSB, and the integral nonlinear error is reduced from 0.82LSB to 0.8LSB. In other embodiments, when the first capacitance portion of the first capacitance of the set of larger capacitances and the first capacitance portion of the second capacitance of the set of larger capacitances are switched in a uniform random order or an alternating order during the second transition, the differential nonlinear error is reduced from 0.37LSB to 0.21LSB and the integral nonlinear error is reduced from 0.82LSB to 0.48LSB
The present invention is not limited to the 3-bit SAR ADC employed in the embodiments, and those skilled in the art can also apply the method 200 to SAR ADCs of other sizes according to the spirit of the present invention. The ADC 1 and the operation method 200 switch the first capacitor array 141 and the second capacitor array 142 using a back-cut technique, so as to reduce a differential non-linear error and an integral non-linear error generated by a mismatch of capacitors between the same capacitor set or different capacitor sets, thereby greatly improving the linearity of the SAR ADC.
The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in the claims of the present invention should fall within the protection scope of the present invention.
Description of reference numerals:
1: analog-to-digital converter
121 first selection circuit
122 second selection circuit
141 first capacitor array
142 second capacitor array
16: comparator
18 control logic circuit
200 method
S202 to S206
Capacitors C1pa, C1pa1, C1pa2, C1pb, C1pb1, C1pb2, C2pa, C2pb, C3pa, C3pb, C1na, C1na1, C1na2, C1nb, C1nb1, C1nb2, C2na, C2nb, C3na, C3nb
Dout digital output data
SW1, SW2 switches
V1 first reference voltage
V2 second reference voltage
Vip, vin, differential input voltage
Voltage Vp, vn

Claims (8)

1. A method of operating an analog-to-digital converter, the analog-to-digital converter comprising a first capacitor array, a first selection circuit, a second capacitor array, a second selection circuit, a comparator, and a control logic circuit, the first capacitor array comprising a plurality of sets of capacitors, each set of capacitors in the first capacitor array comprising a first capacitor and a second capacitor, the second capacitor array comprising a plurality of sets of capacitors, each set of capacitors in the second capacitor array comprising a first capacitor and a second capacitor, the first selection circuit coupled to the first capacitor array, the second selection circuit coupled to the second capacitor array, the comparator comprising a first input coupled to the first capacitor array and a second input coupled to the second capacitor array, the control logic circuit coupled to the first selection circuit, the second selection circuit, and the comparator, the method comprising:
during a first sampling period, the first selection circuit outputs a first reference voltage to the first capacitance of the each group of capacitances in the first capacitance array and a second reference voltage to the second capacitance of the each group of capacitances in the first capacitance array, the second selection circuit outputs the first reference voltage to the first capacitance of the each group of capacitances in the second capacitance array and the second reference voltage to the second capacitance of the each group of capacitances in the second capacitance array;
during a first transition, the comparator compares a voltage of the first input terminal and a voltage of the second input terminal to generate a first comparison result, the first selection circuit outputs the second reference voltage to a first capacitor of a set of larger capacitors of the first capacitor array, and the second selection circuit outputs the first reference voltage to a second capacitor of a set of larger capacitors of the second capacitor array; and
during a second transition period subsequent to the first transition period, the comparator compares a voltage of the first input terminal and a voltage of the second input terminal to generate a second comparison result, the first selection circuit outputs the first reference voltage to a first capacitance portion of the first capacitance of the set of larger capacitances of the first capacitance array or a first capacitance portion of a second capacitance of the set of larger capacitances of the first capacitance array, and the second selection circuit outputs the second reference voltage to a first capacitance portion of the first capacitance of the set of larger capacitances of the second capacitance array or a first capacitance portion of the second capacitance of the set of larger capacitances of the second capacitance array;
wherein the first comparison result and the second comparison result are different.
2. The method of operation of claim 1, wherein:
the first comparison result shows that the voltage of the first input end of the comparator is greater than the voltage of the second input end;
the second comparison result shows that the voltage of the first input end of the comparator is smaller than the voltage of the second input end; and
the first reference voltage is greater than the second reference voltage.
3. The method of operation of claim 1, wherein:
the first comparison result shows that the voltage of the first input end of the comparator is smaller than the voltage of the second input end;
the second comparison result shows that the voltage of the first input end of the comparator is greater than the voltage of the second input end; and
the first reference voltage is less than the second reference voltage.
4. The method of operation of claim 1, wherein:
a capacitance value of the first capacitive portion of the first capacitance of the set of larger capacitances of the first capacitive array is substantially equal to a capacitance value of a first capacitance of a set of smaller capacitances of the first capacitive array;
a capacitance value of the first capacitive portion of the second capacitance of the set of larger capacitances of the first capacitive array is substantially equal to a capacitance value of the first capacitance of the set of smaller capacitances of the first capacitive array;
a capacitance value of the first capacitance portion of the first capacitance of the set of larger capacitances of the second capacitance array is substantially equal to a capacitance value of a first capacitance of a set of smaller capacitances of the second capacitance array; and
the capacitance value of the first capacitive portion of the second capacitance of the larger set of capacitances of the second capacitive array is substantially equal to the capacitance value of the first capacitance of the smaller set of capacitances of the second capacitive array.
5. The method of operation of claim 1, further comprising:
during a second sampling period, the first selection circuit outputs the first reference voltage to the first capacitance of each group of capacitances in the first capacitance array and the second reference voltage to the second capacitance of each group of capacitances in the first capacitance array, the second selection circuit outputs the first reference voltage to the first capacitance of each group of capacitances in the second capacitance array and the second reference voltage to the second capacitance of each group of capacitances in the second capacitance array;
during a third transition, the comparator compares a voltage of the first input terminal and a voltage of the second input terminal to generate a third comparison result, the first selection circuit outputs the second reference voltage to the first capacitance of the set of larger capacitances of the first capacitance array, the second selection circuit outputs the first reference voltage to the second capacitance of the set of larger capacitances of the second capacitance array; and
during a fourth transition period subsequent to the third transition period, the comparator compares a voltage of the first input terminal and a voltage of the second input terminal to generate a fourth comparison result, the first selection circuit outputs the first reference voltage to the first capacitance portion of the first capacitance of the set of larger capacitances of the first capacitance array if the first selection circuit outputs the first reference voltage to the first capacitance portion of the first capacitance of the set of larger capacitances of the first capacitance array during the second transition period, the second selection circuit outputs the second reference voltage to the first capacitance portion of the first capacitance of the set of larger capacitances of the second capacitance array if the second selection circuit outputs the second reference voltage to the first capacitance portion of the second capacitance of the set of larger capacitances of the second capacitance array during the second transition period;
wherein the third comparison result and the fourth comparison result are different.
6. The method of operation of claim 1, further comprising:
during a second sampling period, the first selection circuit outputs the first reference voltage to the first capacitance of each group of capacitances in the first capacitance array and the second reference voltage to the second capacitance of each group of capacitances in the first capacitance array, the second selection circuit outputs the first reference voltage to the first capacitance of each group of capacitances in the second capacitance array and the second reference voltage to the second capacitance of each group of capacitances in the second capacitance array;
during a third transition, the comparator compares a voltage of the first input terminal and a voltage of the second input terminal to generate a third comparison result, the first selection circuit outputs the second reference voltage to the first capacitance of the set of larger capacitances of the first capacitance array, the second selection circuit outputs the first reference voltage to the second capacitance of the set of larger capacitances of the second capacitance array; and
during a fourth transition period subsequent to the third transition period, the comparator compares a voltage of the first input terminal and a voltage of the second input terminal to generate a fourth comparison result, the first selection circuit outputs the first reference voltage to the first capacitance portion of the second capacitance of the set of larger capacitances of the first capacitance array if the first selection circuit outputs the first reference voltage to the first capacitance portion of the first capacitance of the set of larger capacitances of the first capacitance array during the second transition period, the second selection circuit outputs the second reference voltage to the first capacitance portion of the second capacitance of the set of larger capacitances of the second capacitance array if the second selection circuit outputs the second reference voltage to the first capacitance portion of the first capacitance of the set of larger capacitances of the second capacitance array during the second transition period;
wherein the third comparison result and the fourth comparison result are different.
7. The method of operation of claim 1, further comprising:
during a second sampling period, the first selection circuit outputs the first reference voltage to the first capacitance of each group of capacitances in the first capacitance array and the second reference voltage to the second capacitance of each group of capacitances in the first capacitance array, the second selection circuit outputs the first reference voltage to the first capacitance of each group of capacitances in the second capacitance array and the second reference voltage to the second capacitance of each group of capacitances in the second capacitance array;
during a third transition, the comparator compares a voltage of the first input terminal and a voltage of the second input terminal to generate a third comparison result, the first selection circuit outputs the second reference voltage to the first capacitance of the set of larger capacitances of the first capacitance array, the second selection circuit outputs the first reference voltage to the second capacitance of the set of larger capacitances of the second capacitance array; and
during a fourth transition period subsequent to the third transition period, the comparator compares a voltage of the first input terminal and a voltage of the second input terminal to generate a fourth comparison result, the first selection circuit outputs the first reference voltage to the first capacitance portion of the second capacitance of the set of larger capacitances of the first capacitance array if the first selection circuit outputs the first reference voltage to the first capacitance portion of the first capacitance of the set of larger capacitances of the first capacitance array during the second transition period, the second selection circuit outputs the second reference voltage to the first capacitance portion of the first capacitance of the set of larger capacitances of the second capacitance array if the second selection circuit outputs the second reference voltage to the first capacitance portion of the second capacitance of the set of larger capacitances of the second capacitance array during the second transition period;
wherein the third comparison result and the fourth comparison result are different.
8. The method of operation of claim 1, further comprising:
during a second sampling period, the first selection circuit outputs the first reference voltage to the first capacitance of each group of capacitances in the first capacitance array and the second reference voltage to the second capacitance of each group of capacitances in the first capacitance array, the second selection circuit outputs the first reference voltage to the first capacitance of each group of capacitances in the second capacitance array and the second reference voltage to the second capacitance of each group of capacitances in the second capacitance array;
during a third transition, the comparator compares a voltage of the first input terminal and a voltage of the second input terminal to generate a third comparison result, the first selection circuit outputs the second reference voltage to the first capacitance of the set of larger capacitances of the first capacitance array, the second selection circuit outputs the first reference voltage to the second capacitance of the set of larger capacitances of the second capacitance array; and
during a fourth transition period subsequent to the third transition period, the comparator compares the voltage at the first input terminal and the voltage at the second input terminal to generate a fourth comparison result, the first selection circuit outputs the first reference voltage to the first capacitance portion of the first capacitance of the set of larger capacitances of the first capacitance array if the first selection circuit outputs the first reference voltage to the first capacitance portion of the second capacitance of the set of larger capacitances of the first capacitance array during the second transition period, and the second selection circuit outputs the second reference voltage to the first capacitance portion of the second capacitance of the set of larger capacitances of the second capacitance array if the second selection circuit outputs the second reference voltage to the first capacitance portion of the first capacitance of the set of larger capacitances of the second capacitance array during the second transition period;
wherein the third comparison result and the fourth comparison result are different.
CN202110676094.4A 2021-06-18 2021-06-18 Analog-to-digital converter and operation method thereof Pending CN115499012A (en)

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