CN112825485B - Continuous asymptotic analog-to-digital converter and reference ripple suppression circuit thereof - Google Patents
Continuous asymptotic analog-to-digital converter and reference ripple suppression circuit thereof Download PDFInfo
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Abstract
The invention provides a reference ripple suppression circuit suitable for a follow-up asymptotic analog-to-digital converter, which comprises a plurality of code dependent compensation units, wherein each code dependent compensation unit comprises a logic circuit and a compensation capacitor. The first plate of the compensation capacitor receives a reference voltage to be compensated, and the second plate of the compensation capacitor receives an output of a logic circuit, wherein the logic circuit performs a logic operation on an output code of the successive approximation analog-to-digital converter and at least one logic value representing a base plate voltage of the switched digital-to-analog converter. The kth switch of the successive-asymptotic analog-to-digital converter uses at most (k-1) code-dependent compensation units.
Description
Technical Field
The present invention relates to an analog-to-digital converter (ADC), and more particularly, to a sequential asymptotic analog-to-digital converter (SAR ADC) with low-complexity code-dependent reference ripple suppression (reference ripple suppression).
Background
The successive approximation analog-to-digital converter (successive approximation register analog-to-digital converter, SAR ADC, or analog-to-digital converter) is one type of analog-to-digital converter (ADC, or analog-to-digital converter) for equivalently converting an analog signal into a digital signal. The successive approximation analog-to-digital converter performs the conversion by comparing and searching all possible quantization levels to obtain a digital output. Compared to a typical analog-to-digital converter, a sequential asymptotic analog-to-digital converter uses less circuit area and corresponding cost.
Considering the reference voltage generation circuit, its power consumption is generally greater than that of the main circuit of the successive approximation analog-to-digital converter. The successive approximation analog-to-digital converter (capacitive digital-to-analog converter, or referred to as capacitor digital-to-analog converter) requires repeated switching of the capacitor digital-to-analog converter, so that current is repeatedly drawn from the reference voltage generating circuit, making driving of the reference voltage generating circuit more difficult. Furthermore, conventional cyclic asymptotic analog-to-digital converter nonlinearities, in particular differential nonlinearities (differential nonlinearity, DNL).
Therefore, a new and improved sequential asymptotic analog-to-digital converter is needed to improve linearity, power consumption and circuit area.
Disclosure of Invention
In view of the foregoing, an objective of the embodiments of the present invention is to provide a sequential asymptotic analog-to-digital converter (SAR ADC) with low complexity code-dependent reference ripple suppression, which is used to suppress Differential Nonlinearity (DNL) and further save the power and circuit area of the reference voltage generating circuit.
The aim of the invention is achieved by adopting the following technical scheme. The reference ripple suppression circuit for a continuous asymptotic analog-to-digital converter according to the present invention includes a plurality of code dependent compensation units, each of which includes a logic circuit and a compensation capacitor. The first plate of the compensation capacitor receives a reference voltage to be compensated, and the second plate of the compensation capacitor receives an output of a logic circuit, wherein the logic circuit performs a logic operation on an output code of the successive approximation analog-to-digital converter and at least one logic value representing a base plate voltage of the switched digital-to-analog converter. The kth switch of an n-bit sequential asymptotic analog-to-digital converter uses at most (k-1) code dependent compensation units, k being a positive integer from 1 to (n-1), n being a positive integer greater than 1.
The object of the invention can be further achieved by the following technical measures.
The reference ripple suppression circuit for a continuous asymptotic analog-to-digital converter includes an output code pair including B p [k]And B is connected with n [k]And at least one logic value of the backplane voltage comprises a pair of board signals comprising bot p *[i]With bot n *[i]Wherein i is a positive integer from 1 to (k-1), B n [k]Is B p [k]Is the inverse logical value of (bot) p *[i]To represent the inverse logic value of the bottom plate voltage of the switched digital-to-analog converter, bot n *[i]Is bot p *[i]Is a logical value of the inverse of (a).
The reference ripple suppression circuit for a continuous asymptotic analog-to-digital converter according to the above, wherein the logic performs logic operations during sampling and conversion according to the following truth table:
the reference ripple rejection circuit for a sequential asymptotic analog-to-digital converter described above uses only the code dependent compensation units at the mth and thereafter, but tolerates errors caused by uncompensated errors by adding redundancy, where m is a positive integer greater than 2.
The reference ripple suppression circuit for a continuous asymptotic analog-to-digital converter according to the above, wherein only the code dependent compensation unit having the capacitance of the compensation capacitor greater than a predetermined threshold is used.
The above-mentioned reference ripple suppression circuit for a continuous asymptotic analog-to-digital converter, wherein the maximum number of the code-dependent compensation units increases linearly with the switching number of the continuous asymptotic analog-to-digital converter.
The aim of the invention is also achieved by adopting the following technical scheme. According to the present invention, a reference ripple suppression circuit for a continuous asymptotic analog-to-digital converter includes: a plurality of code independent compensation units, each of the code independent compensation units comprising a first logic circuit and a first compensation capacitor, a first plate of the first compensation capacitor receiving a reference voltage to be compensated and a second plate of the first compensation capacitor receiving an output of the first logic circuit, wherein the first logic circuit performs a logic operation on an output code of the successive approximation analog-to-digital converter; and a plurality of code dependent compensation units, each of the code dependent compensation units comprising a second logic circuit and a second compensation capacitor, a first plate of the second compensation capacitor receiving the reference voltage to be compensated and a second plate of the second compensation capacitor receiving an output of the second logic circuit, wherein the second logic circuit performs a logic operation on an output code of the successive approximation analog-to-digital converter and at least one logic value representing a base plate voltage of the switching digital-to-analog converter; wherein n-bit successive approximation analog-to-digital converter uses (n-1) at most the code independent compensation units, and k-th switching of the successive approximation analog-to-digital converter uses (k-1) at most the code dependent compensation units, where n is a positive integer greater than 1 and k is a positive integer from 1 to (n-1).
The object of the invention can be further achieved by the following technical measures.
The output code includes a differential signal pair for the first logic circuit to perform a logic operation.
The reference ripple rejection circuit for a sequential asymptotic analog-to-digital converter according to the above, wherein the logic operation performed by the first logic circuit comprises an OR (OR) logic operation.
The reference ripple suppression circuit for a continuous asymptotic analog-to-digital converter includes an output code pair including B p [k]And B is connected with n [k]And at least one logic value of the backplane voltage comprises a pair of board signals comprising bot p *[i]With bot n *[i]Wherein i is a positive integer from 1 to (k-1), B n [k]Is B p [k]Is the inverse logical value of (bot) p *[i]To represent the inverse logic value of the bottom plate voltage of the switched digital-to-analog converter, bot n *[i]Is bot p *[i]Is a logical value of the inverse of (a).
The reference ripple suppression circuit for a continuous asymptotic analog-to-digital converter according to the above, wherein the second logic performs logic operations during sampling and conversion according to the following truth table:
the reference ripple suppression circuit for a continuous asymptotic analog-to-digital converter described above uses only the code independent compensation unit and the code dependent compensation unit at the mth and thereafter, but tolerates errors caused by uncompensated errors by adding redundancy, where m is a positive integer greater than 2.
The reference ripple suppression circuit for a continuous asymptotic analog-to-digital converter according to the above, wherein only the code independent compensation unit and the code dependent compensation unit with the capacitance values of the first and second compensation capacitors greater than a predetermined threshold are used.
The above-mentioned reference ripple suppression circuit for a continuous asymptotic analog-to-digital converter, wherein the maximum number of the code independent compensation units and the code dependent compensation units increases linearly with the switching number of the continuous asymptotic analog-to-digital converter.
The aim of the invention is also achieved by adopting the following technical scheme. According to the present invention, a continuous asymptotic analog-to-digital converter includes: at least one switching digital-to-analog converter receiving an input signal to generate an output signal; a comparator receiving the output signal; a follow-up asymptotic controller for generating an output code according to the comparison output of the comparator; a reference buffer for generating a reference voltage to the switching digital-to-analog converter; and a reference ripple suppression circuit for suppressing a reference ripple of the reference voltage, the reference ripple suppression circuit comprising:
a plurality of code independent compensation units, each of the code independent compensation units comprising a first logic circuit and a first compensation capacitor, a first plate of the first compensation capacitor receiving the reference voltage and a second plate of the first compensation capacitor receiving an output of the first logic circuit, wherein the first logic circuit performs a logic operation on an output code of the successive approximation analog-to-digital converter; and a plurality of code dependent compensation units, each of the code dependent compensation units comprising a second logic circuit and a second compensation capacitor, a first plate of the second compensation capacitor receiving the reference voltage and a second plate of the second compensation capacitor receiving an output of the second logic circuit, wherein the second logic circuit performs a logic operation on an output code of the successive approximation analog-to-digital converter and at least one logic value representing a bottom plate voltage of the switching digital-to-analog converter; wherein n-bit successive approximation analog-to-digital converter uses (n-1) at most the code independent compensation units, and k-th switching of the successive approximation analog-to-digital converter uses (k-1) at most the code dependent compensation units, where n is a positive integer greater than 1 and k is a positive integer from 1 to (n-1).
In the aforementioned sequential asymptotic analog-to-digital converter, the output code includes differential signal pairs for the first logic circuit to perform logic operation.
In the aforementioned sequential asymptotic analog-to-digital converter, the logic operation performed by the first logic circuit includes an OR (OR) logic operation.
The aforementioned sequential asymptotic analog-to-digital converter, wherein the output code comprises an output code pair comprising B p [k]And B is connected with n [k]And at least one logic value of the backplane voltage comprises a pair of board signals comprising bot p *[i]With bot n *[i]Wherein i is a positive integer from 1 to (k-1), B n [k]Is B p [k]Is the inverse logical value of (bot) p *[i]To represent the inverse logic value of the bottom plate voltage of the switched digital-to-analog converter, bot n *[i]Is bot p *[i]Is a logical value of the inverse of (a).
In the aforementioned sequential asymptotic analog-to-digital converter, the second logic circuit performs logic operations during sampling and conversion according to the following truth table:
the above-mentioned sequential asymptotic analog-to-digital converter uses only the code independent compensation unit and the code dependent compensation unit at the mth and thereafter, but tolerates errors caused by uncompensated by adding redundancy, where m is a positive integer greater than 2.
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention, as well as the preferred embodiments thereof, together with the following detailed description of the invention, given by way of illustration only, together with the accompanying drawings.
Drawings
FIG. 1 is a block diagram of a sequential asymptotic analog-to-digital converter (SAR ADC) with low complexity code dependent reference ripple suppression according to an embodiment of the present disclosure.
Fig. 2 is a circuit diagram of a code independent compensation unit of the reference ripple rejection circuit (fig. 1) according to an embodiment of the present invention.
FIG. 3 is a circuit diagram of a code dependent compensation unit according to an embodiment of the invention.
Fig. 4A-4D illustrate compensation mechanisms for 4-bit analog-to-digital converters.
[ symbolic description ]
100: continuous asymptotic analog-to-digital converter
11A: first digital-to-analog converter
11B: second digital-to-analog converter
12: start switch
13: comparator with a comparator circuit
14: continuous asymptotic controller
15: reference buffer
16: reference ripple suppression circuit
16A: code independent compensation unit
16B: code dependent compensation unit
161: first logic circuit
162: second logic circuit
V DD : supply voltage
Vref: reference voltage
Vip: first input signal
Vin: a second input signal
Vop: a first output signal
Von: a second output signal
B p : first element
B n : second element
B p [k]: first element
B n [k]: second element
bot p *[i]: first element
bot n *[i]: second element
C C0,k : first compensation capacitor
C Ck,i : second compensation capacitor
C C0,1 、C C0,2 、C C0,3 : first compensation capacitor
C C2,1 、C C3,1 、C C3,2 : second compensation capacitor
Detailed Description
In order to further describe the technical means and effects adopted for achieving the preset aim of the present invention, the following detailed description refers to the specific implementation, structure, characteristics and effects of the continuous asymptotic analog-to-digital converter and the reference ripple suppression circuit according to the present invention with reference to the accompanying drawings and the preferred embodiments.
FIG. 1 shows a block diagram of a sequential asymptotic analog-to-digital converter (SAR ADC) 100 with low-complexity code-dependent reference ripple suppression (reference ripple suppression) according to an embodiment of the present disclosure.
In this embodiment, the successive approximation analog-to-digital converter 100 (hereinafter referred to as an analog-to-digital converter) may include at least one switched digital-to-analog converter (switched DAC), such as a first digital-to-analog converter (DAC) 11A (e.g., capacitor array) and a second digital-to-analog converter (DAC) 11B (e.g., capacitor array), for receiving the first input signal Vip and the second input signal Vin via the enable switch (bootstrapped switch) 12, respectively, so as to generate the first output signal Vop and the second output signal Von, respectively.
The analog-to-digital converter 100 of the present embodiment may include a comparator 13 for receiving the first output signal Vop and the second output signal Von at a first input node (e.g., a positive (+) input node) and a second input node (e.g., a negative (-) input node), respectively. MouldThe analog-to-digital converter 100 may include a Successive Asymptotic (SAR) controller 14 that sequentially generates output codes from Most Significant Bits (MSBs) to Least Significant Bits (LSBs) according to a comparison output of the comparator 13. The analog-to-digital converter 100 can control the switching of the first digital-to-analog converter 11A and the second digital-to-analog converter 11B according to the comparison output of the comparator 13. The present embodiment uses a differential signal (differential signaling) mechanism, so the output code may comprise a differential signal pair, e.g., a code pair (code pair), comprising B p And B is connected with n Wherein B is n Is B p Is the inverse (or complementary) logical value of (i) a. In another embodiment, a single-ended mechanism is used, so the output code may comprise a single output value.
In this embodiment, the adc 100 may include a reference buffer (reference buffer) 15 for generating the reference voltage Vref, which is provided to the first adc 11A and the second adc 11B. According to one of the features of the present embodiment, the analog-to-digital converter 100 may include a reference ripple suppression (reference ripple suppression) circuit 16 for suppressing the reference ripple of the reference voltage Vref, which may include a plurality of code-independent (code-independent) compensation units 16A and code-dependent (code-independent) compensation units 16B.
Fig. 2 shows a circuit diagram of a code-independent (code-independent) compensation unit 16A of the reference ripple suppression circuit 16 (fig. 1) according to an embodiment of the present invention. In the present embodiment, one code independent compensation unit 16A is used for each switching (of the first digital-to-analog converter 11A and the second digital-to-analog converter 11B). The code independent compensation unit 16A may include a first logic circuit 161 and a first compensation capacitor C C0,k Corresponding to the kth handoff. First compensation capacitor C C0,k A first plate receiving a reference voltage Vref to be compensated, a first compensation capacitor C C0,k The second board of (c) receives the output of the first logic circuit 161 of the code independent compensation unit 16A. For an n-bit analog-to-digital converter 100 (n is a positive integer greater than 1), which performs (n-1) switches, so that (n-1) code independent compensation units 16A (and corresponding first compensation capacitors C) are used at most C0,k ) Wherein k is 1 toA positive integer of (n-1). For example, the 4-bit analog-to-digital converter 100 uses a total of three first compensation capacitors C C0,1 、C C0,2 、C C0,3 . In one embodiment, a first compensation capacitor C C0,k Capacitance C of (2) C0 (k) The method can be expressed as follows:
wherein C is S (k) For the kth switched capacitor, N is the resolution of the analog-to-digital converter 100, C (j) is the jth capacitor of the switched digital-to-analog converter (e.g., the first digital-to-analog converter 11A), vref is the reference voltage to be compensated, C DAC For switching the total capacitance of a digital-to-analog converter (e.g. the first digital-to-analog converter 11A), and V DD Is the supply voltage.
Code independent compensation unit 16A receives an output code pair comprising B p [k](first element) and B n [k](second element), where k represents the kth switch. The first logic circuit 161 of the code independent compensation unit 16A performs OR logic operation on the output code pair B p And B is connected with n 。
Fig. 3 is a circuit diagram of a code-dependent compensation unit 16B according to an embodiment of the present invention. In the present embodiment, at most (k-1) code dependent compensation units 16B are used for the kth switching (of the first digital-to-analog converter 11A and the second digital-to-analog converter 11B). The ith code dependent compensation unit 16B of the kth switch may include a second logic circuit 162 and a second compensation capacitor C Ck,i Where i is a positive integer from 1 to (k-1) and k is from 1 to (n-1) for the n-bit analog-to-digital converter 100. For example, the 4-bit analog-to-digital converter 100 uses a second compensation capacitor C at the 2 nd switch C2,1 Using two second compensation capacitors C for the 3 rd switching C3,1 、C C3,2 . Second compensation capacitor C Ck,i A first plate receiving a reference voltage Vref to be compensated, a second compensation capacitor C Ck,i Second logic of the second board received code dependent compensation unit 16BThe output of circuit 162. In one embodiment, a second compensation capacitor C Ck,i Capacitance C of (2) C (k, i) may be represented as follows:
code dependent compensation unit 16B receives an output code pair comprising B p [k](first element) and B n [k](second element), and receives a board signal pair (plate signal pair) comprising a bot p *[i](first element) and bot n *[i](second element), wherein bot p * To represent the inverse logical value of the backplane voltage of a switched digital-to-analog converter, bot n * Is bot p * K represents the kth switch, i represents the ith code-dependent compensation unit 16B. Table 1 below is a truth table for the second logic circuit of the code dependent compensation unit of FIG. 3 to perform a logic operation. The second logic 162 of the code dependent compensation unit 16B performs logic operations on the output code pair B during sampling (sampling) and conversion (conversion) according to the truth table (truth table) of Table 1 p [k]/B n [k]Board signal pair bot p *[i]/bot n *[i]. Thus, the second logic 162 of the code dependent compensation unit 16B can output the code B according to the current p /B n And the previous output code bot p /bot n (which represents the switching of the back plane voltage of the digital-to-analog converter) to perform the logical operation. In this specification, the bottom plate refers to one plate switched to the reference voltage Vref or ground among the capacitors of the first/second digital-to-analog converter 11A/11B.
TABLE 1
FIGS. 4A-4D illustrate 4-bit simulation toThe compensation scheme of the digitizer 100 during sampling and conversion shows the kth switched first compensation capacitor C (of the code independent compensation unit 16A) C0,k And a second compensation capacitor C for the kth switching (of the ith code-dependent compensation unit 16B) Ck,i . In this example, a recurring asymptotic (SAR) controller 14 generates the first three bits B of the output code 1 B 2 B 3 Is "101". As previously described, the 4-bit analog-to-digital converter 100 uses up to three first compensation capacitors C C0,1 、C C0,2 、C C0,3 The method comprises the steps of carrying out a first treatment on the surface of the Using a second compensation capacitor C in the 2 nd switching C2,1 The method comprises the steps of carrying out a first treatment on the surface of the Using two second compensation capacitors C at the 3 rd switching C3,1 、C C3,2 。
During sampling (FIG. 4A), the outputs of the code independent compensation unit 16A and the code dependent compensation unit 16B are "0", so that all the first and second compensation capacitors are grounded. Next, as shown in fig. 4B, the first bit B of the generated output code is switched 1 st time during the conversion 1 Is "1", corresponding to the first compensation capacitor C C0,1 The output of the code independent compensation unit 16A is "1", thus electrically connected to the first compensation capacitor C C0,1 To supply voltage V DD . Similarly, as shown in FIG. 4C, the 2 nd switch during the transition generates the first bit B of the output code 1 B 2 Is "10", (since the output of the corresponding code independent compensation unit 16A is "1") and is thus electrically connected to the first compensation capacitor C C0,2 To supply voltage V DD And (due to the output of the corresponding code dependent compensation unit 16B being a "1") is thus electrically connected to a second compensation capacitor C C2,1 To supply voltage V DD . Finally, as shown in FIG. 4D, the 3 rd switch during the transition produces the first three bits B of the output code 1 B 2 B 3 Is "101", (since the output of the corresponding code independent compensation unit 16A is "1") and is thus electrically connected to the first compensation capacitor C C0,3 To supply voltage V DD And (due to the output of the corresponding code dependent compensation unit 16B being a "1") is thus electrically connected to a second compensation capacitor C C3,2 To supply voltage V DD 。
It is noted that not all of the code independent compensation units 16A and the code dependent compensation units 16B need be used. In one embodiment, only the mth and subsequent code independent compensation units 16A and 16B are used, but redundancy is added to tolerate errors caused by uncompensated (where m is a positive integer greater than 2, e.g., m=3).
In another embodiment, only the code independent compensation unit 16A and the code dependent compensation unit 16B of the first and second compensation capacitors of large capacitance values are used. In the present specification, the term large capacitance refers to a capacitance greater than a predetermined threshold value.
According to the above embodiment, the maximum number of the code independent compensation units 16A and the code dependent compensation units 16B only increases linearly with the switching number (or the number of bits) of the analog-to-digital converter 100. The number of compensation units increases exponentially with the number of switching (or bits) of the successive approximation analog-TO-digital converter (adc), for example, U.S. patent No. 10,236,903 entitled "charge compensation circuit and adc thereof (CHARGE COMPENSATION CIRCUIT AND ANALOG-TO-DIGITAL CONVERTER WITH THE SAME)".
The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.
Claims (20)
1. A reference ripple suppression circuit for a continuous asymptotic analog-to-digital converter, comprising:
a plurality of code dependent compensation units, each of the code dependent compensation units comprising a logic circuit and a compensation capacitor, a first plate of the compensation capacitor receiving a reference voltage to be compensated and a second plate of the compensation capacitor receiving an output of the logic circuit, wherein the logic circuit performs a logic operation on an output code of the sequential asymptotic analog-to-digital converter and at least one logic value representing a base plate voltage of the switching digital-to-analog converter;
the kth switching of the n-bit sequential asymptotic analog-to-digital converter uses (k-1) at most the code-dependent compensation units, k is a positive integer from 1 to (n-1), and n is a positive integer greater than 1.
2. The reference ripple suppression circuit of claim 1, wherein the output code comprises an output code pair comprising B p [k]And B is connected with n [k]And at least one logic value of the backplane voltage comprises a pair of board signals comprising bot p *[i]With bot n *[i]Wherein i is a positive integer from 1 to (k-1), B n [k]Is B p [k]Is the inverse logical value of (bot) p *[i]To represent the inverse logic value of the bottom plate voltage of the switched digital-to-analog converter, bot n *[i]Is bot p *[i]Is a logical value of the inverse of (a).
3. The reference ripple rejection circuit of claim 2, wherein the logic circuit performs logic operations during sampling and conversion according to the following truth table:
4. the reference ripple rejection circuit of claim 1, wherein only the mth and subsequent code dependent compensation units are used, but redundancy is added to tolerate errors caused by uncompensated, where m is a positive integer greater than 2.
5. The reference ripple rejection circuit of claim 1, wherein only the code dependent compensation unit having a capacitance greater than a predetermined threshold is used.
6. The reference ripple rejection circuit of claim 1, wherein the maximum number of the code dependent compensation units increases linearly with the number of switching of the successive approximation analog-to-digital converter.
7. A reference ripple suppression circuit for a continuous asymptotic analog-to-digital converter, comprising:
a plurality of code independent compensation units, each of the code independent compensation units comprising a first logic circuit and a first compensation capacitor, a first plate of the first compensation capacitor receiving a reference voltage to be compensated and a second plate of the first compensation capacitor receiving an output of the first logic circuit, wherein the first logic circuit performs a logic operation on an output code of the successive approximation analog-to-digital converter; and
A plurality of code dependent compensation units, each of the code dependent compensation units comprising a second logic circuit and a second compensation capacitor, a first plate of the second compensation capacitor receiving the reference voltage to be compensated and a second plate of the second compensation capacitor receiving an output of the second logic circuit, wherein the second logic circuit performs a logic operation on an output code of the successive approximation analog-to-digital converter and at least one logic value representing a bottom plate voltage of the switching digital-to-analog converter;
wherein n-bit successive approximation analog-to-digital converter uses (n-1) at most the code independent compensation units, and k-th switching of the successive approximation analog-to-digital converter uses (k-1) at most the code dependent compensation units, where n is a positive integer greater than 1 and k is a positive integer from 1 to (n-1).
8. The reference ripple rejection circuit of claim 7, wherein the output code comprises a differential signal pair for the first logic circuit to perform a logic operation.
9. The reference ripple rejection circuit of claim 8, wherein the logic performed by the first logic circuit comprises an OR logic.
10. The reference ripple suppression circuit of claim 7, wherein the output code comprises an output code pair comprising B p [k]And B is connected with n [k]And at least one logic value of the backplane voltage comprises a pair of board signals comprising bot p *[i]With bot n *[i]Wherein i is a positive integer from 1 to (k-1), B n [k]Is B p [k]Is the inverse logical value of (bot) p *[i]To represent the inverse logic value of the bottom plate voltage of the switched digital-to-analog converter, bot n *[i]Is bot p *[i]Is a logical value of the inverse of (a).
11. The reference ripple rejection circuit of claim 10, wherein the second logic circuit performs logic operations during sampling and during conversion according to the following truth table:
12. the reference ripple rejection circuit of claim 7, wherein only the mth and subsequent code independent compensation units and the code dependent compensation units are used, but redundancy is added to tolerate errors caused by uncompensated, wherein m is a positive integer greater than 2.
13. The reference ripple rejection circuit of claim 7, wherein only the code independent compensation unit and the code dependent compensation unit having capacitance values of the first and second compensation capacitors greater than a predetermined threshold are used.
14. The reference ripple rejection circuit of claim 7, wherein the maximum number of the code independent compensation units and the code dependent compensation units increases linearly with the number of switches of the successive approximation analog-to-digital converter.
15. A cyclic asymptotic analog-to-digital converter, comprising:
at least one switching digital-to-analog converter receiving an input signal to generate an output signal;
a comparator receiving the output signal;
a follow-up asymptotic controller for generating an output code according to the comparison output of the comparator;
a reference buffer for generating a reference voltage to the switching digital-to-analog converter; and
A reference ripple suppression circuit for suppressing a reference ripple of the reference voltage, the reference ripple suppression circuit comprising:
a plurality of code independent compensation units, each of the code independent compensation units comprising a first logic circuit and a first compensation capacitor, a first plate of the first compensation capacitor receiving the reference voltage and a second plate of the first compensation capacitor receiving an output of the first logic circuit, wherein the first logic circuit performs a logic operation on an output code of the successive approximation analog-to-digital converter; and
A plurality of code dependent compensation units, each of the code dependent compensation units comprising a second logic circuit and a second compensation capacitor, a first plate of the second compensation capacitor receiving the reference voltage and a second plate of the second compensation capacitor receiving an output of the second logic circuit, wherein the second logic circuit performs a logic operation on an output code of the successive approximation analog-to-digital converter and at least one logic value representing a bottom plate voltage of the switched digital-to-analog converter;
wherein n-bit successive approximation analog-to-digital converter uses (n-1) at most the code independent compensation units, and k-th switching of the successive approximation analog-to-digital converter uses (k-1) at most the code dependent compensation units, where n is a positive integer greater than 1 and k is a positive integer from 1 to (n-1).
16. The continuous-phase asymptotic analog-to-digital converter according to claim 15, wherein the output code includes differential signal pairs for the first logic circuit to perform logic operations.
17. The sequential asymptotic analog-to-digital converter according to claim 16, wherein the logic operations performed by the first logic circuitry include OR (OR) logic operations.
18. The continuous-phase asymptotic analog-to-digital converter according to claim 15, wherein the output code includes output code pairs including B p [k]And B is connected with n [k]And at least one logic value of the backplane voltage comprises a pair of board signals comprising bot p *[i]With bot n *[i]Wherein i is a positive integer from 1 to (k-1), B n [k]Is B p [k]Is the inverse logical value of (bot) p *[i]To represent the inverse logic value of the bottom plate voltage of the switched digital-to-analog converter, bot n *[i]Is bot p *[i]Is a logical value of the inverse of (a).
19. The continuous-phase asymptotic analog-to-digital converter according to claim 18, wherein the second logic circuitry performs logic operations during sampling and during conversion according to the following truth table:
20. the continuous-asymptotic analog-to-digital converter according to claim 15, wherein only the mth and subsequent code independent compensation units and the code dependent compensation units are used, but redundancy is added to tolerate errors caused by uncompensated, where m is a positive integer greater than 2.
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