CN115410904A - 一种通过界面技术改善铁电mos电容性能的方法 - Google Patents

一种通过界面技术改善铁电mos电容性能的方法 Download PDF

Info

Publication number
CN115410904A
CN115410904A CN202211112662.9A CN202211112662A CN115410904A CN 115410904 A CN115410904 A CN 115410904A CN 202211112662 A CN202211112662 A CN 202211112662A CN 115410904 A CN115410904 A CN 115410904A
Authority
CN
China
Prior art keywords
layer
ferroelectric
zro
hafnium
improving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211112662.9A
Other languages
English (en)
Inventor
陈琳
李振海
孟佳琳
王天宇
孙清清
张卫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fudan University
Original Assignee
Fudan University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fudan University filed Critical Fudan University
Priority to CN202211112662.9A priority Critical patent/CN115410904A/zh
Publication of CN115410904A publication Critical patent/CN115410904A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40Oxides
    • C23C16/405Oxides of refractory metals or yttrium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02189Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing zirconium, e.g. ZrO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明公开一种通过界面技术改善铁电MOS电容性能的方法。该方法包括以下步骤:在Si衬底上形成TiN底电极;在所述TiN底电极上形成ZrO2层;在所述ZrO2层上沉积铪基铁电层;在所述铪基铁电层上形成ZrO2层;在所述ZrO2层上形成TiN顶电极;在氮气氛围下进行快速热退火处理。

Description

一种通过界面技术改善铁电MOS电容性能的方法
技术领域
本发明涉及半导体技术领域,具体涉及一种通过界面技术改善铁电MOS电容性能的方法。
背景技术
铁电材料具有剩余极化强度且极化方向可以在外加电场的作用下发生切换,这使得铁电材料成为未来高密度和低功耗器件(例如铁电随机存储器、铁电场效应晶体管和铁电结型晶体管)材料的有利竞争者之一。然而,传统的铁电材料例如钙钛矿、铌酸锂和PVDF等,但传统铁电材料无法与CMOS工艺兼容并且会带来H毒化问题制约了未来的发展。2011年铪基铁电材料的出现重新引起了人们对铁电材料的关注,逐渐成为研究热点。
然而,铪基铁电薄膜中的相型为混合相,并不是单一相结构,这使铪基铁电薄膜的铁电性能较弱,有待进一步的提高。现在提升薄膜的铁电性能通常用的方法是元素的掺杂和改变氧化的条件。但是,这些方法将改变薄膜中氧空位,在提升铁电相比例的同时,也增加了器件的印记效用。这使铪基铁电的发展陷入了两难的境地。
发明内容
本发明公开一种通过界面技术改善铁电MOS电容性能的方法,包括以下步骤:在Si衬底上形成TiN底电极;在所述TiN底电极上形成ZrO2层;在所述ZrO2层上沉积铪基铁电层;在所述铪基铁电层上形成ZrO2层;在所述ZrO2层上形成TiN顶电极;在氮气氛围下进行快速热退火处理。
本发明的通过界面技术改善铁电MOS电容性能的方法中,优选为,所述ZrO2层的厚度为2nm~4nm。
本发明的通过界面技术改善铁电MOS电容性能的方法中,优选为,所述铪基铁电层的掺杂元素为Si、Al、Zr或La。
本发明的通过界面技术改善铁电MOS电容性能的方法中,优选为,所述快速热退火的温度为500℃~900℃,时间为30s~45s。
本发明的通过界面技术改善铁电MOS电容性能的方法中,优选为,采用等离子增强原子层沉积方法形成铪基铁电层。
有益效果:
采用元素掺杂和形成ZrO2/铪基铁电层/ZrO2叠层结构的方式,对铁电薄膜施加内外应力从而提升薄膜铁电相的比例增强器件的铁电性能。
采用原子层淀积技术生长介质薄膜,可以精确地控制薄膜的厚度,得到高保形性高质量的介质薄膜。
附图说明
图1是通过界面技术改善铁电MOS电容性能的方法的流程图。
图2~图6是通过界面技术改善铁电MOS电容性能的方法各阶段的结构示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,应当理解,此处所描述的具体实施例仅用以解释本发明,并不用于限定本发明。所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例,都属于本发明保护的范围。
在本发明的描述中,需要说明的是,术语“上”、“下”、“垂直”“水平”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本发明和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本发明的限制。此外,术语“第一”、“第二”仅用于描述目的,而不能理解为指示或暗示相对重要性。
此外,在下文中描述了本发明的许多特定的细节,例如器件的结构、材料、尺寸、处理工艺和技术,以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样,可以不按照这些特定的细节来实现本发明。除非在下文中特别指出,器件中的各个部分可以由本领域的技术人员公知的材料构成,或者可以采用将来开发的具有类似功能的材料。
图1是通过界面技术改善铁电MOS电容性能的方法的流程图。如图1所示,通过界面技术改善铁电MOS电容性能的方法包括以下步骤:
步骤S1,采用传统的RCA清洗工艺清洗Si衬底100,并用N2吹干。
步骤S2,采用物理气相沉积方法(PVD)在Si衬底100上溅射TiN作为底电极101,厚度优选为30nm~60nm,如图2所示。
步骤S3,使用等离子增强原子层沉积方法(PEALD)在底电极101上沉积2nm~4nm厚的ZrO2层102,如图3所示。
步骤S4,使用PEALD方法在ZrO2层102上沉积10nm~12nm厚的铪基铁电层103,如图4所示。铪基铁电层为掺杂HfO2,掺杂元素如Si、Al、Zr、La等。由于ZrO2的相型为正交相,在退火过程中铪基铁电层的晶粒会沿着ZrO2的晶相进行生长,且ZrO2/铪基铁电层界面应力能够校正铪基铁电层的生长的方向,提升铁电相比例。界面处应力的大小主要与ZrO2的厚度有关,当ZrO2的厚度超过2nm时ZrO2为正交相,可以为氧化铪薄膜提供较大的应力从而使薄膜沿着规定的方向生长,但是当ZrO2的厚度超过4nm后,ZrO2/HfO2界面处的应力将不会发生明显的变化,所以沉积ZrO2的厚度应控制在2~4nm的范围内。
步骤S5,使用等离子增强原子层沉积方法在铪基铁电层104上沉积2nm~4nm厚的ZrO2层105,如图5所示。
步骤S6,采用剥离法(lift-off)或者硬掩膜(hard mask),在铪基铁电层104上使用PVD溅射30nm~60nm厚的TiN形成顶电极105,如图6所示。
步骤S7,在氮气氛围下以500℃~900℃进行30s~45s的快速热退火处理。
本发明利用PEALD在沉积氧化铪薄膜时进行元素(Zr、Al、La和Si等)的掺杂改变薄膜内部键型,且在铪基铁电层的两侧沉积ZrO2层,通过上述方式对铁电薄膜施加内外应力来提高铁电薄膜中铁电相所占的比例从而提升器件的铁电特性。
以上所述,仅为本发明的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到的变化或替换,都应涵盖在本发明的保护范围之内。

Claims (5)

1.一种通过界面技术改善铁电MOS电容性能的方法,其特征在于,
包括以下步骤:
在Si衬底上形成TiN底电极;
在所述TiN底电极上形成ZrO2层;
在所述ZrO2层上沉积铪基铁电层;
在所述铪基铁电层上形成ZrO2层;
在所述ZrO2层上形成TiN顶电极;
在氮气氛围下进行快速热退火处理。
2.根据权利要求1所述的通过界面技术改善铁电MOS电容性能的方法,其特征在于,
所述ZrO2层的厚度为2nm~4nm。
3.根据权利要求1所述的通过界面技术改善铁电MOS电容性能的方法,其特征在于,
所述铪基铁电层的掺杂元素为Si、Al、Zr或La。
4.根据权利要求1所述的通过界面技术改善铁电MOS电容性能的方法,其特征在于,
所述快速热退火的温度为500℃~900℃,时间为30s~45s。
5.根据权利要求1所述的通过界面技术改善铁电MOS电容性能的方法,其特征在于,
采用等离子增强原子层沉积方法形成铪基铁电层。
CN202211112662.9A 2022-09-14 2022-09-14 一种通过界面技术改善铁电mos电容性能的方法 Pending CN115410904A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211112662.9A CN115410904A (zh) 2022-09-14 2022-09-14 一种通过界面技术改善铁电mos电容性能的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211112662.9A CN115410904A (zh) 2022-09-14 2022-09-14 一种通过界面技术改善铁电mos电容性能的方法

Publications (1)

Publication Number Publication Date
CN115410904A true CN115410904A (zh) 2022-11-29

Family

ID=84166187

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211112662.9A Pending CN115410904A (zh) 2022-09-14 2022-09-14 一种通过界面技术改善铁电mos电容性能的方法

Country Status (1)

Country Link
CN (1) CN115410904A (zh)

Similar Documents

Publication Publication Date Title
CN106463513B (zh) 铁电存储器单元及形成半导体结构的方法
US8546236B2 (en) High performance dielectric stack for DRAM capacitor
US8765570B2 (en) Manufacturable high-k DRAM MIM capacitor structure
US8847397B2 (en) High work function, manufacturable top electrode
JP4465413B1 (ja) 誘電体膜、誘電体膜の製造方法、半導体装置、および、記録媒体
US8541868B2 (en) Top electrode templating for DRAM capacitor
Jung et al. A review on morphotropic phase boundary in fluorite-structure hafnia towards DRAM technology
CN113948520A (zh) 一种氧化铪基铁电电容及其制备方法
US20160099304A1 (en) MoNx as a Top Electrode for TiOx Based DRAM Applications
KR100378276B1 (ko) 절연 재료, 절연막 피복 기판, 그 제조 방법 및 박막 소자
US8652927B2 (en) Integration of non-noble DRAM electrode
US9318546B1 (en) Doped electrode for DRAM capacitor stack
US20130071986A1 (en) Partial etch of dram electrode
CN115410904A (zh) 一种通过界面技术改善铁电mos电容性能的方法
CN113363384B (zh) 一种HfO2基铁电隧道结器件及其制备方法
US8853049B2 (en) Single-sided non-noble metal electrode hybrid MIM stack for DRAM devices
CN115410903A (zh) 一种通过插层技术优化铁电mos电容性能的方法
CN114988470B (zh) 一种氧化铪基铁电薄膜、电容结构、晶体管及制备方法
CN115410902A (zh) 一种改善铁电mos电容性能的方法
CN112259552A (zh) 一种铁电场效应晶体管存储器及其制备方法
CN115440595A (zh) 一种基于ZrO2反铁电性的多比特存储场效应晶体管制备方法
TW202405912A (zh) 半導體元件的製造方法
CN117729776A (zh) 一种高耐久存算一体器件及其制备方法
CN116075210A (zh) 一种铁电异质结阻变存储器的制备方法及其应用
JPH06329497A (ja) 結晶性薄膜の成形法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination