CN115360227A

CN115360227A - Array substrate and display device

Info

Publication number: CN115360227A
Application number: CN202211084966.9A
Authority: CN
Inventors: 高娅娜; 黄高军
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2022-09-06
Filing date: 2022-09-06
Publication date: 2022-11-18

Abstract

The embodiment of the application provides an array substrate and a display device, wherein the array substrate comprises a transparent hole, a display area and a non-display area, the display area surrounds the transparent hole, the non-display area comprises a first frame area and a second frame area, the first frame area, the display area and the second frame area are sequentially arranged along a first direction, the second frame area is used for being connected with a touch chip or a flexible circuit board, and the first frame area is provided with a load module; the display area includes: a plurality of target scanning signal lines electrically connected to the sub-pixels in the display region for supplying scanning signals to the sub-pixels; a plurality of data signal lines and a plurality of dummy data signal lines; the display area comprises a first area and a second area, and the first area is divided into at least two sub-areas by the transparent holes along the second direction; the target scanning signal line in the first area is electrically connected with the load module in the first frame area through a virtual data signal line. The embodiment of the application can improve the display effect.

Description

Array substrate and display device

Technical Field

The application belongs to the technical field of display, and particularly relates to an array substrate and a display device.

Background

With the development of display technology, the functions of display devices are more and more complete. In order to provide electronic components such as a fingerprint recognition, an earpiece, a light sensor and/or a camera on the display surface of the display device, these components may be placed by providing transparent holes in the array substrate.

Fig. 1 is a schematic structural diagram of an array substrate. As shown in fig. 1, the display region of the array substrate may include a first region A1 and a second region A2. Wherein the first area A1 is divided into two sub-areas by the transparent hole k1. Through research by the inventor of the present application, it is found that when the display device displays, the display effect of the first area A1 and the display effect of the second area A2 are different, which results in poor display effect of the display device as a whole.

Disclosure of Invention

The embodiment of the application provides an array substrate and a display device, and the problem that the difference of display effects between a first region corresponding to a transparent hole and other display regions is large can be solved.

In a first aspect, an embodiment of the present application provides an array substrate, where the array substrate includes a transparent hole, a display area and a non-display area, the display area surrounds the transparent hole, the non-display area includes a first frame area and a second frame area, the first frame area, the display area and the second frame area are sequentially arranged along a first direction, the second frame area is used for connecting a touch chip or a flexible circuit board, and the first frame area is provided with a load module; the display area includes: a plurality of target scanning signal lines extending along the second direction and arranged at intervals along the first direction, wherein the target scanning signal lines are electrically connected with the sub-pixels in the display area and used for providing scanning signals for the sub-pixels, and the first direction is crossed with the second direction; a plurality of data signal lines and a plurality of dummy data signal lines extending along a first direction and arranged at intervals along a second direction; the display area comprises a first area and a second area, and the first area is divided into at least two sub-areas by the transparent holes along the second direction; the target scanning signal line in the first area is electrically connected with the load module in the first frame area through the virtual data signal line.

In a second aspect, embodiments of the present application provide a display device, which includes the array substrate provided in the first aspect.

According to the array substrate and the display device, on one hand, the load compensation of the target scanning signal line in the first area can be realized by electrically connecting the additional load module with the target scanning signal line in the first area, so that the load of the target scanning signal line in the first area is the same as, similar to or in accordance with a certain gradual change rule with the load of the target scanning signal line in the second area, the display effect difference between the first area and the second area is improved, and the display effect is improved; on the other hand, the virtual data signal lines in the display area are multiplexed into the connecting wires between the load module and the target scanning signal lines in the first area, so that the number of wires in the array substrate can be reduced, and the number of wires in the non-display area can be reduced because the virtual data signal lines are positioned in the display area, namely the connecting wires between the load module and the target scanning signal lines in the first area do not need to be wound to the non-display area, thereby being beneficial to reducing the size of a frame and realizing a narrow frame; in another aspect, the load module is disposed in the first frame region closest to the transparent hole, so that the length of the connection trace between the load module and the target scan signal line in the first region can be reduced, the wiring space can be saved, and the production cost can be reduced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic structural diagram of an array substrate;

FIG. 2 is a partial circuit diagram of the array substrate;

FIG. 3 is a circuit diagram of a pixel circuit;

fig. 4 is a schematic partial cross-sectional view of a display panel on which an array substrate according to an embodiment of the present disclosure is disposed;

fig. 5 is a schematic top view of an array substrate according to an embodiment of the present disclosure;

fig. 6 is a schematic partial top view of an array substrate according to an embodiment of the present disclosure;

fig. 7 is a schematic partial cross-sectional view of an array substrate according to an embodiment of the present application;

fig. 8 is another schematic partial cross-sectional view of an array substrate according to an embodiment of the present disclosure;

fig. 9 is a schematic partial top view of an array substrate according to an embodiment of the present disclosure;

fig. 10 is a schematic top view of an array substrate according to an embodiment of the present application;

FIG. 11 is a schematic partial circuit diagram of an array substrate according to an embodiment of the present disclosure;

fig. 12 is a schematic partial circuit diagram of an array substrate according to an embodiment of the present disclosure;

fig. 13 is a schematic partial circuit diagram of an array substrate according to an embodiment of the present disclosure;

fig. 14 is a schematic partial circuit diagram of an array substrate according to an embodiment of the present disclosure;

fig. 15A is a circuit diagram of a pixel circuit in an array substrate according to an embodiment of the present disclosure;

FIG. 15B is a timing diagram of the corresponding one embodiment of FIG. 15A;

fig. 16 is a schematic partial circuit diagram of an array substrate according to an embodiment of the present disclosure;

fig. 17 is a schematic partial circuit diagram of an array substrate according to an embodiment of the present disclosure;

fig. 18 is a schematic view of another partial structure of an array substrate according to an embodiment of the present disclosure;

fig. 19 is a schematic view of another partial structure of an array substrate according to an embodiment of the present disclosure;

fig. 20 is a schematic view of another partial structure of an array substrate according to an embodiment of the present disclosure;

fig. 21 is a schematic view of another partial structure of an array substrate according to an embodiment of the present disclosure;

fig. 22 is a schematic partial cross-sectional view of an array substrate according to an embodiment of the present application;

fig. 23 is a schematic partial plan view of an array substrate according to an embodiment of the present application;

fig. 24 is another partial schematic plan view of an array substrate according to an embodiment of the present disclosure;

fig. 25 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.

Detailed Description

Features of various aspects and exemplary embodiments of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative only and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising 8230; \8230;" comprises 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

It should be understood that the term "and/or" as used herein is merely a relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B, may represent: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

Note that the transistor in the embodiment of the present application may be an N-type transistor or a P-type transistor, except where a type of the transistor is specifically described. For an N-type transistor, the on level is high and the off level is low. That is, when the gate of the N-type transistor is at a high level, the first pole and the second pole of the N-type transistor are turned on, and when the gate of the N-type transistor is at a low level, the first pole and the second pole of the N-type transistor are turned off. For a P-type transistor, the on level is low and the off level is high. That is, when the gate of the P-type transistor is at a low level, the first pole and the second pole of the P-type transistor are turned on, and when the gate of the P-type transistor is at a high level, the first pole and the second pole of the P-type transistor are turned off. In a specific implementation, the gate of each transistor is used as its control electrode, and according to the signal of the gate of each transistor and its type, the first electrode of each transistor can be used as its source and the second electrode as its drain, or the first electrode of each transistor can be used as its drain and the second electrode as its source, which are not distinguished herein.

In the embodiments of the present application, the term "electrically connected" may mean that two components are directly electrically connected, or may mean that two components are electrically connected to each other via one or more other components.

In the embodiments of the present application, the first node is defined only for convenience of describing a circuit structure, and the first node is not an actual circuit unit.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application cover the modifications and variations of this application provided they come within the scope of the corresponding claims (the claimed subject matter) and their equivalents. It should be noted that the embodiments provided in the embodiments of the present application can be combined with each other without contradiction.

Before explaining the technical solutions provided in the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

as described above, the inventors of the present application have found that the display effect of the first region corresponding to the transparent hole is greatly different from that of the other display region in the related art.

In order to solve the above technical problems, the inventors of the present application first conducted research and analysis on the root causes leading to the above technical problems, and the specific research and analysis processes are as follows:

fig. 2 is a partial circuit diagram of the array substrate. As shown in fig. 2, it was found by the inventors of the present application that, since the pixel circuits 10' are not provided in the transparent hole k1, or the sub-pixels (not shown in fig. 2) are not provided in the transparent hole k1, the number of the pixel circuits 10' to which the scanning signal lines S in the first region A1 are connected is smaller than the number of the pixel circuits 10' to which the scanning signal lines S in the second region A2 are connected, which in turn causes the load of the scanning signal lines S in the first region A1 to be smaller than the load of the scanning signal lines S in the second region A2, i.e., the load of the scanning signal lines SN in the first region A1 is greatly different from the load of the scanning signal lines S in the second region A2. As a result, the display effect of the first area A1 is different from the display effect of the second area A2, and the overall display effect is poor.

Fig. 3 is a circuit diagram of a pixel circuit. As shown in fig. 2 and fig. 3, for example, taking the scanning signal line S as the scanning signal line for controlling the on/off of the data writing transistor T1', since the load of the scanning signal line S in the first area A1 is smaller than the load of the scanning signal line S in the second area A2, the delay of the scanning signal output by the scanning signal line S in the first area A1 is smaller than the delay of the scanning signal output by the scanning signal line S in the second area A2. Thus, the on-time of the data writing transistor T1 'in the first area A1 is longer than the on-time of the data writing transistor T1' in the second area A2, that is, the time for writing the data signal in the first area A1 is more sufficient. In some cases where the refresh rate is high, since the on-time of the data writing transistor T1 'is itself short, the time for writing the data signal in the second area A2 may be insufficient, so that the potential of the gate of the driving transistor T0' (i.e. the first node N1) may not reach the expected potential. Since the turn-on time of the data writing transistor T1' in the first area A1 is longer than the turn-on time of the data writing transistor T1' in the second area A2, the gate potential of the driving transistor T0' in the first area A1 can reach the expected potential well, or the difference between the expected potential and the gate potential is small. As a result, the display luminance of the first area A1 is different from the display luminance of the second area A2, and the overall display effect of the display device is poor.

In view of the above research by the inventors, the embodiments of the present application provide an array substrate and a display device, which can solve the technical problem of poor display effect caused by a large difference between the load of the scan signal line in the first region and the load of the scan signal line in the second region in the related art.

The technical idea of the embodiment of the application is as follows: the load module is additionally arranged in the first frame area closest to the transparent hole, and the target scanning signal line in the first area is electrically connected with the load module through the virtual data signal line positioned in the display area; on the other hand, the virtual data signal lines in the display area are multiplexed into the connecting wires between the load module and the target scanning signal lines in the first area, so that the number of wires in the array substrate can be reduced, and the number of wires in the non-display area can be reduced because the virtual data signal lines are positioned in the display area, namely the connecting wires between the load module and the target scanning signal lines in the first area do not need to be wound to the non-display area, thereby being beneficial to reducing the size of a frame and realizing a narrow frame; in another aspect, the load module is disposed in the first frame region closest to the transparent hole, so that the length of the connection trace between the load module and the target scan signal line in the first region can be reduced, the wiring space can be saved, and the production cost can be reduced.

First, the array substrate provided in the embodiments of the present application will be described.

Fig. 4 is a schematic partial cross-sectional view of a display panel on which an array substrate according to an embodiment of the present disclosure is disposed. As shown in fig. 4, the display panel may include an array substrate 40 provided in the embodiment of the present disclosure and a light emitting element D, and the light emitting element D may be disposed on the array substrate 40 and electrically connected to a pixel circuit in the array substrate 40. That is, the array substrate 40 may be a part of a display panel for providing a pixel circuit for driving the light emitting element D to emit light. Exemplarily, the light emitting element D may include a first electrode RE, a second electrode SE, and a light emitting layer OM between the first electrode RE and the second electrode SE. Here, the first electrode RE of the light emitting element D may be an anode of the light emitting element D, and the second electrode SE of the light emitting element D may be a cathode of the light emitting element D.

The film structure of the array substrate 40 in fig. 4 is only an illustration and is not a limitation to the embodiments of the present application.

Fig. 5 is a schematic top view of an array substrate according to an embodiment of the present disclosure. As shown in fig. 5, the array substrate 40 provided in the embodiment of the present application includes a transparent hole k1, a display area AA, and a non-display area NA. The display area AA surrounds the transparent hole k1. The non-display area NA may include a first bezel area NA1 and a second bezel area NA2. Along the first direction Y, the first frame area NA1, the display area AA, and the second frame area NA2 are sequentially arranged. For example, in fig. 5, the first frame area NA1 may be an upper frame, and the second frame area NA2 may be a lower frame. The second frame area NA2 may be used to connect a driving chip (not shown) or a Flexible Printed Circuit (FPC). The driving chip may provide a driving signal to the array substrate 40. The first frame area NA1 is provided with a load module 50. The load module 50 has a certain resistance or capacitance value, and can be used for compensating the load of the target scan signal line.

With continued reference to fig. 5, the display area AA may include a plurality of target scan signal lines SN extending along the second direction X and arranged at intervals along the first direction Y, the target scan signal lines SN may be electrically connected to sub-pixels (not shown) in the display area AA, and the target scan signal lines SN may be used to provide scan signals to the sub-pixels. It is to be understood that the sub-pixel may include a pixel circuit and a light emitting element electrically connected to the pixel circuit. The target scan signal line SN may be electrically connected to a pixel circuit in the display area AA, for supplying a scan signal to the pixel circuit.

The first direction Y may cross the second direction X. For example, the first direction Y may be perpendicular to the second direction X. For example, the first direction Y may be a column direction of the array substrate 40, and the second direction X may be a row direction of the array substrate 40.

The display area AA may further include a plurality of data signal lines data and a plurality of dummy data signal lines data' extending in the first direction Y and arranged at intervals in the second direction X. In some examples, for example, the data signal line data located in the edge region of the array substrate 40 may be electrically connected to a bonding pad (not shown) through the dummy data signal line data' located in the central region of the array substrate 40, and the bonding pad is further electrically connected to the driving chip or the FPC, so that the area occupied by the fanout line in the second frame region NA2 is reduced, which is beneficial to implementing a narrow frame. Specific examples will be described in detail below, without undue experimentation.

With continued reference to fig. 5, the display area AA may include a first area A1 and a second area A2. Along the second direction X, the first area A1 may be spaced by the transparent hole k1 into at least two sub-areas a. Here, for example, the width w of the first region A1 in the first direction Y may be equal to the width w of the transparent hole k1 in the first direction Y. For convenience of explanation, for example, the other display areas except for the first area A1 in the display area AA are referred to as a second area A2.

The target scan signal line SN in the first area A1 may be electrically connected to the load module 50 in the first bezel area NA1 through the dummy data signal line data', so as to compensate for a load of the target scan signal line SN in the first area A1.

On one hand, the array substrate 40 of the embodiment of the application, on the one hand, can realize load compensation for the target scanning signal line in the first region by additionally arranging the load module to be electrically connected with the target scanning signal line in the first region, so that the load of the target scanning signal line in the first region is the same as, similar to or in accordance with a certain gradual change rule with the load of the target scanning signal line in the second region, thereby improving the display effect difference between the first region and the second region and improving the display effect; on the other hand, the virtual data signal lines in the display area are multiplexed into the connecting wires between the load module and the target scanning signal lines in the first area, so that the number of wires in the array substrate can be reduced, and the number of wires in the non-display area can be reduced because the virtual data signal lines are positioned in the display area, namely the connecting wires between the load module and the target scanning signal lines in the first area do not need to be wound to the non-display area, thereby being beneficial to reducing the size of a frame and realizing a narrow frame; in another aspect, the load module is disposed in the first frame region closest to the transparent hole, so that the routing length of the connection routing between the load module and the target scan signal line in the first region can be reduced, the routing space can be saved, and the production cost can be reduced.

Fig. 6 is a schematic partial top view of an array substrate according to an embodiment of the present disclosure. As shown in fig. 6, according to some embodiments of the present application, optionally, the dummy data signal line data' may include at least two broken line segments L, where the line segment L closest to the first bezel area NA1 is the first line segment L1. The target scan signal line SN in the first area A1 may be electrically connected to the load module 50 in the first frame area NA1 through the first routing segment L1. That is, the target scan signal line SN in the first area A1 may be electrically connected to the load module 50 in the first frame area NA1 through the trace segment L closest to the first frame area NA 1.

In this way, by dividing the dummy data signal line data ' into at least two line segments L, only one line segment L in the dummy data signal line data ' is used to connect the target scan signal line SN and the load module 50, so that the normal use of the other line segments L in the dummy data signal line data ' is not affected. For example, the other trace segments L except the first trace segment L1 in the dummy data signal line data' may be electrically connected to the data signal line data for transmitting data signals. For another example, the other trace segments L except the first trace segment L1 in the dummy data signal line data' may be electrically connected to the first power voltage signal line PVDD (not shown) and/or the second power voltage signal line PVEE (not shown), so that the first power voltage signal line PVDD and/or the second power voltage signal line PVEE form a mesh trace to reduce the IR-drop of the first power voltage signal line PVDD and/or the second power voltage signal line PVEE.

Further research by the inventor of the present application finds that when a breakpoint exists in the dummy data signal line data ', a bright point appears in a picture when the display panel displays due to different degrees of reflected light from the breakpoint position and the non-breakpoint position of the dummy data signal line data', which may affect the display effect.

In view of this, the present application considers that the breakpoint of the dummy data signal line data 'is disposed right below the anode of the light emitting element, and the breakpoint of the dummy data signal line data' is shielded by the anode of the light emitting element, so as to avoid a bright point appearing in a display image during displaying, and improve a display effect.

Fig. 7 is a schematic partial cross-sectional view of an array substrate according to an embodiment of the present disclosure. As shown in fig. 7, according to some embodiments of the present application, optionally, the array substrate 40 is provided with a light emitting element D, and the dummy data signal line data' may be located at a different film layer from the anode RE of the light emitting element D. Along the direction Z perpendicular to the plane of the array substrate, the breakpoint position p1 of the dummy data signal line data 'may be located within the orthographic projection of the anode RE of the light emitting element D on the array substrate 40, i.e., the breakpoint position p1 of the dummy data signal line data' may be located directly below the anode RE of the light emitting element D.

Therefore, the anode RE of the light emitting device D shields the breakpoint p1 of the dummy data signal line data', so as to prevent bright spots from appearing in the display image and improve the display effect.

With continued reference to fig. 7, in some specific examples, optionally, the array substrate 40 includes a substrate 01, a first metal layer M1, a second metal layer M2, a third metal layer M3, a fourth metal layer M4, and a fifth metal layer M5, which are stacked.

It is easily understood that electronic devices such as a thin film transistor and a capacitor are disposed in the array substrate 40. In some specific embodiments, for example, at least a portion of the gate electrode of the thin film transistor and at least a portion of the first plate of the capacitor may be located in the first metal layer M1, at least a portion of the second plate of the capacitor may be located in the second metal layer M2, and at least a portion of the source electrode and the drain electrode of the thin film transistor may be located in the third metal layer M3.

Illustratively, the dummy data signal line data' may be located at the fifth metal layer M5, for example.

Fig. 8 is another schematic partial cross-sectional view of an array substrate according to an embodiment of the present disclosure. As shown in fig. 8, according to other embodiments of the present disclosure, the array substrate 40 of the present disclosure may alternatively use Low Temperature Polycrystalline Oxide (LTPO) technology. That is, the pixel circuit of the array substrate 40 may include both the low temperature polysilicon thin film transistor T1 'and the oxide thin film transistor T2'.

Specifically, unlike the embodiment shown in fig. 7, the array substrate 40 may further include a sixth metal layer M6, and the sixth metal layer M6 may be located between the second metal layer M2 and the third metal layer M3 along the direction Z perpendicular to the plane of the array substrate. The oxide thin film transistor T2' may be a double-gate transistor, the first gate g1 of the oxide thin film transistor T2' may be located on the first metal layer M1 or the second metal layer M2, and the second gate g2 of the oxide thin film transistor T2' may be located on the sixth metal layer M6.

Fig. 9 is a schematic partial top view of an array substrate according to an embodiment of the present disclosure. As shown in fig. 9, it is considered that the connection position p2 of some target scan signal lines SN and the first wire segment L1 may not be right under the anode RE of the light emitting element, and if the dummy data signal line data 'is disconnected at a position adjacent to the connection position p2, the breakpoint position p1 of the dummy data signal line data' may not be right under the anode RE of the light emitting element. For this reason, for example, for any ith first route segment L1, the ith first route segment L1 may extend to the position where the anode RE of the light emitting element is within the orthographic projection of the array substrate, and then be disconnected from other route segments L on the same straight line. Wherein i is a positive integer.

Thus, even if the connection position p2 of the target scanning signal line SN and the first trace line L1 is not under the anode RE of the light-emitting element, the breakpoint position p1 of the dummy data signal line data' can be ensured to be under the anode RE of the light-emitting element, so that bright spots are prevented from appearing in the display screen during display, and the display effect is improved.

As described above, the data signal line data located in the edge region of the array substrate 40 may be electrically connected to the bonding pad (not shown in the figure) through the dummy data signal line data' located in the central region of the array substrate 40, and the bonding pad is electrically connected to the driving chip or the FPC, so that the area of the second bezel region NA2 occupied by the fanout line is reduced, which is beneficial to realizing a narrow bezel. For ease of understanding, the following description is made in detail with reference to fig. 10.

Fig. 10 is a schematic top view of an array substrate according to an embodiment of the present disclosure. As shown in fig. 10, according to some embodiments of the present application, optionally, the array substrate 40 further includes a first connection line X1 extending along the second direction X. The display area AA may include a first edge area B1, a central area Q, and a second edge area B2 sequentially arranged along the second direction X. The data signal lines data in the first and second edge regions B1 and B2 may be electrically connected to the dummy data signal line data 'located in the central region Q through the first connection line X1, and the dummy data signal line data' of the central region Q may be electrically connected to the driving chip or the FPC through the bonding pad in the second frame region NA2 to receive the data signal.

In this way, it is not necessary to provide a fanout line electrically connected to the data signal lines data in the first edge region B1 and the second edge region B2, or to move the fanout line electrically connected to the data signal lines data in the first edge region B1 and the second edge region B2 to the center of the array substrate 40, so as to reduce the area of the second frame region NA2 occupied by the fanout line, which is beneficial to realizing a narrow frame.

It should be noted that, in some examples, the data signal line data and the dummy data signal line data' may be located on the same film layer, and the first connection line X1 is located on another film layer. In other examples, the dummy data signal line data' may be located on the same film as the first connection line X1, and the data signal line data may be located on another film. In still other examples, the data signal line data may be located on the same film as the first connection line X1, and the dummy data signal line data' may be located on another film, which is not limited in this embodiment of the present invention.

With continued reference to fig. 10, according to some embodiments of the present application, optionally, at least a portion of the trace segment L of the dummy data signal line data' that is not connected to the target scan signal line SN and the data signal line data is referred to as a target trace segment Ln, and the target trace segment Ln may be electrically connected to a constant voltage signal line (not shown in the figure). The target line segment Ln may be electrically connected to the constant voltage signal line through a via. Illustratively, the constant voltage signal lines include, for example, but are not limited to, a first power supply voltage signal line PVDD and/or a second power supply voltage signal line PVEE.

Therefore, on one hand, the target routing segment Ln is electrically connected with the constant voltage signal line, so that the target routing segment Ln can be ensured to maintain stable potential, and the stability of the circuit in the array substrate is ensured; on the other hand, the constant voltage signal lines can be made to constitute mesh wiring to reduce the IR-drop of the constant voltage signal lines.

Fig. 11 is a schematic partial circuit diagram of an array substrate according to an embodiment of the present disclosure. As shown in fig. 11, according to some embodiments of the present application, optionally, one sub-region a may include m1 entry mark scan signal lines SN, the m1 entry mark scan signal lines SN may be electrically connected to the m1 dummy data signal lines data' in a one-to-one correspondence, and m1 is a positive integer. Although m1=6 is illustrated as an example in fig. 11, it is understood that m1 may be a value other than 6, and this is not limited in the embodiment of the present application.

Item 1 st to item 1 st target scan signal lines SN1 to SN _m1 Sequentially arranged along a first direction Y, m1 virtual data signal lines data' sequentially arranged along a second direction X, and the m1 th virtual data signal lines data _m1 ' data line at 1 st virtual data line ₁ ' is close to one side of the transparent hole k1.

Item 1 st to item 1 st target scan signal lines SN1 to SN _m1 Can be sequentially connected with the m1 th virtual data signal line data _m1 ' to 1 st dummy data signal line data ₁ ' electrically connected in a one-to-one correspondence. That is, the 1 st entry mark scanning signal line SN1 and the m1 st dummy data signal line data _m1 ' electric connection ' \ 8230; \ 8230;'m 1 th item scan signal line SN _m1 Can be connected with the 1 st virtual data signal line data ₁ ' electrically connected.

In this way, the 1 st to m1 st entry mark scanning signal lines SN1 to SN in the sub-area a _m1 The data lines are electrically connected with the virtual data signal lines data' in sequence according to the arrangement sequence, and the connection mode accords with the wiring rule of the display area, so that the wiring is convenient. In addition, when the target scanning signal line SN is disconnected with the virtual data signal line data', the target scanning signal line SN is convenient to find and repair.

Fig. 12 is a schematic partial circuit diagram of an array substrate according to an embodiment of the present disclosure. As shown in fig. 12, according to other embodiments of the present application, optionally, one sub-region a may include m1 entry mark scan signal lines SN, the m1 entry mark scan signal lines SN may be electrically connected to the m1 dummy data signal lines data' in a one-to-one correspondence, and m1 is a positive integer. Although m1=6 is illustrated as an example in fig. 12, it is understood that m1 may be a value other than 6, and this is not limited in the embodiment of the present application.

Item 1 st to item 1 st target scan signal lines SN1 to SN _m1 The m1 virtual data signal lines data' are sequentially arranged along the second direction X. Unlike the embodiment shown in FIG. 11, the 1 st dummy data signal line data ₁ ' bitAt m1 st virtual data signal line data _m1 ' one side near the transparent hole k1.

Item 1 st to item 1 st target scan signal lines SN1 to SN _m1 Can be sequentially connected with the m1 th virtual data signal line data _m1 ' to 1 st dummy data signal line data ₁ ' electrically connected in a one-to-one correspondence. That is, the 1 st entry mark scanning signal line SN1 and the m1 st dummy data signal line data _m1 'electric connection, \8230;' item 1 indicates a scanning signal line SN _m1 Can be connected with the 1 st virtual data signal line data ₁ ' an electrical connection.

In this way, the 1 st to m1 st entry mark scanning signal lines SN1 to SN in the sub-area a _m1 The data wires are sequentially and electrically connected with the virtual data signal wires data' according to the arrangement sequence, and the connection mode accords with the wiring rule of the display area, so that the wiring is convenient. In addition, when the target scanning signal line SN is disconnected with the virtual data signal line data', the target scanning signal line SN is convenient to find and repair.

Fig. 13 is a schematic partial circuit diagram of an array substrate according to an embodiment of the present disclosure. As shown in fig. 13, according to some embodiments of the application, optionally, one sub-region a may include m 1-entry-mark scanning signal lines SN, the m 1-entry-mark scanning signal lines SN may be electrically connected to the m1 dummy data signal lines data' in a one-to-one correspondence, and m1 is a positive integer. Although m1=6 is shown as an example in fig. 13, it is to be understood that m1 may be a numerical value other than 6, and this is not limited in the embodiment of the present application.

Item 1 st to item 1 st target scan signal lines SN1 to SN _m1 Sequentially arranged along a first direction Y, m1 virtual data signal lines data' sequentially arranged along a second direction X, and the m1 th virtual data signal lines data _m1 ' at the 1 st virtual data signal line data ₁ ' one side near the transparent hole k1.

Item 1 st to jth item target scan signal lines SN1 to SN _j Sequentially connected with the 1 st virtual data signal line data ₁ ' to jth dummy data signal line data _j ' one-to-one correspondence electric connection, 1 <j < m1 and j is an integer. Alternatively, in some examples, j may be equal to m1/2. Of course, j may also be any value greater than 1 and less than m1, which is not limited in the embodiments of the present application.

Item j +1 mark scanning signal line SN _j+1 Scan signal line SN for item m1 _m1 Sequentially connected with the m1 th virtual data signal line data _m1 ' to the (j + 1) th dummy data signal line data _j+1 ' electrically connected in a one-to-one correspondence.

As shown in fig. 13, two load modules 50 may be disposed in a row along the second direction X, each load module 50 being for compensating a load of one target scan signal line SN. In this way, since two load modules 50 are disposed in a row, the width of the first frame area NA1 along the first direction Y can be reduced, which is beneficial to realizing a narrow frame.

In addition, since the edge of the transparent hole k1 is arc-shaped, the target scan signal line SN (e.g., the 1 st entry mark scan signal line SN1 or the m1 st entry mark scan signal line SN) located at the edge of the sub-area a _m1 ) The number of the connected pixel circuits is large, and correspondingly, the load needing to be compensated is small; and the target scan signal line SN located at the center of the sub-area a (e.g., the m1/2 th item mark scan signal line SN1 or the (m 1/2) +1 th item mark scan signal line SN) _m1 ) The number of connected pixel circuits is small, corresponding to a large load to be compensated. The larger the resistance or capacitance of the load module 50, the larger the size of the corresponding load module 50. Taking m1=6 as an example, the 1 st item scanning signal line SN1 and the 6 th item scanning signal line SN _m1 The size of the connected load module 50 is the largest, the size of the load module 50 connected to the 3 rd item scan signal line SN and the 4 th item scan signal line SN is the smallest, and the size of the load module 50 connected to the 2 nd item scan signal line SN and the 5 th item scan signal line SN is intermediate.

In the connection manner shown in fig. 13, the load module 50 connected to the 1 st item scan signal line SN1 and the load module 50 connected to the 4 th item scan signal line SN are located on the same row, and the load module 50 connected to the 2 nd item scan signal line SN and the 5 th item scan signal line SN are connectedThe load module 50 of item 3 is located in the same row, the load module 50 connected to the item 6 tag scan signal line SN is connected to the item 3 tag scan signal line SN _m1 The connected load modules 50 are located in the same row such that the sum of the sizes of the load modules 50 in each row is the same or similar, avoiding large differences in the sum of the sizes of the load modules 50 in different rows. In addition, by adopting the connection manner shown in fig. 13, any dummy data signal line data' can be connected to the corresponding load module 50 without overlapping with other load modules 50, so that the over-line design can be avoided, the wiring space can be saved, the simplification of the production process can be facilitated, and the production cost can be reduced. Here, the other load modules 50 mentioned above may be understood as the load modules 50 to which the other dummy data signal lines data' are connected.

Fig. 14 is a schematic partial circuit diagram of an array substrate according to an embodiment of the present disclosure. As shown in fig. 14, according to some embodiments of the application, optionally, one sub-region a may include m 1-entry-mark scanning signal lines SN, the m 1-entry-mark scanning signal lines SN may be electrically connected to the m1 dummy data signal lines data' in a one-to-one correspondence, and m1 is a positive integer. Although m1=6 is shown as an example in fig. 14, it is to be understood that m1 may be a numerical value other than 6, and this is not limited in the embodiment of the present application.

Item 1 st to jth item target scan signal lines SN1 to SN _j Sequentially connected with the m1 th virtual data signal line data _m1 ' to m1-j +1 th dummy data signal line data _m1-j+1 ' are electrically connected in one-to-one correspondence, j is more than 1 and less than m1, and j is an integer. Alternatively, in some examples, j may be equal to m1/2. Of course, j may also be any value greater than 1 and less than m1, which is not limited in the embodiments of the present application.

Item (j + 1)Target scanning signal line SN _j+1 Item number m1 to item number scanning signal line SN _m1 Sequentially connected with the 1 st virtual data signal line data ₁ ' to j-1 th dummy data signal line data _j-1 ' electrically connected in a one-to-one correspondence.

The embodiment shown in fig. 14 can produce the same or similar technical effects as the embodiment shown in fig. 13, and for details, refer to the above, which are not repeated herein.

As described above, when the scanning signal lines S are used for controlling data writing, the display luminance of the first area A1 may be greatly different from the display luminance of the second area A2 without compensating the scanning signal lines S in the first area A1. Therefore, in some embodiments, the target scan signal line SN may be a scan signal line controlling data writing, i.e., a scan signal line compensating for control data writing in the first region A1.

Fig. 15A is a circuit schematic diagram of a pixel circuit in an array substrate according to an embodiment of the present disclosure. As shown in fig. 15A, according to some embodiments of the present application, optionally, the array substrate includes a pixel circuit 100, and the pixel circuit 100 may include a driving module 101 and a data writing module 102. The driving module 101 may be used to drive the light emitting element D to emit light.

The control end of the data writing module 102 is electrically connected to the first scanning signal line S1, the first end of the data writing module 102 is electrically connected to the data signal line data, the second end of the data writing module 102 is electrically connected to the first end of the driving module 101, and the data writing module 102 is configured to be turned on in response to the turn-on level provided by the first scanning signal line S1 to write the data signal of the data signal line data into the first end of the driving module 101.

Among them, the target scanning signal line SN may include the first scanning signal line S1.

In this way, by compensating the load of the first scan signal line S1 in the first area A1, the delay of the first scan signal output by the first scan signal line S1 in the first area A1 is the same as or similar to the delay of the first scan signal output by the first scan signal line S1 in the second area A2, so that the on-time period of the data write module 102 in the first area A1 is the same as or similar to the on-time period of the data write module 102 in the second area A2, the display luminance difference between the first area A1 and the second area A2 is reduced, and the display effect is improved.

With continued reference to fig. 15A, according to some embodiments of the present application, optionally, the pixel circuit 100 may further include a first reset module 102 and a threshold compensation module 103, wherein:

the control end of the first reset module 103 is electrically connected to the second scanning signal line S2, the first end of the first reset module 103 is electrically connected to the first reference voltage signal line VREF1, the second end of the first reset module 103 is electrically connected to the control end of the driving module 101, and the first reset module 103 is configured to be turned on in response to the turn-on level provided by the second scanning signal line S2, and transmit the first reference voltage signal of the first reference voltage signal line VREF1 to the control end of the driving module 101, so as to reset the control end of the driving module 101;

the control end of the threshold compensation module 104 is electrically connected to the third scanning signal line S3, the first end of the threshold compensation module 104 is electrically connected to the control end of the driving module 101, the second end of the threshold compensation module 104 is electrically connected to the second end of the driving module 101, and the threshold compensation module 104 is configured to be turned on in response to a conduction level provided by the third scanning signal line S3, communicate the control end of the driving module 101 with the second end of the driving module 101, and implement threshold voltage compensation of the driving module 101 in cooperation with the data writing module 102.

With continued reference to fig. 15A, according to some embodiments of the present application, optionally, the pixel circuit 100 may further include a second reset module 105, a first light emitting control module 106, a second light emitting control module 107, a bias voltage compensation module 108, and a storage capacitor Cst.

The control terminal of the second reset module 105 may be electrically connected to the fourth scan signal line S4, the first terminal of the second reset module 105 is electrically connected to the second reference voltage signal line VREF2, the second terminal of the second reset module 105 is electrically connected to the first electrode of the light emitting device D, and the second reset module 105 is configured to be turned on in response to the conduction level provided by the fourth scan signal line S4, and transmit the second reference voltage signal provided by the second reference voltage signal line VREF2 to the first electrode of the light emitting device D, so as to reset the first electrode of the light emitting device D.

A control end of the first light emission control module 106 is electrically connected to the light emission control signal line EM, a first end of the first light emission control module 106 is electrically connected to the first power voltage signal line PVDD, and a second end of the first light emission control module 106 is electrically connected to the first end of the driving module 101.

A control terminal of the second light emission control module 107 is electrically connected to the light emission control signal line EM, a first terminal of the second light emission control module 107 is electrically connected to a second terminal of the driving module 101, and a second terminal of the second light emission control module 107 is electrically connected to the first electrode of the light emitting element D.

The control terminal of the offset voltage compensation module 108 is electrically connected to the fifth scanning signal line S5, the first terminal of the offset voltage compensation module 108 is electrically connected to the offset voltage signal line DVH, the second terminal of the offset voltage compensation module 108 is electrically connected to the first terminal of the driving module 101, and before the data signal is written, the offset voltage compensation module 108 is turned on in response to the turn-on level provided by the fifth scanning signal line S5, and transmits the offset voltage signal provided by the offset voltage signal line DVH to the first terminal of the driving module 101. Since the driving module 101 is in the on state at this time, the bias voltage signal is also transmitted to the second end of the driving module 101, so that the potential of the second end of the driving module 101 is higher than the potential of the control end of the driving module 101, and the threshold voltage Vth of the driving module 101 is adjusted.

A first plate of the storage capacitor Cst is electrically connected to the first power voltage signal line PVDD, and a second plate of the storage capacitor Cst is electrically connected to the first node N1, and is configured to maintain a potential of the first node N1.

In some embodiments, the target scan signal line SN may further include at least one of the second scan signal line S2 and the third scan signal line S3.

Since the first reset module 103 and the threshold compensation module 104 are electrically connected to the control terminal (i.e., the first node N1) of the driving module 101, the on-time of the first reset module 103 and the on-time of the threshold compensation module 104 may have a certain influence on the brightness of the light emitting element D. Therefore, by compensating the load of the second scanning signal line S2 and/or the third scanning signal line S3 in the first area A1, the difference between the display luminance of the first area A1 and the display luminance of the second area A2 can be further improved, and the display effect can be improved.

For example, as shown in fig. 15A, for an 8T1C pixel circuit, each row of pixel circuits needs 5 scan signals (i.e., scan signals provided by scan signal lines S1 to S5), and if each scan signal is provided with one shift register circuit and double-side driving is adopted, a single-side frame needs 5 shift register circuits, and a narrow-frame design cannot be realized. Therefore, in the present application, the other scan signal lines except the first scan signal line S1 can be driven by a single side, and the design of one driving and two driving can be used. This can greatly reduce the width of the border area.

FIG. 15B is a timing diagram of the embodiment shown in FIG. 15A. As shown in fig. 15B, S1-1 in fig. 15B indicates the first scanning signal line S1 (hereinafter, simply referred to as "first-row first scanning signal line S1") to which the first-row pixel circuits 100 in two adjacent rows of pixel circuits 100 are connected, and S1-2 indicates the first scanning signal line S1 (hereinafter, simply referred to as "second-row first scanning signal line S1") to which the second-row pixel circuits 100 in two adjacent rows of pixel circuits 100 are connected. Each third scanning signal line S3 may be electrically connected to two rows of pixel circuits 100, thereby implementing a one-drive-two design of the third scanning signal line S3.

Referring to fig. 15A and 15B, taking the threshold compensation module 104 as an N-type transistor and the data write module 102 as a P-type transistor as an example, when the third scan signal line S3 adopts a second driving scheme, the high level pulse output by the third scan signal line S3 needs to cover the low level pulses of the first scan signal line S1 in the first row and the first scan signal line S1 in the second row. When the third scanning signal line S3 is turned on (i.e., outputs a high-level pulse), the first scanning signal lines S1 to which the two rows of pixel circuits 100 are connected are turned on in turn (i.e., outputs a low-level pulse). The luminance difference of the odd and even rows occurs if the third scanning signal line S3 is turned off immediately after the first scanning signal line S1 of the second row is turned off. Because the third scanning signal line S3 is still turned on after the first row of the first scanning signal line S1 is turned off, and the third scanning signal line S3 is turned off immediately after the second row of the first scanning signal line S1 is turned off. This results in some additional charging time for the first row of pixel circuits 100. Therefore, in order to solve the problem of the luminance difference of the odd and even rows, the third scanning signal line S3 is still turned on for a while after the first scanning signal line S1 of the second row is turned off, so that the difference of the charging time of the odd and even rows can be reduced by a multiple, and the luminance difference of the odd and even rows can be alleviated.

Based on the above design, since the on time of the third scan signal line S3 may affect the data signal input by the driving module 101, the brightness difference between the first area A1 and the second area A2 caused by the delay may be mitigated by compensating for the load of the third scan signal line S3.

In some embodiments, the fourth scanning signal line S4 may be multiplexed with the first scanning signal line S1.

With continued reference to fig. 15A, according to some embodiments of the present application, optionally, the driving module 101 may include a driving transistor T0, the data writing module 102 may include a first transistor T1, the first reset module 103 may include a second transistor T2, the threshold compensation module 104 may include a third transistor T3, the second reset module 105 may include a fourth transistor T4, the first light emission control module 106 may include a fifth transistor T5, the second light emission control module 107 may include a sixth transistor T6, and the bias voltage compensation module 108 may include a seventh transistor T7. Please refer to fig. 15A and the above description of the connection manner of each module, which are not described herein again.

Fig. 16 is a schematic partial circuit diagram of an array substrate according to an embodiment of the present disclosure. As shown in fig. 16, according to some embodiments of the present application, optionally, the array substrate 40 further includes a scan driving circuit 200, and the scan driving circuit 200 includes a plurality of cascaded shift registers 200a. One shift register 200a may be electrically connected to the m-th and m + 1-th entry target scan signal lines SN, m being a positive integer, which are adjacent. That is, one shift register 200a may be electrically connected to an adjacent target scanning signal line SN, and the shift register 200a may be used to output a scanning signal to the target scanning signal line SN.

The m-th entry mark scan signal line SN and the m + 1-th entry mark scan signal line SN in the first area A1 may be electrically connected to the load module 50 in the first bezel area NA1 through the same dummy data signal line data'. That is, for the mth entry scan signal line SN and the (m + 1) th entry scan signal line SN connected to the same shift register 200a, the adjacent mth entry scan signal line SN and the (m + 1) th entry scan signal line SN may be connected to the same dummy data signal line data', and then electrically connected to one load module 50. The resistance of the load module 50 may be the sum of the resistance of the mth entry target scanning signal line SN to be compensated and the resistance of the m +1 th entry target scanning signal line SN to be compensated. Alternatively, the capacitance value of the load module 50 may be the sum of the capacitance value to be compensated for the mth entry standard scanning signal line SN and the capacitance value to be compensated for the (m + 1) th entry standard scanning signal line SN.

In this way, for the m-th entry mark scanning signal line SN and the m + 1-th entry mark scanning signal line SN connected to the same shift register 200a, the two target scanning signal lines SN can implement load compensation only through one dummy data signal line data 'and one load module 50, thereby greatly reducing the number of the dummy data signal lines data' and the load modules 50 used, and saving the wiring space and the production cost.

In some specific embodiments, as shown in fig. 15A and fig. 16, optionally, the second scanning signal lines S2 and the third scanning signal lines S3 may adopt a one-to-two connection manner shown in fig. 16, that is, one shift register may connect two adjacent second scanning signal lines S2, and/or one shift register may connect two adjacent third scanning signal lines S3.

Fig. 17 is a schematic partial circuit diagram of an array substrate according to an embodiment of the present disclosure. As shown in fig. 17, according to some embodiments of the present application, optionally, the z1 th entry mark in the first sub-area a1 scans the signal line SN _z1 The number of connected sub-pixels (not shown in the figure) can be equal to the z2 th stripe in the first sub-area a1Target scanning signal line SN _z2 The number of connected sub-pixels is the same, and z1 and z2 are both positive integers. For example, as shown in FIG. 13, for example, the number of sub-pixels to which the 1 st item scan signal line SN1 is connected and the 6 th item scan signal line SN _m1 The number of connected sub-pixels may be the same.

Since the z1 th item is marked with the scanning signal line SN _z1 The number of connected sub-pixels and the z2 th item mark scanning signal line SN _z2 The number of connected sub-pixels is the same, so that theoretically the z1 th entry marks the scanning signal line SN _z1 The magnitude of the load to be compensated and the z2 th entry mark scanning signal line SN _z2 The size of the load to be compensated. However, the inventors of the present application have found that, in practice, if the z1 th item is marked with the scanning signal line SN _z1 And z2 th entry mark scanning signal line SN _z2 Compensating for the same load may cause problems of under-compensation or over-compensation of one or both of the target scanning signal lines.

In view of this, the present application considers that the signal line SN is scanned for the z1 th entry mark _z1 And z2 th entry mark scanning signal line SN _z2 And performing difference compensation. Specifically, for convenience of explanation, the signal line SN will be scanned with the z1 th entry _z1 The first line segment L1 connected is called the first target line segment Lm1, and the z2 th item is marked with the scanning signal line SN _z2 The connected first route segment L1 is referred to as a second target route segment Lm2. The length h1 of the first target running line segment Lm1 may be greater than the length h2 of the second target running line segment, and/or the number of scanning signal lines (not shown in the figure) overlapping with the first target running line segment Lm1 may be greater than the number of scanning signal lines overlapping with the second target running line segment Lm2.

It is easy to understand that, the longer the length of the trace is, the greater the impedance of the trace itself is, so the impedance of the first target trace segment Lm1 is greater than the impedance of the second target trace segment. In addition, the first target routing segment Lm1 and the second target routing segment Lm2 extending along the first direction Y overlap with the scanning signal line extending along the second direction X, and coupling capacitance is generated due to the overlapping, so that the load of the first target routing segment Lm1 and the second target routing segment Lm2 is increased. When the number of the scanning signal lines overlapped by the first target line segment Lm1 is greater than the number of the scanning signal lines overlapped by the second target line segment Lm2, the load of the first target line segment Lm1 is also greater than that of the second target line segment Lm2. Therefore, the first wiring segment L1 can be regarded as a part of compensating the load of the target scanning signal line SN.

Accordingly, the z1 th item marks the scanning signal line SN _z1 The resistance value of the corresponding connected load module 50 may be smaller than the z2 th item scan signal line SN _z2 Corresponding to the resistance of the connected load module 50. Alternatively, the z1 th entry mark scanning signal line SN _z1 The capacity value of the corresponding connected load module 50 may be smaller than the z2 th entry scan signal line SN _z2 Corresponding to the capacitance of the connected load module 50.

Therefore, different target scanning signal lines SN with the same load to be compensated are subjected to differential compensation, the problem of under-compensation or over-compensation of the target scanning signal lines can be solved, and accurate compensation is achieved.

For ease of understanding, the array substrate 40 of the present application is illustrated in the following with reference to some specific embodiments.

Fig. 18 is a schematic partial structure view of an array substrate according to an embodiment of the present disclosure. As shown in fig. 18, according to some embodiments of the present application, optionally, the first area A1 is partitioned by the transparent hole k1 into at least a first sub-area A1 and a second sub-area a2 along the second direction X.

The first sub-area a1 may include an m 1-item-mark scan signal line SN, the second sub-area a2 may include an m 2-item-mark scan signal line SN, the m 1-item-mark scan signal line SN may extend to the first side edge k1a of the transparent hole k1 to be cut off, the m 2-item-mark scan signal line SN may extend to the second side edge k1b of the transparent hole k1 to be cut off, and m1 and m2 are positive integers. Wherein the first side edge k1a and the second side edge k1b may be opposite along the second direction X. In fig. 18, the first side edge k1a may be a left edge of the transparent hole k1, and the second side edge k1b may be a right edge of the transparent hole k1. Illustratively, m1 may be equal to m2, i.e., the number of target scan signal lines SN in the first sub-area a1 may be equal to the number of target scan signal lines SN in the second sub-area a2. The target scan signal line SN in the first sub-area a1 and the target scan signal line SN in the second sub-area a2 are not connected to each other, the target scan signal line SN in the first sub-area a1 may be electrically connected to a scan driving circuit (not shown) located on a left frame of the array substrate 40, and the target scan signal line SN in the second sub-area a2 may be electrically connected to a scan driving circuit (not shown) located on a right frame of the array substrate 40, so as to provide scan signals for the pixel circuits in the first sub-area a1 and the second sub-area a2.

The m1 entry mark scanning signal lines SN may be electrically connected to the m1 dummy data signal lines data 'on the first side (e.g., left side) of the transparent hole k1 in a one-to-one correspondence, and the m2 entry mark scanning signal lines SN may be electrically connected to the m2 dummy data signal lines data' on the second side of the transparent hole k1 in a one-to-one correspondence.

In this way, since the target scan signal line SN in the first sub-area a1 extends to the first side edge k1a of the transparent hole k1 to be cut off, and the target scan signal line SN in the second sub-area a2 extends to the second side edge k1b of the transparent hole k1 to be cut off, the target scan signal line SN on the first side of the transparent hole k1 does not need to be wound to the second side of the transparent hole k1, so that the number of wires around the transparent hole k1 can be reduced, and the problem of signal crosstalk caused by an excessive number of wires around the transparent hole k1 can be effectively avoided.

Fig. 19 is a schematic view of another partial structure of an array substrate according to an embodiment of the present disclosure. As shown in fig. 19, according to further embodiments of the present application, optionally, the first area A1 is partitioned by the transparent hole k1 into at least a first sub-area A1 and a second sub-area a2 along the second direction X.

The first sub-region a1 may include an m 1-entry scan signal line SN, the m 1-entry scan signal line SN in the first sub-region a1 may be routed to the second sub-region a2 along an edge of the transparent hole k1, and the m 1-entry scan signal line may be electrically connected to the sub-pixels in the second sub-region a2. That is, the m1 entry marks the scan signal line SN to simultaneously supply the scan signals to the sub-pixels in the first sub-area a1 and the second sub-area a2.

Among the m1 entry mark scanning signal lines SN, a part of the target scanning signal lines SN may be electrically connected to the load block 50 through the dummy data signal line data 'located at the first side of the transparent hole k1, and another part of the target scanning signal lines SN may be electrically connected to the load block 50 through the dummy data signal line data' located at the second side of the transparent hole k1. In fig. 19, the first side of the transparent hole k1 may be the left side of the transparent hole k1, and the second side of the transparent hole k1 may be the right side of the transparent hole k1.

Therefore, by communicating the target scanning signal lines SN in the first sub-area a1 and the second sub-area a2, the problem of screen splitting caused by inconsistent load or inconsistent load compensation effect of the first sub-area a1 and the second sub-area a2 can be avoided, and the display effect is improved.

In other embodiments, the m1 entry mark scanning signal lines SN may be electrically connected to the load module 50 through the dummy data signal lines data 'on the first side of the transparent hole k1, or may be electrically connected to the load module 50 through the dummy data signal lines data' on the second side of the transparent hole k1, which is not limited in this embodiment of the present invention.

Fig. 20 is a schematic view of another partial structure of the array substrate according to the embodiment of the present application. As shown in fig. 20, according to further embodiments of the present application, the transparent holes k1 may optionally include first holes k11 and second holes k12 arranged at intervals in the second direction X. Illustratively, each of the first and second holes k11 and k12 may include any one of a kidney-shaped hole, a rectangular hole, an elliptical hole, and a circular hole. For example, as shown in fig. 20, the first hole k11 may include a kidney-shaped hole, and the second hole k12 may include a circular hole. The straight line of the center of the kidney-shaped hole and the center of the circular hole is parallel to the second direction X. The length direction of the kidney-shaped hole may be parallel to the second direction X, the width direction of the kidney-shaped hole may be parallel to the first direction Y, and the width of the kidney-shaped hole may be equal to the diameter of the circular hole.

The first region A1 is partitioned into a first sub-region A1, a second sub-region a2, and a third sub-region a3 by the first hole k11 and the second hole k12, and the third sub-region a3 may be located between the first hole k11 and the second hole k12.

The first sub-area a1 may include m 1-item-index scan signal lines SN, and the second sub-area a2 may include m 2-item-index scan signal lines SN. The m 1-entry scan signal line SN may extend to the edge cutoff of the first hole k 11. The m 2-entry scan signal line SN may be routed to the third sub-area a3 along the edge of the second hole k12, and the m 2-entry scan signal line SN may be electrically connected to the sub-pixel in the third sub-area a3. That is, the m2 entry marks the scan signal line SN to simultaneously supply the scan signal to the sub-pixels in the third sub-area a3 and the second sub-area a2. Alternatively, the size of the second hole k12 may be smaller than that of the first hole k11, i.e., the target scanning signal line SN is routed to the third sub-area a3 through the edge of the hole having the smaller size.

The m1 entry mark scan signal lines SN in the first sub-region a1 may be electrically connected to the m1 dummy data signal lines data' on the first side of the first hole k11 in a one-to-one correspondence, where the first side of the first hole k11 is a side of the first hole k11 away from the second hole k12, for example, the left side of the first hole k 11.

The m2 entry mark scanning signal lines SN in the second sub-region a2 may be electrically connected to the m2 dummy data signal lines data' located at the second side of the first hole k11 in a one-to-one correspondence manner, where the second side of the first hole k11 is a side of the first hole k11 close to the second hole k12, for example, the right side of the first hole k 11.

In this way, since the target scan signal line SN in the first sub-region a1 extends to the first side edge of the first hole k11 to be cut off, and the target scan signal line SN in the second sub-region a2 extends to the second side edge of the first hole k11 to be cut off, the target scan signal line SN on the first side of the first hole k11 does not need to be wound to the second side of the first hole k11, so that the number of wires around the first hole k11 can be reduced, and the problem of signal crosstalk caused by the excessive number of wires around the first hole k11 can be effectively avoided.

With continued reference to fig. 20, according to some embodiments of the present application, optionally, the m2 entry mark scan signal lines SN in the second sub-region a2 may be electrically connected to the m2 dummy data signal lines data' located between the first hole k11 and the second hole k12 (in the Q1 region in fig. 20) in a one-to-one correspondence. That is, the m 2-entry mark scan signal line SN in the second sub-region a2 may be electrically connected to the load module 50 at the dummy data signal line data' between the first and second holes k11 and k12.

The m2 entry mark scanning signal line SN in the second sub-region a2 extends to the region between the first hole k11 and the second hole k12 and is cut off, and the dummy data signal line data' is connected to the end of the target scanning signal line SN for load compensation, so that a better compensation effect is achieved.

With continued reference to fig. 20, according to further embodiments of the present application, optionally, of the m2 entry mark scan signal lines SN in the second sub-region a2, a part of the target scan signal lines SN may be electrically connected to the dummy data signal line data 'located between the first hole k11 and the second hole k12 (e.g., in the Q1 region in fig. 20), another part of the target scan signal lines SN may be electrically connected to the dummy data signal line data' located on a second side of the second hole k12 (e.g., in the Q2 region in fig. 20), where the second side of the second hole k12 is a side of the second hole k12 far from the first hole k11, i.e., a right side of the second hole k12.

In this way, in the m2 entry mark scanning signal line SN in the second sub-region a2, a part of the target scanning signal line SN is electrically connected to the dummy data signal line data 'in the Q1 region, and another part of the target scanning signal line SN is electrically connected to the dummy data signal line data' in the Q2 region, so that the wiring is uniform, the wiring is facilitated, and the size of the upper frame is reduced.

Fig. 21 is a schematic view of another partial structure of an array substrate according to an embodiment of the present disclosure. As shown in fig. 21, according to further embodiments of the present application, the transparent holes k1 may optionally include first holes k11 and second holes k12 arranged at intervals in the second direction X. The first region A1 is partitioned into a first sub-region A1, a second sub-region a2, and a third sub-region a3 by the first hole k11 and the second hole k12, and the third sub-region a3 may be located between the first hole k11 and the second hole k12.

The first sub-area a1 may include an m 1-entry scan signal line SN, the m 1-entry scan signal line SN may be sequentially wound to the third sub-area a3 and the second sub-area a2 along an edge of the first hole k11 and an edge of the second hole k12, and the m 1-entry scan signal line SN is electrically connected to the sub-pixel in the third sub-area a3 and the sub-pixel in the second sub-area a2.

Of the m 1-entry scan signal lines SN of the first sub-region a1, a portion of the target scan signal lines SN may be electrically connected to the load block 50 through the dummy data signal lines data 'located at the first side of the first hole k11, and another portion of the target scan signal lines SN may be electrically connected to the load block 50 through the dummy data signal lines data' located at the second side of the first hole k 11. The first side of the first hole k11 is a side of the first hole k11 away from the second hole k12, and the second side of the first hole k11 is a side of the first hole k11 close to the second hole k12.

Therefore, by communicating the target scanning signal lines SN in the first sub-area a1, the second sub-area a2 and the third sub-area a3, the problem of screen splitting caused by inconsistent load or inconsistent load compensation effect of the first sub-area a1, the second sub-area a2 and the third sub-area a3 can be avoided, and the display effect is improved.

In addition, in the m1 entry mark scanning signal line SN of the first sub-area a1, a part of the target scanning signal line SN may be electrically connected to the load module 50 through the dummy data signal line data 'located at the first side of the first hole k11, and another part of the target scanning signal line SN may be electrically connected to the load module 50 through the dummy data signal line data' located at the second side of the first hole k11, so that the wiring may be uniform, the wiring may be facilitated, and the size of the upper bezel may be reduced.

Of course, in other embodiments, the m1 entry mark scanning signal lines SN of the first sub-region a1 may be electrically connected to the load module 50 through the dummy data signal line data 'located at the first side of the first hole k11, or electrically connected to the load module 50 through the dummy data signal line data' located at the second side of the first hole k11, which is not limited in this embodiment.

According to some embodiments of the present application, the load module 50 may optionally include a compensation capacitance. That is, capacitance compensation is performed on the target scanning signal line in the first region, so that the load of the target scanning signal line in the first region is the same as, similar to or in accordance with a certain gradual change rule with the load of the target scanning signal line in the second region, thereby improving the difference in display effect between the first region and the second region and improving the display effect.

Of course, in other embodiments, the load module 50 may also be an electronic device having a resistance, an inductance, or the like.

The following description will take the load module 50 as an example of a compensation capacitor, and take the film structure of the array substrate as an example.

Fig. 22 is a schematic partial cross-sectional view of an array substrate according to an embodiment of the present application. As shown in fig. 22, according to some embodiments of the present application, the array substrate 40 may optionally include a substrate 01, a first active layer b1, and a plurality of metal layers M, which are stacked.

The first plate C1 of the compensation capacitor C may be located on the first active layer b1, the first plate C1 of the compensation capacitor C may be electrically connected to the first power voltage signal line PVDD through a via hole, and the second plate C2 of the compensation capacitor C may be electrically connected to the dummy data signal line data' through a via hole.

Along a direction Z perpendicular to a plane of the array substrate, a metal layer on which the second plate C2 of the compensation capacitor C is located may be located between the first active layer b1 and the metal layer on which the first power voltage signal line PVDD is located.

In this way, the compensation capacitor C is formed by the first active layer b1 and the metal layer closer to the first active layer b1, so that the capacitance value of the compensation capacitor C is larger, and the compensation capacitor C with a larger capacitance value is formed in a limited wiring space, thereby meeting the load compensation requirement of the target scanning signal line.

With continued reference to fig. 22, in some specific embodiments, the plurality of metal layers M may optionally include a first metal layer M1, a second metal layer M2, a third metal layer M3, a fourth metal layer M4, and a fifth metal layer M5, which are stacked. It is easily understood that the array substrate 40 may include a transistor and a storage capacitor, a gate of the transistor and a first plate of the storage capacitor may be located in the first metal layer M1, a second plate of the storage capacitor may be located in the second metal layer M2, and a source and a drain of the transistor may be located in the third metal layer M3.

For example, the second plate C2 of the compensation capacitor C may be located on the first metal layer M1 or the second metal layer M2, the dummy data signal line data 'may be located on the fifth metal layer M5, and the dummy data signal line data' may be electrically connected to the second plate C2 of the compensation capacitor C through a via hole. The first power voltage signal line PVDD may be located in the third metal layer M3, and may be electrically connected to the first plate C1 of the compensation capacitor C in the first active layer b1 through a via hole. It should be noted that although the first plate C1 of the compensation capacitor C and the material forming the active region (including the source region, the drain region, and the channel region) of the transistor in the display region are located in the same film layer, the first plate C1 of the compensation capacitor C and the material forming the active region of the transistor in the display region are disconnected and not communicated with each other.

Fig. 23 is a schematic partial plan view of an array substrate according to an embodiment of the present disclosure. As shown in fig. 22 and 23, according to some embodiments of the present application, optionally, the array substrate may include a plurality of first power voltage signal lines PVDD extending along the first direction Y and arranged at intervals along the second direction X, head ends of the plurality of first power voltage signal lines PVDD may be connected to each other, and tail ends of the plurality of first power voltage signal lines PVDD may also be connected to each other, so as to reduce IR-drop of the first power voltage signal lines PVDD. The first plate C1 of the compensation capacitor C may extend in the first direction Y and be electrically connected to the first power voltage signal line PVDD through the via k 2. The first plate C1 of the compensation capacitor C may be located on the first active layer b1, and the first power voltage signal line PVDD may be located on the third metal layer M3. The second plate C2 of the compensation capacitor C may be in a shape of "C", or "S", or other multi-segment winding. Specifically, for example, the second plate C2 of the compensation capacitor C may include two opposite first extending portions 231 and a second extending portion 232 for connecting the two first extending portions 231, wherein the first extending portions 231 may extend along the second direction X, and the second extending portions 232 may extend along the first direction Y. The two opposing first extensions 231 may be parallel. The length of the first extension 231 may be greater than the length of the second extension 232.

The dummy data signal line data' on the fifth metal layer M5 may be electrically connected to the second plate C2 of the compensation capacitor C on the second metal layer M2 through the multi-layer via k 3. The lengths of the first plates C1 of different compensation capacitors C may be the same, so that the capacitance values of different compensation capacitors C may be different by adjusting the lengths of the second plates C2 of the compensation capacitors C.

Fig. 24 is another partial plan view of an array substrate according to an embodiment of the present application. As shown in fig. 22 and 24, unlike the embodiment shown in fig. 23, according to other embodiments of the present application, a plurality of first power voltage signal lines PVDD may optionally extend along the second direction X and be arranged at intervals along the first direction Y. The first plate C1 of the compensation capacitor C may extend in the second direction X and be electrically connected to the first power voltage signal line PVDD through the via k 2. The first plate C1 of the compensation capacitor C may be located on the first active layer b1, and the first power voltage signal line PVDD may be located on the third metal layer M3. The second plate C2 of the compensation capacitor C may have a "C" shape, and in particular, for example, the second plate C2 of the compensation capacitor C may include two opposite first extending portions 231 and a second extending portion 232 for connecting the two first extending portions 231, wherein the first extending portions 231 may extend along the first direction Y, and the second extending portions 232 may extend along the second direction X. The two opposing first extensions 231 may be parallel. The length of the first extension 231 may be greater than the length of the second extension 232.

The dummy data signal line data' located in the fifth metal layer M5 may be electrically connected to the second plate C2 of the compensation capacitor C located in the second metal layer M2 through the via hole k 3. The lengths of the first plates C1 of the different compensation capacitors C may be the same, so that the capacitance values of the different compensation capacitors C may be different by adjusting the lengths of the second plates C2 of the compensation capacitors C.

It should be noted that, in combination with fig. 15A and fig. 22, in the layout design of the pixel circuit in the display region, the storage capacitor Cst may include a first plate located in the first metal layer M1 and a second plate located in the second metal layer M2.

Based on the array substrate 40 provided by the above embodiment, correspondingly, the present application further provides a display device, which includes the array substrate 40 provided by the present application. Referring to fig. 25, fig. 25 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. Fig. 25 provides a display device 1000 including the array substrate 40 according to any of the above embodiments of the present application. The display device 1000 is described in the embodiment of fig. 25 by taking a mobile phone as an example, but it should be understood that the display device provided in the embodiment of the present application may be other display devices having a display function, such as wearable products, computers, televisions, and vehicle-mounted display devices, and the present application is not limited thereto. The display device provided in the embodiment of the present application has the beneficial effects of the array substrate 40 provided in the embodiment of the present application, and specific descriptions on the array substrate 40 in the above embodiments may be specifically referred to, and the detailed descriptions in this embodiment are omitted here.

It should be understood that the circuit structure of the array substrate 40 and the cross-sectional structure of the array substrate 40 provided in the drawings of the embodiments of the present application are only examples, and are not intended to limit the present application. In addition, the above embodiments provided by the present application may be combined with each other without contradiction.

In accordance with the embodiments of the present application as described above, these embodiments are not exhaustive of all of the details and are not intended to limit the application to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and its practical application, to thereby enable others skilled in the art to best utilize the application and its various modifications as are suited to the particular use contemplated. The application is limited only by the claims and their full scope and equivalents.

As described above, only the specific embodiments of the present application are provided, and it can be clearly understood by those skilled in the art that, for convenience and simplicity of description, the specific working processes of the system, the module and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again. It should be understood that the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the present application, and these modifications or substitutions should be covered within the scope of the present application.

Claims

1. An array substrate is characterized by comprising a transparent hole, a display area and a non-display area, wherein the display area surrounds the transparent hole, the non-display area comprises a first frame area and a second frame area, the first frame area, the display area and the second frame area are sequentially arranged along a first direction, the second frame area is used for being connected with a touch chip or a flexible circuit board, and the first frame area is provided with a load module;

the display area includes:

a plurality of target scanning signal lines extending along a second direction and arranged at intervals along a first direction, the target scanning signal lines being electrically connected to the sub-pixels in the display region and configured to provide scanning signals to the sub-pixels, the first direction crossing the second direction;

a plurality of data signal lines and a plurality of dummy data signal lines extending in the first direction and arranged at intervals in the second direction;

the display area comprises a first area and a second area, and the first area is divided into at least two sub-areas by the transparent holes along the second direction; the target scanning signal line in the first region is electrically connected to the load module in the first frame region through the dummy data signal line.

2. The array substrate of claim 1, wherein the dummy data signal lines comprise at least two broken line segments, the line segment closest to the first frame region is a first line segment, and the target scan signal line in the first region is electrically connected to the load module in the first frame region through the first line segment.

3. The array substrate of claim 2, wherein the array substrate is provided with a light emitting element, and the dummy data signal line and an anode of the light emitting element are located on different layers;

along the direction perpendicular to the plane of the array substrate, the breakpoint position of the virtual data signal line is located in the orthographic projection of the anode of the light-emitting element on the array substrate.

4. The array substrate according to claim 3, wherein the ith trace segment extends to the inside of the orthographic projection of the anode of the light emitting element and then is disconnected from other trace segments on the same straight line, and i is a positive integer.

5. The array substrate of claim 2, wherein at least some of the dummy data signal lines that are not connected to the target scan signal lines and the data signal lines are target trace lines, and the target trace lines are electrically connected to constant voltage signal lines.

6. The array substrate of claim 1, wherein one of the sub-regions comprises m1 target scan signal lines, wherein m1 target scan signal lines are electrically connected to m1 dummy data signal lines in a one-to-one correspondence, and m1 is a positive integer;

the 1 st to the m1 st target scanning signal lines are sequentially arranged along the first direction, the m1 virtual data signal lines are sequentially arranged along the second direction, and the m1 st virtual data signal line is positioned on one side of the 1 st virtual data signal line close to the transparent hole;

the 1 st to the m1 st target scanning signal lines are electrically connected with the m1 st to the 1 st virtual data signal lines in a one-to-one correspondence manner.

7. The array substrate of claim 1, wherein one of the sub-regions comprises m1 target scan signal lines, m1 target scan signal lines are electrically connected to m1 dummy data signal lines in a one-to-one correspondence, and m1 is a positive integer;

the 1 st to the m1 st target scanning signal lines are sequentially arranged along the first direction, the m1 virtual data signal lines are sequentially arranged along the second direction, and the 1 st virtual data signal line is positioned on one side of the m1 st virtual data signal line close to the transparent hole;

8. The array substrate of claim 1, wherein one of the sub-regions comprises m1 target scan signal lines, m1 target scan signal lines are electrically connected to m1 dummy data signal lines in a one-to-one correspondence, and m1 is a positive integer;

the 1 st to the jth target scanning signal lines are sequentially and correspondingly electrically connected with the 1 st to the jth virtual data signal lines in a one-to-one correspondence manner, j is more than 1 and less than m1, and j is an integer;

the (j + 1) th target scanning signal line to the (m 1) th target scanning signal line are electrically connected with the (m 1) th virtual data signal line to the (j + 1) th virtual data signal line in a one-to-one correspondence mode.

9. The array substrate of claim 1, wherein one of the sub-regions comprises m1 target scan signal lines, m1 target scan signal lines are electrically connected to m1 dummy data signal lines in a one-to-one correspondence, and m1 is a positive integer;

the 1 st to the jth target scanning signal lines are electrically connected with the m1 st to the m1-j +1 th virtual data signal lines in a one-to-one correspondence manner, j is more than 1 and less than m1, and j is an integer;

the (j + 1) th target scanning signal line to the (m 1) th target scanning signal line are sequentially and correspondingly electrically connected with the (1) th virtual data signal line to the (j-1) th virtual data signal line in a one-to-one correspondence manner.

10. The array substrate of claim 1, wherein the array substrate comprises a pixel circuit, the pixel circuit comprising:

the driving module is used for driving the light-emitting element to emit light;

the control end of the data writing module is electrically connected with a first scanning signal line, the first end of the data writing module is electrically connected with a data signal line, the second end of the data writing module is electrically connected with the first end of the driving module, and the data writing module is used for responding to a conduction level provided by the first scanning signal line to be conducted and writing a data signal of the data signal line into the first end of the driving module;

the target scanning signal line includes the first scanning signal line.

11. The array substrate of claim 10, wherein the pixel circuit further comprises:

the control end of the first reset module is electrically connected with the second scanning signal line, the first end of the first reset module is electrically connected with the first reference voltage signal line, the second end of the first reset module is electrically connected with the control end of the driving module, and the first reset module is used for responding to a conduction level provided by the second scanning signal line to be conducted and transmitting a first reference voltage signal of the first reference voltage signal line to the control end of the driving module so as to reset the control end of the driving module;

a control end of the threshold compensation module is electrically connected with a third scanning signal line, a first end of the threshold compensation module is electrically connected with a control end of the driving module, a second end of the threshold compensation module is electrically connected with a second end of the driving module, and the threshold compensation module is used for responding to a conduction level provided by the third scanning signal line to be conducted and communicating the control end of the driving module with the second end of the driving module;

the target scanning signal line further includes at least one of the second scanning signal line and the third scanning signal line.

12. The array substrate of claim 1, further comprising a scan driving circuit, wherein the scan driving circuit comprises a plurality of cascaded shift registers;

one shift register is electrically connected with the m & ltth & gt target scanning signal line and the m +1 & ltth & gt target scanning signal line which are adjacent, wherein m is a positive integer;

the mth target scanning signal line and the (m + 1) th target scanning signal line in the first region are electrically connected to the load module in the first frame region through the same dummy data signal line.

13. The array substrate according to claim 2, wherein the number of the sub-pixels connected to the z1 th target scanning signal line in the first sub-area is the same as the number of the sub-pixels connected to the z2 th target scanning signal line in the first sub-area, and z1 and z2 are both positive integers;

the first route segment connected with the z1 st target scanning signal line is a first target route segment, and the first route segment connected with the z2 nd target scanning signal line is a second target route segment;

the length of the first target route segment is greater than that of the second target route segment, and/or the number of scanning signal lines overlapped with the first target route segment is greater than that of the scanning signal lines overlapped with the second target route segment;

the resistance value of the load module correspondingly connected with the z1 th target scanning signal line is smaller than the resistance value of the load module correspondingly connected with the z2 th target scanning signal line.

14. The array substrate of claim 1, wherein along the second direction, the first region is separated by the transparent hole into at least a first sub-region and a second sub-region;

the first sub-area comprises m1 target scanning signal lines, the second sub-area comprises m2 target scanning signal lines, the m1 target scanning signal lines extend to a first side edge of the transparent hole and are cut off, the m2 target scanning signal lines extend to a second side edge of the transparent hole and are cut off, and m1 and m2 are positive integers;

m1 target scanning signal lines are electrically connected with m1 virtual data signal lines on the first side of the transparent hole in a one-to-one corresponding mode, and m2 target scanning signal lines are electrically connected with m2 virtual data signal lines on the second side of the transparent hole in a one-to-one corresponding mode.

15. The array substrate of claim 1, wherein along the second direction, the first region is separated into a first sub-region and a second sub-region by the transparent hole;

the first sub-region comprises m1 target scanning signal lines, the m1 target scanning signal lines are wound to the second sub-region along the edge of the transparent hole, and the m1 target scanning signal lines are electrically connected with the sub-pixels in the second sub-region;

in m1 target scanning signal lines, a part of the target scanning signal lines are electrically connected with the load module through the dummy data signal lines located on the first side of the transparent hole, and the other part of the target scanning signal lines are electrically connected with the load module through the dummy data signal lines located on the second side of the transparent hole.

16. The array substrate of claim 1, wherein the transparent holes comprise a first hole and a second hole spaced along the second direction, the first region is divided into a first sub-region, a second sub-region and a third sub-region by the first hole and the second hole, and the third sub-region is located between the first hole and the second hole;

the first sub-region comprises m1 target scanning signal lines, the second sub-region comprises m2 target scanning signal lines, the m1 target scanning signal lines extend to the edge of the first hole and are cut off, the m2 target scanning signal lines are wound to the third sub-region along the edge of the second hole, and the m2 target scanning signal lines are electrically connected with the sub-pixels in the third sub-region;

the m1 target scanning signal lines are electrically connected with the m1 virtual data signal lines positioned on the first side of the first hole in a one-to-one correspondence manner, and the first side of the first hole is the side of the first hole far away from the second hole;

the m2 target scanning signal lines are electrically connected with the m2 virtual data signal lines on the second side of the first hole in a one-to-one correspondence manner, and the second side of the first hole is the side, close to the second hole, of the first hole.

17. The array substrate of claim 16, wherein m2 target scan signal lines are electrically connected to m2 dummy data signal lines between the first hole and the second hole in a one-to-one correspondence;

or, in m2 target scanning signal lines, a part of the target scanning signal lines is electrically connected to the dummy data signal line located between the first hole and the second hole, another part of the target scanning signal lines is electrically connected to the dummy data signal line located on a second side of the second hole, and the second side of the second hole is a side of the second hole far from the first hole.

18. The array substrate of claim 1, wherein the transparent holes comprise a first hole and a second hole spaced along the second direction, the first region is divided into a first sub-region, a second sub-region and a third sub-region by the first hole and the second hole, and the third sub-region is located between the first hole and the second hole;

the first sub-region comprises m1 target scanning signal lines, the m1 target scanning signal lines are sequentially wound to the third sub-region and the second sub-region along the edge of the first hole and the edge of the second hole, and the m1 target scanning signal lines are electrically connected with the sub-pixels in the third sub-region and the sub-pixels in the second sub-region;

in m1 target scanning signal lines, a part of the target scanning signal lines are electrically connected with the load module through the dummy data signal lines located on the first side of the first hole, the other part of the target scanning signal lines are electrically connected with the load module through the dummy data signal lines located on the second side of the first hole, the first side of the first hole is the side of the first hole far away from the second hole, and the second side of the first hole is the side of the first hole close to the second hole.

19. The array substrate of claim 1, wherein the load module comprises a compensation capacitor.

20. The array substrate of claim 19, wherein the array substrate comprises a substrate, a first active layer, and a plurality of metal layers in a stacked arrangement;

the first polar plate of the compensation capacitor is positioned on the first active layer, the first polar plate of the compensation capacitor is electrically connected with a first power supply voltage signal line through a via hole, and the second polar plate of the compensation capacitor is electrically connected with the virtual data signal line through a via hole;

and along the direction vertical to the plane of the array substrate, the metal layer where the second plate of the compensation capacitor is located is positioned between the first active layer and the metal layer where the first power supply voltage signal line is located.

21. The array substrate of claim 20, wherein the plurality of metal layers comprises a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer arranged in a stacked arrangement;

the second plate of the compensation capacitor is located on the first metal layer or the second metal layer, and the first power supply voltage signal line is located on the third metal layer;

the array substrate comprises a transistor and a storage capacitor, a grid electrode of the transistor and a first polar plate of the storage capacitor are located on the first metal layer, a second polar plate of the storage capacitor is located on the second metal layer, and a source electrode and a drain electrode of the transistor are located on the third metal layer.

22. A display device comprising the array substrate according to any one of claims 1 to 21.