CN116613171A

CN116613171A - Display panel

Info

Publication number: CN116613171A
Application number: CN202310493622.1A
Authority: CN
Inventors: 姚学彬; 张露
Original assignee: Kunshan Govisionox Optoelectronics Co Ltd; Hefei Visionox Technology Co Ltd
Current assignee: Kunshan Govisionox Optoelectronics Co Ltd; Hefei Visionox Technology Co Ltd
Priority date: 2023-04-28
Filing date: 2023-04-28
Publication date: 2023-08-18

Abstract

The invention discloses a display panel, which comprises a light transmission area, a non-display area at least partially surrounding the light transmission area, a display area at least partially surrounding the non-display area, a plurality of first grid signal lines which are positioned on one side of a substrate, extend along a first direction in the display area and are distributed along a second direction, wherein each first grid signal line comprises a first wiring part positioned on one side of the light transmission area and positioned on the display area, and a second wiring part positioned on the other second side of the light transmission area and positioned on the display area. The first grid signal lines further comprise first connecting lines located in the non-display area, the first wiring portions are connected with the second wiring portions through the first connecting lines, the first connecting lines comprise first subsections and second subsections, and the first subsections and the second subsections are connected in parallel. According to the scheme, the load difference of the first grid signal line in the non-display area surrounding the light transmission area and the display area can be reduced, delay of the first grid signal transmitted on the first grid signal line is reduced, and display quality is improved.

Description

Display panel

Technical Field

The invention relates to the technical field of display, in particular to a display panel.

Background

With the development of display technology, people have increasingly high requirements on display quality.

Holes are typically provided in the display area of the display panel for placement of the camera assembly. In the prior art, the delay of the transmission signals on the signal lines at two sides of the hole is different, so that the display effect at two sides of the hole is easy to be different, and the display quality is reduced.

Disclosure of Invention

The invention provides a display panel, which aims to solve the problem of poor display effect on two sides of a hole in the display panel.

According to an aspect of the present invention, there is provided a display panel including a light-transmitting region, a non-display region at least partially surrounding the light-transmitting region, and a display region at least partially surrounding the non-display region, the display panel further comprising:

a substrate;

the first grid signal lines are positioned on one side of the substrate, extend in a first direction in the display area and are distributed in a second direction, each first grid signal line comprises a first wiring part positioned on the first side of the light transmission area and positioned in the display area and a second wiring part positioned on the second side of the light transmission area and positioned in the display area, and the first wiring part and the second wiring part extend to the non-display area; the first direction and the second direction are crossed and are perpendicular to the thickness direction of the display panel;

The first grid signal line further comprises a first connecting line, the first connecting line is located in the non-display area, the first wiring portion is connected with the second wiring portion through the first connecting line, the first connecting line comprises a first subsection and a second subsection, and the first subsection and the second subsection are connected in parallel.

Optionally, the display panel includes a plurality of conductive layers stacked on one side of the substrate;

in the same first gate signal line, the first subsection and the second subsection are positioned on different conductive layers;

optionally, in the same first gate signal line, the first subsection and the first wiring portion are located on the same conductive layer; or alternatively, the process may be performed,

the first subsection and the first wiring part are positioned on different conductive layers, and the second subsection and the first wiring part are positioned on different conductive layers;

optionally, the first subsection and the second subsection are connected through a via hole, and the first wiring part and the second wiring part are arranged in the same layer.

Optionally, the multi-layer conductive layer includes a first conductive layer and a second conductive layer, the first conductive layer is located at one side of the substrate, and the second conductive layer is located at one side of the first conductive layer away from the substrate;

The multi-layer conductive layer further comprises a third conductive layer and/or a fourth conductive layer, wherein the third conductive layer is positioned on one side of the first conductive layer close to the substrate, and the fourth conductive layer is positioned on one side of the second conductive layer far away from the substrate;

the first wiring part is located on the first conductive layer, the first subsection is located on the first conductive layer or the second conductive layer, and the second subsection is located on the third conductive layer or the fourth conductive layer.

Optionally, in a non-display area at least partially surrounding the light-transmitting area, the perpendicular projections of the first sub-segment on the substrate and the perpendicular projections of the second sub-segment on the substrate are staggered.

Optionally, the first subsections corresponding to the two adjacent first gate signal lines are located in different conductive layers, and the second subsections corresponding to the two adjacent first gate signal lines are located in the same conductive layer;

optionally, the first subsections corresponding to the first gate signal lines are arranged in a mode that the first conductive layers and the second conductive layers alternate with each other to replace lines.

Optionally, the display panel further includes a plurality of second gate signal lines;

The second grid signal line comprises a third wiring part which is positioned at the first side of the light transmission area and positioned in the display area, a fourth wiring part which is positioned at the second side of the light transmission area and positioned in the display area, and a second connecting line which is positioned in the non-display area, wherein the second connecting line comprises a third subsection, and the third wiring part and the fourth wiring part are connected through the third subsection;

optionally, the third wiring portion and the first wiring portion are arranged on the same layer, the second gate signal lines and the first gate signal lines are alternately arranged, and in the adjacent first gate signal lines and second gate signal lines, the third sub-segment and the first sub-segment are located on different conductive layers.

Optionally, the second connecting line further comprises a fourth sub-section, and the third sub-section and the fourth sub-section are located on different layers and connected in parallel;

optionally, the fourth sub-segment is arranged in the same layer as the second sub-segment.

Optionally, the display panel further includes a plurality of third gate signal lines, a vertical projection of the first gate signal line on the substrate is located between a vertical projection of the second gate signal line on the substrate and a vertical projection of the third gate signal line on the substrate, the third gate signal line includes a fifth trace portion located at a first side of the light-transmitting region and located at the display region and a sixth trace portion located at a second side of the light-transmitting region and located at the display region, the third gate signal line further includes a third connection line located at the non-display region, the third connection line includes a fifth subsection, and the fifth trace portion and the sixth trace portion are connected through the fifth subsection;

The second gate signal lines, the first gate signal lines and the third gate signal lines are alternately arranged, and at least two of the first sub-section, the third sub-section and the fifth sub-section are located in different conductive layers.

Preferably, the third sub-section, the first sub-section and the fifth sub-section are arranged in a manner that the first conductive layer and the second conductive layer alternate with each other to form a line, a plurality of the second sub-sections are located in conductive layers different from the first conductive layer and the second conductive layer, and a plurality of the second sub-sections are located in the same conductive layer.

Optionally, the third connecting line further comprises a sixth subsection, wherein the fifth subsection and the sixth subsection are positioned on different layers and are connected in parallel;

optionally, the sixth subsection is arranged in a same layer as the second subsection.

Optionally, the display panel further includes a plurality of data lines extending in the second direction in the display area and arranged in the first direction, the data lines including first data lines and second data lines alternately arranged, the first data lines including first connection portions located in the non-display area, the second data lines including second connection portions located in the non-display area, the first connection portions and the second connection portions being located in different layers;

Optionally, the first connection portion and/or the second connection portion is located at a different layer than the first subsection.

Optionally, the display panel further includes a pixel circuit including a data writing transistor, a driving transistor, and a storage capacitor, the data writing transistor being connected between a data line and the driving transistor, the driving transistor and the light emitting diode being connected between a first power line and a second power line, the storage capacitor being connected between the first power line and a gate of the driving transistor;

the data writing transistor is turned on in response to a first gate signal transmitted on the first gate signal line, and transmits a data voltage on the data line to the driving transistor;

optionally, the display panel further includes a shielding layer, where the shielding layer is located at a side of the pixel circuit, where the gate of the driving transistor is close to the substrate;

optionally, the second subsection is arranged in the same layer as the shielding layer.

Optionally, the pixel circuit further includes a first initialization transistor, a first light emitting control transistor, and a second light emitting control transistor, the first initialization transistor is connected to the gate of the driving transistor, and the second diode of the light emitting diode is connected to the second power line; the first light emitting control transistor is connected between a first power line and a first pole of the driving transistor, and the second light emitting control transistor is connected between a second pole of the driving transistor and a first pole of the light emitting diode;

The display panel further includes a second gate signal line and a third gate signal line, the first initialization transistor is turned on in response to a second gate signal transmitted on the second gate signal line, and the first light emission control transistor and the second light emission control transistor are turned on in response to a third gate signal transmitted on the third gate signal line.

Optionally, the display panel further includes:

a first active layer located at one side of the substrate, the first active layer including a first source region, a first drain region, and a first channel region located between the first source region and the first drain region;

the first conductive layer is positioned on one side of the first active layer away from the substrate, and the grid electrode of the driving transistor is positioned on the first conductive layer;

the second conductive layer is positioned at one side of the first conductive layer far away from the substrate, the first polar plate of the storage capacitor is positioned at the first conductive layer, and the second polar plate of the storage capacitor is positioned at the second conductive layer;

a third conductive layer, which is positioned on one side of the first active layer, which is close to the substrate, wherein the third conductive layer comprises a shielding layer, and the vertical projection of the shielding layer on the substrate is at least partially overlapped with the vertical projection of the first channel region on the substrate;

A fifth conductive layer, which is located at one side of the second conductive layer away from the substrate, and the first source electrode layer and the first drain electrode layer of the pixel circuit are located at the fifth conductive layer;

for the same first connecting line, the first subsection is positioned on the second conductive layer, and the second subsection is positioned on the third conductive layer or the first conductive layer;

alternatively, the first sub-segment is located in the first conductive layer, and the second sub-segment is located in the third conductive layer or the second conductive layer.

Optionally, the pixel circuit further includes a compensation transistor that is turned on in response to a first gate signal transmitted on the first gate signal line, compensating a threshold voltage of the driving transistor;

the display panel further includes:

the second conductive layer is positioned at one side of the first conductive layer far away from the substrate, and the first polar plate of the storage capacitor is positioned at the second conductive layer;

A second active layer located at one side of the second conductive layer away from the substrate, the second active layer including a second source region, a second drain region, and a second channel region located between the second source region and the second drain region;

the fourth conductive layer is positioned at one side of the second active layer away from the substrate, the grid electrode of the compensation transistor is positioned at the fourth conductive layer, and the second plate of the storage capacitor is positioned at the second conductive layer or the fourth conductive layer;

the third conductive layer is positioned on one side of the first active layer, close to the substrate, and comprises the shielding layer;

the fifth conductive layer is positioned on one side, far away from the substrate, of the fourth conductive layer, the first source electrode layer and the first drain electrode layer of the pixel circuit are positioned on the fifth conductive layer, the first source electrode layer is connected with the first source region, and the first drain electrode layer is connected with the first drain region; alternatively, a second source layer and a second drain layer of the pixel circuit are also located in the fifth conductive layer, the second source layer is connected to the second source region, and the second drain layer is connected to the second drain region;

wherein a perpendicular projection of the shielding layer on the substrate at least partially overlaps a perpendicular projection of the first channel region on the substrate and/or a perpendicular projection of the shielding layer on the substrate at least partially overlaps a perpendicular projection of the second channel region on the substrate;

For the same first connecting line, the first subsection is positioned on the second conductive layer, and the second subsection is positioned on any one layer of the third conductive layer, the first conductive layer or the fourth conductive layer;

alternatively, the first subsection is located in the first conductive layer, and the second subsection is located in any one of the third conductive layer, the second conductive layer, or the fourth conductive layer.

According to the technical scheme provided by the embodiment of the invention, the first wiring part which is positioned at the first side of the light transmission area and positioned at the display area and the second wiring part which is positioned at the second side of the light transmission area and positioned at the display area are connected through the first connecting wire, wherein the first connecting wire comprises the first subsection and the second subsection which are connected in parallel so as to reduce the impedance of the first connecting wire, thereby reducing the load difference of the first grid signal wire in the non-display area surrounding the light transmission area and the display area, being beneficial to reducing the delay of the first grid signal transmitted on the first grid signal wire, and further being beneficial to improving the problem of uneven display caused by larger signal delay on two sides of the light transmission area, and further improving the display quality.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic top view of a display panel according to an embodiment of the present invention;

fig. 2 is a schematic top view of another display panel according to an embodiment of the invention;

FIG. 3 is an enlarged schematic view of a portion of the structure of the display panel area A shown in FIG. 2;

fig. 4 is a schematic cross-sectional structure of a display panel according to an embodiment of the invention;

FIG. 5 is a schematic cross-sectional view of another display panel according to an embodiment of the invention;

FIG. 6 is a schematic cross-sectional view of another display panel according to an embodiment of the invention;

FIG. 7 is a schematic cross-sectional view of another display panel according to an embodiment of the invention;

FIG. 8 is a schematic cross-sectional view of another display panel according to an embodiment of the invention;

FIG. 9 is a schematic cross-sectional view of another display panel according to an embodiment of the invention;

Fig. 10 is a schematic cross-sectional view of another display panel according to an embodiment of the invention;

FIG. 11 is a schematic top view of another display panel according to an embodiment of the present invention;

fig. 12 is a schematic cross-sectional view of another display panel according to an embodiment of the invention;

FIG. 13 is a schematic cross-sectional view of another display panel according to an embodiment of the invention;

FIG. 14 is a schematic view of a partially enlarged structure of the display panel shown in FIG. 11;

FIG. 15 is a schematic cross-sectional view of another display panel according to an embodiment of the present invention;

fig. 16 is a schematic top view of another display panel according to an embodiment of the invention;

FIG. 17 is a schematic view of a partially enlarged structure of the display panel shown in FIG. 16;

FIG. 18 is a schematic cross-sectional view of another display panel according to an embodiment of the invention;

FIG. 19 is a schematic cross-sectional view of another display panel according to an embodiment of the invention;

fig. 20 is a schematic top view of another display panel according to an embodiment of the invention;

fig. 21 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

fig. 22 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

FIG. 23 is a schematic cross-sectional view of another display panel according to an embodiment of the present invention;

fig. 24 is a schematic cross-sectional view of another display panel according to an embodiment of the invention;

fig. 25 is a schematic cross-sectional view of another display panel according to an embodiment of the invention;

fig. 26 is a schematic cross-sectional view of another display panel according to an embodiment of the invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

As described in the background art, the existing display panel connects the gate signal lines on both sides of the hole in a wire winding manner, so that the load of the gate signal line on the hole is different from the load of the gate signal line in the normal display area, resulting in the difference in the delay of the transmission signal (the delay of the rising edge and/or the falling edge of the signal) on the signal lines on both sides of the hole, especially for a medium-and-large-sized display panel, the load difference on both sides of the hole is larger, so that the difference in the driving signal received by a plurality of pixels connected to the same gate signal line is larger, which causes the phenomenon of transverse mura (uneven display) and reduces the display effect.

In view of the foregoing, embodiments of the present invention provide a display panel. Fig. 1 is a schematic top view of a display panel according to an embodiment of the present invention, and referring to fig. 1, the display panel provided in this embodiment includes a light-transmitting region 10, a non-display region 20 at least partially surrounding the light-transmitting region 10, and a display region 30 at least partially surrounding the non-display region 20. The light-transmitting area 10 is a hole, and the hole may be a through hole. The light-transmitting region 10 is located in the display region 30, and a non-display region 20 surrounding the light-transmitting region 10 is disposed around the light-transmitting region 10, the non-display region 20 being used for wiring to connect signal lines on both sides of the light-transmitting region 10. Here, both sides of the light-transmitting region 10 may refer to the first side and the second side of the light-transmitting region 10 in the X-direction, and may also refer to the first side and the second side of the light-transmitting region 10 in the Y-direction.

Fig. 2 is a schematic top view of another display panel according to an embodiment of the present invention, specifically, a schematic top view of a light-transmitting area 10 and a wiring around a non-display area 20 of the light-transmitting area 10, and fig. 3 is an enlarged schematic view of a part of the structure of the display panel area a shown in fig. 2, and referring to fig. 2 and 3, the display panel further includes a plurality of first gate signal lines 11 extending along a first direction, and the plurality of first gate signal lines 11 are arranged along a second direction. The first direction may be an X direction, and the second direction may be a Y direction. In the X direction, the first gate signal line 11 extends directly from the left side to the right side of the display panel within the display region 30 that does not pass through the light-transmitting region 10. At the position of the light-transmitting area 10, the first gate signal line 11 includes a first trace portion 101 located at a first side of the light-transmitting area 10 (e.g., a left side of the display panel) and located at the display area 30, and a second trace portion 102 located at a second side of the light-transmitting area 10 (e.g., a right side of the display panel) and located at the display area 30, and both the first trace portion 101 and the second trace portion 102 extend from the display area 30 to the non-display area 20 surrounding the light-transmitting area 10.

The first gate signal line 11 further includes a first connection line 103 located in the non-display region 20, the first connection line 103 for connecting the first and second routing parts 101 and 102 so that a gate signal can be transmitted from the first routing part 101 to the second routing part 102.

With continued reference to fig. 3, in the present embodiment, the first connection line 103 includes the first sub-segment 113 and the second sub-segment 123 connected in parallel to increase the cross-sectional area of the first connection line 103, and the impedance of the first connection line 103 formed by the connection structure in which the first sub-segment 113 and the second sub-segment 123 are connected in parallel to each other is lower than the first connection line 103 adopting a single wiring, so that the impedance difference of the first gate signals transmitted by the first gate signal lines 11 on both sides of the light-transmitting area 10 can be reduced, and the delay difference of the gate signals on both sides of the light-transmitting area 10 can be reduced to improve the display effect of the pixels on both sides of the light-transmitting area 10.

According to the technical scheme provided by the embodiment of the invention, the first wiring part 101 which is positioned at the first side of the light transmission area 10 and positioned at the display area 30 and the second wiring part 102 which is positioned at the second side of the light transmission area 10 and positioned at the display area 30 are connected through the first connecting wire 103, wherein the first connecting wire 103 comprises the first subsection 113 and the second subsection 123 which are connected in parallel so as to reduce the impedance of the first connecting wire 103, thereby reducing the load difference of the first grid signal wire 11 in the non-display area 20 surrounding the light transmission area 10 and the display area 30, being beneficial to reducing the delay of the first grid signal transmitted on the first grid signal wire 11, and further being beneficial to improving the problem of uneven display caused by larger signal delay at two sides of the light transmission area 10, and improving the display quality.

Fig. 4 is a schematic cross-sectional structure of a display panel according to an embodiment of the present invention, and specifically, a cross-sectional structure of the display panel shown in fig. 3 along a cutting line BB'. Referring to fig. 3 and 4, in an alternative embodiment, the display panel includes a substrate 40, and a plurality of conductive layers stacked on one side of the substrate 40, and the first and second sub-segments 113 and 123 are disposed on different conductive layers. For example, the first trace portion 101 and the second trace portion 102 are located on the same conductive layer, the first sub-segment 113 may be disposed on the same layer as the first trace portion 101, and the second sub-segment 123 may be located on a different conductive layer than the first sub-segment 113. Because the first sub-segment 113 and the second sub-segment 123 are different layers, the space between the first sub-segment 113 and the second sub-segment 123 can be greatly reduced on the horizontal plane of the Y direction, and the first sub-segment 113 and the second sub-segment 123 which are positioned on different conductive layers can even overlap together under specific conditions, so as to reduce the occupied area of the first connecting line 103, which is beneficial to realizing high PPI.

Fig. 5 is a schematic cross-sectional structure of another display panel according to an embodiment of the present invention, and referring to fig. 5, based on the above technical solutions, optionally, the first subsection 113 may be located in a different conductive layer from the first routing portion 101, and the second subsection 123 may also be located in a different conductive layer from the first routing portion 113. Illustratively, the first sub-segment 113 and the second sub-segment 123 are connected through a via, and after the first sub-segment 113 and the second sub-segment 123 are connected in parallel, the first sub-segment 113 and the second sub-segment 123 are respectively connected with the first routing portion 113 and the second routing portion 123 through the via, and since the first sub-segment 113 and the second sub-segment 123 are different from the first routing portion 101, the wiring space of the first sub-segment 113 or the second sub-segment 123 can be increased, which is beneficial to simplifying the process.

Fig. 6 is a schematic cross-sectional structure of another display panel according to an embodiment of the present invention, and fig. 7 is a schematic cross-sectional structure of another display panel according to an embodiment of the present invention, referring to fig. 6 and fig. 7, based on the above technical solutions, optionally, the multiple conductive layers include a first conductive layer M1 and a second conductive layer M2, where the first conductive layer M1 is located on one side of the substrate 40, and the second conductive layer M2 is located on one side of the first conductive layer M1 away from the substrate 40. The multi-layer conductive layer further includes a third conductive layer M3, and the third conductive layer M3 is located on a side of the first conductive layer M1 close to the substrate 10, that is, in the thickness direction Z of the display panel, the first conductive layer M1 is interposed between the second conductive layer M2 and the third conductive layer M3. Wherein, the first wiring portion 101 and the second wiring portion 102 are located in the first conductive layer M1; the first subsection 113 may be located in the first conductive layer M1 or in the second conductive layer M2, and the second subsection 123 is located in the third conductive layer M3.

In this embodiment, the third conductive layer M3 is a film layer where a shielding layer in the pixel circuit is located, where the shielding layer is used for shielding a transistor in the pixel circuit, so as to meet the requirements of the display panel on reliability and display effect. By arranging the second subsections 123 on the third conductive layer M3, the number of masks and development cost are not increased, the problem of wiring load difference at two sides of the light transmission area 10 can be improved by utilizing the existing film layer, the process difficulty is not increased, and the implementation is easy.

Fig. 8 is a schematic cross-sectional structure of another display panel according to an embodiment of the present invention, and referring to fig. 8, based on the above technical solutions, optionally, the multiple conductive layers may further include a fourth conductive layer M4, where the fourth conductive layer M4 is located on a side of the second conductive layer M2 away from the substrate 10. The second subsection 123 may also be located in a fourth conductive layer M4.

Specifically, in the LTPO (Low Temperature Polycrystalline Oxide, low temperature polysilicon and oxide) pixel circuit, the active layer of the silicon-based transistor and the active layer of the metal oxide transistor are located in different layers, and the gates corresponding to the two layers are also located in different layers. The first conductive layer M1 may be a film layer where a gate of the silicon-based transistor is located, and the fourth conductive layer M4 may be a film layer where a gate of the metal oxide transistor is located. The second subsection 123 of the fourth conductive layer M4 is parallel to the first subsection 113 of the first conductive layer M1 or the second conductive layer M2, so that the impedance of the first connecting line 103 can be reduced, and the fourth conductive layer M4 is an existing film layer, and no additional conductive layer is needed to be prepared, thereby being beneficial to the realization of the process.

Fig. 9 is a schematic cross-sectional structure of another display panel according to an embodiment of the present invention, specifically, a cross-sectional structure of the display panel shown in fig. 2 along a cutting line CC', and referring to fig. 2 and 9, based on the above technical solutions, optionally, in a non-display area 20 at least partially surrounding a light-transmitting area 10, vertical projections of a first sub-segment 113 on a substrate 40 and vertical projections of a second sub-segment 123 on the substrate 40 are staggered. The staggered arrangement may refer to a non-overlapping portion of the perpendicular projection of the first sub-segment 113 onto the substrate 40 and the perpendicular projection of the second sub-segment 123 onto the substrate 40, or may refer to a partial overlap between the perpendicular projection of the first sub-segment 113 onto the substrate 40 and the perpendicular projection of the second sub-segment 123 onto the substrate 40. Optionally, the perpendicular projection of the first subsection 113 onto the substrate 40 and the perpendicular projection of the second subsection 123 onto the substrate 40 do not overlap. The purpose of this is to reduce mutual interference between the first and second sub-segments 113 and 123, and to prevent the mutual interference of signals on both the first and second sub-segments 113 and 123 during signal transmission from causing signal fluctuations, which is detrimental to the driving of the pixel circuit.

Fig. 10 is a schematic cross-sectional view of another display panel according to an embodiment of the present invention, and referring to fig. 6 to 10, alternatively, the first subsections 113 corresponding to two adjacent first gate signal lines 11 are located on different conductive layers. Illustratively, the first subsections 113 of each first gate signal line 11 are arranged in such a manner that the first conductive layers M1 and the second conductive layers M2 alternate. That is, two adjacent first gate signal lines 11, wherein the first subsection 113 of one first gate signal line 11 is located on the first conductive layer M1, and the first subsection 113 of the other first gate signal line 11 is located on the second conductive layer M2, so as to save the arrangement space of the first subsection 113, and simultaneously, improve the impedance of the adjacent first gate signal lines 11. The second subsection 123 of the same first gate signal line 11 is disposed at a different layer from the first subsection 113.

Alternatively, in the above embodiments, the third conductive layer M3 and the fourth conductive layer M4 may exist at the same time, or only the third conductive layer M3 or only the fourth conductive layer M4 may be formed according to practical situations.

Fig. 11 is a schematic top view of another display panel according to an embodiment of the present invention, and referring to fig. 11, based on the above technical solutions, optionally, the display panel provided in this embodiment further includes a plurality of second gate signal lines 12, where the second gate signal lines 12 are disposed in the same manner as the first gate signal lines 11. The second gate signal line 12 includes a third trace portion 201 located on the first side of the light-transmitting region 10 and located in the display region 30, and a fourth trace portion 202 located on the second side of the light-transmitting region 10 and located in the display region 30, and the second gate signal line 12 further includes a second connection line 203 located in the non-display region 20, where the third trace portion 201 and the fourth trace portion 202 are connected by the second connection line 203.

Fig. 12 is a schematic cross-sectional structure of another display panel according to an embodiment of the present invention, specifically, a cross-sectional structure of the display panel shown in fig. 11 along a cutting line DD', referring to fig. 11 and 12, the second connecting line 203 includes a third subsection 213, and the third wiring portion 201 and the fourth wiring portion 202 may be connected through the third subsection 213. The third subsection 213 may be disposed on the same layer as the first subsection 113, which is beneficial to saving the occupied space of the film layer. Of course, in other embodiments, the third subsection 213 may be disposed in a different layer from the first subsection 113, which is beneficial to optimizing the wiring space and simplifying the wiring process.

Fig. 13 is a schematic cross-sectional structure of another display panel according to an embodiment of the invention, referring to fig. 13, in the present embodiment, adjacent first gate signal lines 11 and second gate signal lines 12, third sub-segment 213 and first sub-segment 113 are located in different conductive layers, so as to increase a wiring space and prevent signal interference between third sub-segment 213 and first sub-segment 113. Illustratively, the first subsection 113 may be located in a first conductive layer M1, the second subsection 123 in a third conductive layer M3, and the third subsection 213 in a second conductive layer M2. In the Y-direction, the perpendicular projection of the third sub-segment 213 onto the substrate 40 does not overlap with the perpendicular projection of the first sub-segment 113 onto the substrate 40.

Alternatively, the third sub-segment 213 may be located at the first conductive layer M1 when the first sub-segment 113 is located at the second conductive layer M2.

Fig. 14 is a schematic diagram of a partial enlarged structure of the display panel shown in fig. 11, and referring to fig. 11 and 14, based on the above technical solution, optionally, the second connection line 203 further includes a fourth subsection 223, and the fourth subsection 223 is connected in parallel with the third subsection 213, so as to reduce the impedance of the second connection line 203, improve the delay phenomenon of the second gate signal transmitted on the second gate signal line 12, and its specific working principle is the same as that of the first connection line 103, and will not be repeated.

Fig. 15 is a schematic cross-sectional structure of another display panel according to an embodiment of the invention, referring to fig. 14 and 15, in this embodiment, a fourth subsection 223 may be disposed on the same layer as the second subsection 123, for example, the fourth subsection 223 and the second subsection 123 are both located on the third conductive layer M3, and the third wiring portion 201 and the fourth wiring portion 202 are laterally (X-direction) connected by using the existing conductive layer.

Fig. 16 is a schematic top view of another display panel according to an embodiment of the present invention, referring to fig. 16, based on the above technical solutions, optionally, the display panel further includes a plurality of third gate signal lines 13, the third gate signal lines 13 are arranged in the same manner as the first gate signal lines 11 and the second gate signal lines 12, and the vertical projection of the first gate signal lines 11 on the substrate 40 is between the vertical projection of the second gate signal lines 12 on the substrate 40 and the vertical projection of the third gate signal lines 13 on the substrate 40. The third gate signal line 13 may be used to transmit a third gate signal. The third gate signal line 13 includes a fifth trace portion 301 located at a first side of the light-transmitting region 10 and located at the display region 30, and a sixth trace portion 302 located at a second side of the light-transmitting region 10 and located at the display region 30, the fifth trace portion 301 and the sixth trace portion 302 being connected by a third connection line 303, the third connection line 303 being located in the non-display region 20 disposed around the light-transmitting region 10.

Fig. 17 is a partially enlarged structural schematic view of the display panel shown in fig. 16, referring to fig. 16 and 17, the third connection line 303 includes a fifth sub-section 313 and a sixth sub-section 323, and the fifth sub-section 313 and the sixth sub-section 323 are connected in parallel, for example, the fifth sub-section 313 and the sixth sub-section 323 are connected in parallel through a via hole. In the present embodiment, the second gate signal line 12, the first gate signal line 11, and the third gate signal line 13 are alternately arranged in order along the Y direction, and the second gate signal line 12, the first gate signal line 11, and the third gate signal line 13 are grouped together to drive one row of pixels. At least two of the first subsection 113 corresponding to the first gate line number 11, the third subsection 213 corresponding to the second gate signal line 12, and the fifth subsection 313 corresponding to the third gate signal line 13 are located on different conductive layers so as to reduce interference between the different subsections. For example, the first subsection 113 is located solely in one conductive layer and the third subsection 213 and the fifth subsection 313 are located in the same conductive layer. That is, the connection sub-segments of two adjacent connection lines are different layers, so as to reduce the occupation space of the connection lines in the non-display area 20, which is beneficial to wiring design. In addition, the line width of each sub-segment is also beneficial to flexibly setting so as to reduce the impedance of the connecting line, improve the load difference between the grid signal lines at two sides of the light transmission area 10 and the grid signal lines in the normal display area 30, reduce the signal attenuation or the signal delay of the grid signal, and be beneficial to improving the display effect. At the same time, the frame of the non-display area 20 disposed around the light-transmitting area 10 is advantageously reduced, and the area of the display area 30 is advantageously increased.

Of course, in other embodiments, the first sub-segment 113, the third sub-segment 213, and the fifth sub-segment 313 are each located in different conductive layers.

Fig. 18 is a schematic cross-sectional structure of another display panel according to an embodiment of the present invention, and referring to fig. 18, a fifth subsection 313 may be disposed on the same layer as the third subsection 213 and located on the second conductive layer M2; the sixth sub-segment 323 can be arranged in the same layer as the second sub-segment 123, and is located on the third conductive layer M3, and the vertical projections of the sub-segments on the substrate 40 do not overlap each other.

As a preferred implementation manner of this embodiment, fig. 19 is a schematic cross-sectional structure of another display panel provided by this embodiment, and referring to fig. 16 to fig. 19, the second connection line 203 and the third connection line 303 are both single-layer wires, where the second connection line 203 includes a third subsection 213, and the third connection line 303 includes a fifth subsection 313; the first connection line 103 is a double-layer wiring, and the first connection line 103 includes a first sub-section 113 and a second sub-section 123, and the first sub-section 113 and the second sub-section 123 are connected in parallel. Specifically, for the plurality of first connection lines 103, second connection lines 203, and third connection lines 303, it is possible to divide into a plurality of groups, each of which includes the second connection lines 203, the first connection lines 103, and the third connection lines 303 arranged in order. Wherein the third sub-segment 213, the first sub-segment 113 and the fifth sub-segment 313 are arranged in such a way that the first conductive layer M1 and the second conductive layer M2 alternate lines. That is, in the first group, the third sub-segment 213 is located at the first conductive layer M1, the first sub-segment 113 is located at the second conductive layer M2, and the fifth sub-segment 313 is located at the first conductive layer M1; in the second group, the third subsection 213 is located at the second conductive layer M2, the first subsection 113 is located at the first conductive layer M1, the fifth subsection 313 is located at the second conductive layer M2 … …, and so on. For the second sub-segments 213, each second sub-segment 213 may be located in the same conductive layer, e.g., the second sub-segment 213 is located in a third conductive layer M3, the third conductive layer M3 being a different conductive layer than the first conductive layer M1 and the second conductive layer M2. By the arrangement, on the basis of optimizing the wiring space, the load difference of the first gate signal line 11 in the non-display area 20 and the display area 30 surrounding the light transmission area 10 can be reduced, the delay of the first gate signal transmitted on the first gate signal line 11 is reduced, and the problem of uneven display caused by larger signal delay on two sides of the light transmission area 10 is further solved.

It should be noted that, in the specific implementation process, only the first connection line 103 may be in a parallel connection line structure, and the second connection line 203 and the third connection line 303 may be in a single-layer line structure; at least two of the first connection line 103, the second connection line 203 and the third connection line 303 may be in a parallel connection structure, which may be specifically set according to practical situations.

Fig. 20 is a schematic top view of another display panel according to an embodiment of the present invention, referring to fig. 20, optionally, the display panel further includes a plurality of data lines DL, the data lines DL extend along a second direction in the display area and are arranged along a first direction, the data lines DL include a first data line DL1 and a second data line DL2, the first data line DL1 and the second data line DL2 are alternately arranged along the first direction, the first data line DL1 includes a first connection portion 41 located in the non-display area 20, the second data line DL2 includes a second connection portion 42 located in the non-display area 20, and the first connection portion 41 and the second connection portion 42 are located in different layers. The first data line DL1 may be connected to the pixels of the odd columns, and the second data line DL2 may be connected to the pixels of the even columns, which is beneficial to improving the load difference on each data line DL.

Alternatively, in the present embodiment, the vertical projection of the first data line DL1 on the substrate 40 is staggered with the vertical projection of the second data line DL2 on the substrate 40. The staggered arrangement means that the perpendicular projection of the first data line DL1 on the substrate 40 and the perpendicular projection of the second data line DL2 on the substrate 40 may or may not overlap. Optionally, the perpendicular projection of the first data line DL1 on the substrate 40 does not overlap with the perpendicular projection of the second data line DL2 on the substrate 40.

Optionally, the first connection portion 41 of the first data line DL1 in the non-display area 20 and the first sub-segment 113 of the first connection line 103 are located in different conductive layers, and/or the second connection portion 42 of the second data line DL2 in the non-display area 20 and the first sub-segment 113 of the first connection line 103 are located in different conductive layers.

Optionally, the display panel further includes a plurality of pixel circuits arranged in an array, each pixel circuit corresponding to a light emitting diode, and the pixel circuits are configured to drive the light emitting diodes to emit light according to the gate signals transmitted on the first gate signal line 11, the second gate signal line 12, and the third gate signal line 13. Fig. 21 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention, referring to fig. 20 and 21, the pixel circuit at least includes a data writing transistor Q4, a driving transistor Q1 and a storage capacitor Cs, wherein the data writing transistor Q4 is connected between a data line DL and the driving transistor Q1, and is used for writing a data voltage transmitted on the data line DL to a gate of the driving transistor Q1, the driving transistor Q1 and the light emitting diode D1 are connected between a first power line and a second power line, the first power line can transmit a first power voltage VDD, the second power line can transmit a second power voltage VSS, one of the first power voltage VDD and the second power voltage VSS is at a high level, and the other is at a low level. The storage capacitor Cs is connected between the first power line and the gate of the driving transistor Q1, and is used for storing the gate voltage of the driving transistor Q1.

In the present embodiment, the first gate signal line 11 is connected to the gate of the data writing transistor Q4 for transmitting the first gate signal S1 to the gate of the data writing transistor Q4.

Optionally, with continued reference to fig. 20 and 21, the pixel circuit further includes a first initialization transistor Q2, a first light emitting control transistor Q6, and a second light emitting control transistor Q7, the first initialization transistor Q2 being connected to the gate of the driving transistor Q1, the second pole of the light emitting diode D1 being connected to the second power line; the first light emitting control transistor Q6 is connected between the first power line and the first pole of the driving transistor Q1, and the second light emitting control transistor Q7 is connected between the second pole of the driving transistor Q1 and the first pole of the light emitting diode D1. The display panel further includes a second gate signal line 12 and a third gate signal line 13, the first initialization transistor Q2 is turned on in response to the second gate signal S2 transmitted on the second gate signal line 12, the first initialization voltage Vref1 is transmitted to the gate of the driving transistor Q1, the gate of the driving transistor Q1 is initialized, and the first and second light emission control transistors Q6 and Q7 are turned on in response to the third gate signal S3 transmitted on the third gate signal line 13.

Optionally, the pixel circuit further includes a second initializing transistor Q3, where the second initializing transistor Q3 is connected to the first pole of the light emitting diode D1, and is configured to transmit the second initializing voltage Vref2 to the first pole of the light emitting diode D1 in response to the control signal on the gate thereof. For example, the second initializing transistor Q3 may be connected to the fourth gate signal line in response to the fourth gate signal S4 on the fourth gate signal line. The fourth gate signal line connected to the second initializing transistor Q3 of the pixel circuit of the present row is multiplexed to the second gate signal line connected to the first initializing transistor Q2 of the pixel circuit of the next row, that is, the first initializing transistor Q2 and the second initializing transistor Q3 in two adjacent rows of pixel circuits share the same gate signal line. The fourth scan signal S4 may be the same as or different from the second scan signal S2. Alternatively, the second gate signal line to which the first initialization transistor Q2 is connected is multiplexed as the fourth gate signal line.

The first initialization transistor Q2 and the compensation transistor Q5 shown in fig. 21 are P-type transistors. Alternatively, the first initializing transistor Q2 and/or the compensating transistor Q5 may be N-type transistors. Fig. 22 is a schematic diagram of a pixel circuit according to another embodiment of the present invention, as shown in fig. 22, when the first initializing transistor Q2 and the compensating transistor Q5 are N-type transistors, the gate signals of the data writing transistor Q4 and the compensating transistor Q5 are opposite. For example, the gate of the data writing transistor Q4 is connected to the first gate signal line, and the gate of the compensation transistor Q5 is connected to the other gate signal line (e.g., the fifth gate signal line, on which the gate signal S1' is transmitted).

Fig. 23 is a schematic cross-sectional structure of another display panel according to an embodiment of the present invention, specifically, a cross-sectional structure of the display panel shown in fig. 20 along a cutting line EE', and in combination with fig. 20-23, the display panel includes:

a substrate 40;

a first active layer 502 on one side of the substrate 40, the first active layer 502 including a first source region SR1, a first drain region DR1, and a first channel region CR1 between the first source region SR1 and the first drain region DR 1; wherein, a first buffer layer 51 and a second buffer layer 52 are further disposed between the first active layer 502 and the substrate 40, and the second buffer layer 52 is located at a side of the first buffer layer 51 away from the substrate 40.

The first gate insulating layer 53 is located at a side of the first active layer 502 remote from the substrate 40, and the first gate insulating layer 53 covers the first active layer 502.

The first conductive layer M1 is located on a side of the first active layer 502 away from the substrate 40, and the first conductive layer M1 may include at least a portion of a gate of a transistor. For example, the gate 503 of the driving transistor Q1 is located in the first conductive layer M1.

The capacitor insulating layer 54 is located on the side of the first conductive layer M1 away from the substrate 40.

The second conductive layer M2 is located on a side of the first conductive layer M1 away from the substrate 40, and may specifically be located on a side of the first capacitive insulating layer 54 away from the substrate 40. The first electrode 511 of the storage capacitor Cs is located on the first conductive layer M1, and the second electrode 512 is located on the second conductive layer M2, where the first electrode 511 may be a lower electrode of the storage capacitor Cs, and the second electrode 512 may be an upper electrode of the storage capacitor Cs.

The first interlayer insulating layer 55 is located on the side of the second conductive layer M2 away from the substrate 40.

The third conductive layer M3 is located on the side of the first active layer 502 close to the substrate 40, and may specifically be located between the substrate 40 and the first buffer layer 51, or may be located between the first buffer layer 51 and the second buffer layer 52. The shielding layer 501 is located on the third conductive layer M3, and a vertical projection of the shielding layer 501 on the substrate 40 at least partially overlaps with a vertical projection of the first channel region CR1 on the substrate 40, so as to shield the first channel region CR1 and prevent external illumination or ions on the substrate 40 from adversely affecting the first channel region CR 1.

The fifth conductive layer M5 is located on a side of the second conductive layer M2 away from the substrate 40, and may specifically be located on a side of the first interlayer insulating layer 55 away from the substrate 40. The first source layer 504 and the first drain layer 505 of the pixel circuit are located in the fifth conductive layer M5. The first source layer 504 is connected to the first source region SR1 of the first active layer 502, and the first drain layer 505 is connected to the first drain region DR1 of the first active layer 502.

The display panel further includes a planarization layer 56 located on a side of the fifth conductive layer M5 remote from the substrate 40. An anode 601 is located on a side of the planarization layer 56 remote from the substrate, the anode 601 being connected to the first source layer 504 or the first drain layer 505. The pixel defining layer 57 is disposed on a side of the planarization layer 56 away from the substrate 40, the pixel defining layer 57 includes an opening exposing the anode 601, a light emitting layer 602 is evaporated in the opening, a cathode 603 is disposed on a side of the pixel defining layer 57 away from the substrate 40, and the cathode 603 is connected to the light emitting layer 602. The anode 601, the light emitting layer 602, and the cathode 603 collectively form a light emitting diode D1.

In this embodiment, for the first connection line 103 in the non-display area 20, the first subsection 113 may be located in the first conductive layer M1 or the second conductive layer M2, and the second subsection 123 may be located in the third conductive layer M3, and is disposed in the same layer as the shielding layer 501, so as to be beneficial to optimizing the wiring space of each subsection. Wherein, for the same first connection line 103, when the first subsection 113 is located in the second conductive layer M2, the second subsection 123 may be located in the first conductive layer M1, and the second subsection 123 is disposed by using the third conductive layer M3, which has the same beneficial effect.

The first connection portion 41 of the first data line DL1 may be located at the second conductive layer M2, and the second connection portion 42 of the second data line DL2 may be located at the fifth conductive layer M5.

Alternatively, the positions of the second connection line 203 and the third connection line 303 may be set with reference to the first connection line 103. For example, fig. 24 is a schematic cross-sectional structure of another display panel according to an embodiment of the present invention, specifically, a cross-sectional structure of the display panel shown in fig. 20 along a cutting line DD', when the second connection line 203 and the third connection line 303 are both single-layer wires, that is, the second connection line 203 includes a third sub-segment 213, the third connection line 303 includes a fifth sub-segment 313, the third sub-segment 213, the first sub-segment 113 and the fifth sub-segment 313 are arranged in a manner that the first conductive layer M1 and the second conductive layer M2 alternate wires, and the second sub-segment 213 is located in the third conductive layer M3. Here, the second connection line 203 and the third connection line 303 adopt a single-layer wiring manner, which is favorable for saving wiring space, and is convenient for setting other wirings so as to simplify the wiring process.

Alternatively, when the second connection line 203 includes the third sub-section 213 and the fourth sub-section 223, the fourth sub-section 223 may be disposed in the same layer as the second sub-section 123. And/or when the third connecting line 303 comprises a fifth subsection 313 and a sixth subsection 323. The sixth sub-segment 323 may be arranged in the same layer as the second sub-segment 123. The scheme can be favorable for the parallel subsection of the existing third conductive layer M3 serving as a connecting wire, so that the impedance of each connecting wire is reduced, the problem of uneven display caused by larger signal delay on two sides of a light transmission area is solved, and the number and development cost of photomasks are not required to be increased in the preparation process.

Fig. 25 is a schematic cross-sectional structure of another display panel according to an embodiment of the present invention, specifically, another cross-sectional structure of the display panel shown in fig. 20 along a cutting line EE', and in combination with fig. 20-25, the display panel further includes, based on the structure shown in fig. 22:

the second active layer 701 is located on a side of the second conductive layer M2 away from the substrate 40, specifically on a side of the first interlayer insulating layer 55 away from the substrate 40. The second active layer 701 includes a second source region SR2, a second drain region DR2, and a second channel region CR2 between the second source region SR2 and the second drain region DR 2;

The fourth conductive layer M4 is located on the side of the second active layer 701 away from the substrate 40, the gate 702 of the compensation transistor Q5 is located on the fourth conductive layer M4, and the second plate 512 of the storage capacitor Cs is located on the second conductive layer M2 or the fourth conductive layer M4. When the second plate 512 of the storage capacitor Cs is located in the fourth conductive layer M4, the first plate 511 thereof may also be located in the second conductive layer M2.

The second source layer 703 and the second drain layer 704 of the pixel circuit are also located in the fifth conductive layer M5 and are arranged in the same layer as the first source layer 504 and the first drain layer 505. The second source layer 703 is connected to the second source region SR2, and the second drain layer 704 is connected to the second drain region DR 2.

In this embodiment, the material of the first active layer 502 may be polysilicon, and the material of the second active layer 701 may be a metal oxide, such as indium gallium zinc oxide. The first active layer 502 may be an active layer of the driving transistor Q1, and the second active layer 502 may be an active layer of the compensation transistor Q5 to reduce leakage current of the compensation transistor Q5. A shielding layer 501 may be disposed below the second channel region CR2 for shielding. Here, the second active layer 502 may also serve as an active layer of the first initialization transistor Q2 at the same time, and the gate electrode of the first initialization transistor Q2 is also located on the fourth conductive layer M4.

In this embodiment, for the first connection line 103 in the non-display area 20, the first subsection 113 may be located in the first conductive layer M1 or the second conductive layer M2, and the second subsection 123 may be located in the third conductive layer M3 or the fourth conductive layer M4. The second subsection 123 may also be located in the first conductive layer M1 when the first subsection 113 is located in the second conductive layer M2.

The first connection portion 41 of the first data line DL1 may be located at the fourth conductive layer M4, and the second connection portion 42 of the second data line DL may be located at the fifth conductive layer M5. Of course, in other embodiments, the first connection portion 41 and the second connection portion 42 may also be located in other conductive layers, which is not limited in this embodiment.

Fig. 26 is a schematic cross-sectional structure of another display panel according to an embodiment of the present invention, specifically, another cross-sectional structure of the display panel shown in fig. 20 along a cutting line DD', referring to fig. 26, when the second connection line 203 and the third connection line 303 are both single-layer wires, that is, the second connection line 203 includes a third sub-section 213, the third connection line includes a fifth sub-section 313, the third sub-section 213 and the fifth sub-section 313 may be located in the first conductive layer M1, the first sub-section 113 is located in the second conductive layer M2, and the second sub-section 213 is located in the fourth conductive layer M4.

Alternatively, when the second connection line 203 includes the three sub-segments 213 and the fourth sub-segment 223, the fourth sub-segment 223 may be disposed in the same layer as the second sub-segment 123. And/or when the third connecting line 303 comprises a fifth subsection 313 and a sixth subsection 323. The sixth sub-section 323 may be arranged in the same layer as the second sub-section 123, and the fourth sub-section 223 and/or the sixth sub-section 323 may also be located in the third conductive layer M3. The scheme can be favorable for the parallel subsection of the existing third conductive layer M3 and/or fourth conductive layer M4 serving as connecting wires, so that the impedance of each connecting wire is reduced, the problem of uneven display caused by larger signal delay on two sides of a light transmission area is solved, and the number of masks and development cost are not required to be increased in the preparation process.

As another alternative implementation of this embodiment, the third subsection 213, the first subsection 113 and the fifth subsection 313 may also be arranged in a manner that the third conductive layer M3 and the first conductive layer M1 alternate with each other, and the second subsection 213 may be located in the second conductive layer M2; alternatively, the third sub-section 213, the first sub-section 113 and the fifth sub-section 313 are arranged in such a manner that the fourth conductive layer M4 and the first conductive layer M1 alternate with each other, and the second sub-section 213 may be located at the second conductive layer M2. Can also achieve the benefits described in any of the embodiments above.

Note that the cross-sectional structures of the display panels shown in fig. 23 and 24 may correspond to the pixel circuit shown in fig. 21, and the cross-sectional structures of the display panels shown in fig. 25 and 26 may correspond to the pixel circuit shown in fig. 22.

In the above-described embodiments, the second sub-segment 123 is not generally disposed on the fifth conductive layer M5 in order to reduce the interference to the data line DL. Of course, the second subsection 123 may also be provided at the fifth conductive layer M5 in case the wiring space of the fifth conductive layer M5 is sufficiently large.

The inventor has verified through experiments that, by adopting the technical solutions in the above embodiments, the delay difference of the first gate signal S1 transmitted on the first gate signal line 11 can be reduced to at least 5%, so that the phenomenon of uneven display on both sides of the light-transmitting area 10 of the display panel can be greatly improved, and the improvement of the display quality is facilitated.

Alternatively, the display panel may be applied to any electronic product having a display function, including but not limited to the following categories: the embodiment of the invention is not particularly limited to a mobile phone, a television, a notebook computer, a desktop display, a tablet computer, a digital camera, an intelligent bracelet, intelligent glasses, a vehicle-mounted display, medical equipment, industrial control equipment, a touch interaction terminal and the like.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims

1. A display panel comprising a light transmissive region, a non-display region at least partially surrounding the light transmissive region, and a display region at least partially surrounding the non-display region, the display panel further comprising:

a substrate;

the first grid signal lines are positioned on one side of the substrate, extend in the first direction in the display area and are distributed in the second direction, each first grid signal line comprises a first wiring part positioned on the first side of the light transmission area and positioned in the display area and a second wiring part positioned on the second side of the light transmission area and positioned in the display area, and the first wiring part and the second wiring part extend to the non-display area; the first direction and the second direction are crossed and are perpendicular to the thickness direction of the display panel;

2. The display panel according to claim 1, wherein the display panel includes a plurality of conductive layers stacked on one side of the substrate;

preferably, in the same first gate signal line, the first subsection and the first wiring portion are located on the same conductive layer; or alternatively, the process may be performed,

preferably, the first sub-section and the second sub-section are connected through a via hole, and the first wiring portion and the second wiring portion are arranged in the same layer.

3. The display panel of claim 2, wherein the multi-layer conductive layer comprises a first conductive layer on the substrate side and a second conductive layer on the first conductive layer side away from the substrate side;

4. A display panel according to claim 3, characterized in that in the non-display area at least partly surrounding the light-transmitting area, the perpendicular projections of the first sub-segment on the substrate and the perpendicular projections of the second sub-segment on the substrate are staggered.

5. The display panel according to claim 3, wherein the first subsections corresponding to two adjacent first gate signal lines are located in different conductive layers, and the second subsections corresponding to two adjacent first gate signal lines are located in the same conductive layer;

preferably, the first subsections corresponding to the first gate signal lines are arranged in a mode that the first conductive layers and the second conductive layers alternate with each other to replace lines.

6. The display panel according to any one of claims 1 to 5, further comprising a plurality of second gate signal lines;

preferably, the third wiring part and the first wiring part are arranged on the same layer;

preferably, the second gate signal lines and the first gate signal lines are alternately arranged, and the third sub-segment and the first sub-segment are located in different conductive layers in adjacent first gate signal lines and second gate signal lines.

7. The display panel of claim 6, wherein the second connection line further comprises a fourth sub-segment, the third sub-segment and the fourth sub-segment being located at different layers and connected in parallel;

preferably, the fourth subsection is arranged in layers with the second subsection.

8. The display panel of claim 6, further comprising a plurality of third gate signal lines, a vertical projection of the first gate signal lines on the substrate being between a vertical projection of the second gate signal lines on the substrate and a vertical projection of the third gate signal lines on the substrate, the third gate signal lines including a fifth trace portion on a first side of the light transmissive region and on the display region and a sixth trace portion on a second side of the light transmissive region and on the display region, the third gate signal lines further including a third connection line on the non-display region, the third connection line including a fifth subsection, the fifth trace portion being connected to the sixth trace portion through the fifth subsection;

the second gate signal line, the first gate signal line and the third gate signal line are sequentially and alternately arranged, and at least two of the first subsection, the third subsection and the fifth subsection are positioned on different conductive layers;

9. The display panel of claim 8, wherein the third connection line further comprises a sixth subsection, the fifth subsection and the sixth subsection being located at different layers and connected in parallel;

preferably, the sixth subsection is arranged in layers with the second subsection.

10. The display panel of claim 1, wherein the display panel comprises,

the display panel further comprises a plurality of data lines, the data lines extend in the second direction in the display area and are distributed in the first direction, the data lines comprise first data lines and second data lines, the first data lines and the second data lines are alternately distributed, the first data lines comprise first connecting parts located in the non-display area, the second data lines comprise second connecting parts located in the non-display area, and the first connecting parts and the second connecting parts are located in different layers;

preferably, the first connection and/or the second connection is located in a different layer than the first subsection.

11. The display panel according to claim 1, further comprising a pixel circuit and a light emitting diode, wherein the pixel circuit comprises a data writing transistor, a driving transistor, and a storage capacitor, wherein the data writing transistor is connected between a data line and the driving transistor, wherein the driving transistor and the light emitting diode are connected between a first power line and a second power line, and wherein the storage capacitor is connected between the first power line and a gate electrode of the driving transistor;

preferably, the display panel further includes a shielding layer, the shielding layer being located at a side of the pixel circuit, where the gate of the driving transistor is close to the substrate;

preferably, the second subsection is arranged in the same layer as the shielding layer.

12. The display panel according to claim 11, wherein the pixel circuit further comprises a first initialization transistor, a first light emission control transistor, and a second light emission control transistor, the first initialization transistor is connected to a gate of the driving transistor, and a second pole of the light emitting diode is connected to the second power supply line; the first light emitting control transistor is connected between a first power line and a first pole of the driving transistor, and the second light emitting control transistor is connected between a second pole of the driving transistor and a first pole of the light emitting diode;

13. The display panel of claim 11, further comprising:

in the same first connecting line, the first subsection is positioned on the second conductive layer, and the second subsection is positioned on the third conductive layer or the first conductive layer;

14. The display panel according to claim 11, wherein the pixel circuit further comprises a compensation transistor that is turned on in response to the first gate signal transmitted on the first gate signal line, and compensates for a threshold voltage of the driving transistor;

the display panel further includes:

In the same first connecting line, the first subsection is positioned on the second conductive layer, and the second subsection is positioned on any one layer of the third conductive layer, the first conductive layer or the fourth conductive layer;