CN115356527A - Fault detection method, device and equipment - Google Patents
Fault detection method, device and equipment Download PDFInfo
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- G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
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Abstract
The application discloses a fault detection method, a device and equipment, relates to the technical field of computers, and is used for solving the defects of high cost and low detection efficiency at present, and comprises the following steps: generating a step pulse signal and sending the step pulse signal to a cable to be detected so as to detect the voltage of the cable to be detected; receiving a reflected signal returned by the cable to be detected when the step pulse signal reaches a fault point; and marking a time node when the reflected signal is received, and determining the position information of the fault point based on the time node. According to the method and the device, voltage detection is carried out on the cable by utilizing the step pulse signal, the time node is marked when the reflected signal is received, the position information of the fault point is positioned through the time node, the cost is reduced, and the simplicity and the detection efficiency of operation are improved.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a fault detection method, a fault detection device and fault detection equipment.
Background
With the development of data communication technology, the requirement for the interconnection communication rate between chips is higher and higher, taking an intra-board interconnection PCIE (peripheral component interconnect express, a high-speed serial computer expansion bus standard) bus as an example, new standards are continuously introduced in recent years, the current PCIE 6.0 rate has already reached 64GT/s (Giga Transmission per second), and a high-speed signal has raised a higher requirement for signal integrity. In the past interconnection design, high-speed signals are usually designed in a PCB (Printed Circuit Board), as the signal rate increases, such design encounters a problem of large loss, distortion of long-distance transmission signals is serious, a cable has a significant advantage in loss compared with the PCB in the high-speed interconnection, the loss can be reduced by 20-30% at the same rate and transmission length, as the rate increases continuously in the future, the interconnection design based on high-speed cables becomes an important trend, the cables become important carriers of future high-speed signals, and therefore, the interconnection design is of great importance for detecting defects of the cables.
The common practice in the industry at present is to use a Time-Domain Reflectometry (Time-Domain Reflectometry) Time Domain impedance test system to identify the defect of the impedance of the cable, and the system composition of the TDR is complex and basically includes three major components: a signal generator; an oscilloscope; a probe system. The rationale is the pulse signal that signal generator produced, apply on the cable, impedance discontinuity can appear if the cable defect, there is the reflection signal production this moment, calculate the impedance through measuring time and the amplitude that the reflection signal received, thereby judge whether there is the defect, the problem that exists at present is because equipment cost drops into expensively, the test efficiency is low, must professional can be fine carry out the operation and the use of equipment, system integrator has the detection demand to the high-speed cable quality of purchase, adopt the industry common practice also can only accomplish the selective examination mode in laboratory, not efficient and can not cover whole cable and detect.
Disclosure of Invention
In view of this, the present invention provides a fault detection method, apparatus, and device, which can reduce cost and improve simplicity of operation and detection efficiency. The specific scheme is as follows:
in a first aspect, the present application discloses a fault detection method, including:
generating a step pulse signal and sending the step pulse signal to a cable to be detected so as to detect the voltage of the cable to be detected;
receiving a reflected signal returned by the cable to be detected when the step pulse signal reaches a fault point;
and marking a time node when the reflected signal is received, and determining the position information of the fault point based on the time node.
Optionally, the generating a step pulse signal and sending the step pulse signal to the cable to be detected includes:
after the step signal circuit receives an enabling signal, generating a step pulse signal, and sending the step pulse signal to the cable to be detected;
the rising edge triggers the timing circuit and the voltage sampling circuit to start running.
Optionally, before the rising edge triggers the timing circuit and the voltage sampling circuit to start operating, the method further includes:
setting the signal transmission speed of the step pulse signal;
and determining the timing time of the timing circuit based on the signal transmission speed and the length of the cable to be detected.
Optionally, the receiving a reflected signal returned by the cable to be detected when the step pulse signal reaches the fault point includes:
receiving voltage detection information returned by the cable to be detected through the voltage sampling circuit, and storing the voltage detection information;
when the voltage detection information is received, judging whether the voltage detection information meets a preset voltage value change rule or not;
and if the preset voltage value change rule is not met, receiving the reflection signal corresponding to the voltage detection information and used for representing the return of the step pulse signal when the step pulse signal reaches the fault point.
Optionally, after receiving the reflection signal corresponding to the voltage detection information and used for characterizing that the step pulse signal returns when reaching the fault point, the method further includes:
generating a marking trigger signal through the voltage sampling circuit so that the timing circuit completes marking operation;
correspondingly, the marking the time node when the reflected signal is received comprises:
when the timing circuit receives the mark trigger signal, completing state marking on the time node when the voltage sampling circuit receives the reflection signal;
and storing the time nodes and the corresponding state mark information into a target storage area in the timing circuit.
Optionally, after the voltage detection information returned by the cable to be detected is received by the voltage sampling circuit and stored, the method further includes:
generating a target voltage wave based on the voltage detection information;
and sending the target voltage wave to a preset calculation region so as to judge the fault type corresponding to the target voltage wave in the preset calculation region based on a preset waveform fault judgment rule.
Optionally, the determining the location information of the fault point based on the time node includes:
and sending the time node to the preset calculation area so as to determine the position information of the fault point in the preset calculation area based on the time node and the signal transmission speed.
In a second aspect, the present application discloses a fault detection device, comprising:
the signal transmitting module is used for generating a step pulse signal and transmitting the step pulse signal to a cable to be detected so as to carry out voltage detection on the cable to be detected;
the signal receiving module is used for receiving a reflected signal returned by the cable to be detected when the step pulse signal reaches a fault point;
the time node marking module is used for marking the time node when the reflected signal is received;
and the position information calculation module is used for determining the position information of the fault point based on the time node. In a third aspect, the present application discloses an electronic device, comprising:
a memory for storing a computer program;
a processor for executing said computer program for carrying out the steps of the fault detection method as disclosed in the foregoing.
It can be seen that the present application provides a fault detection method, comprising: generating a step pulse signal and sending the step pulse signal to a cable to be detected so as to detect the voltage of the cable to be detected; receiving a reflected signal returned by the cable to be detected when the step pulse signal reaches a fault point; and marking a time node when the reflected signal is received, and determining the position information of the fault point based on the time node. Therefore, the step pulse signal is sent to the cable to be detected so as to carry out voltage detection, the time node is marked when the reflected signal is received, subsequent voltage detection is continued, and then the position information of the fault point is calculated through the time node, so that the position of the fault cable is quickly positioned, the cost is reduced, and the simplicity and the detection efficiency of operation are improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a flow chart of a fault detection method disclosed herein;
FIG. 2 is a hardware topology of the present disclosure;
FIG. 3 is a flow chart of a particular fault detection method disclosed herein;
FIG. 4 is a schematic diagram of a specific fault detection method disclosed herein;
FIG. 5 is a schematic diagram of a system interconnection disclosed herein;
FIG. 6 is a schematic diagram of a test system interconnect disclosed herein;
FIG. 7 is a schematic structural diagram of a fault detection device provided in the present application;
fig. 8 is a block diagram of an electronic device provided in the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
At present, the common practice in the industry is to use a TDR time domain impedance testing system to identify defects in the impedance of a cable, and the TDR system is complex in composition. The fundamental principle is that the pulse signal that signal generator produced is exerted on the cable, impedance discontinuity point can appear if the cable defect, there is reflection signal production this moment, calculate the impedance through measuring time and the amplitude that the reflection signal received, thereby judge whether defective, the problem that exists at present is because equipment cost drops into expensively, the test efficiency is low, must professional can be fine carry out the operation and the use of equipment, system integrator has the testing requirement to the high-speed cable quality of purchase, adopt industry common practice also can only accomplish the random access mode in laboratory, it is not high and can't cover whole cable and detect to be efficient. Therefore, the fault detection method is provided, the cost can be reduced, and the simplicity and the detection efficiency of operation can be improved.
The embodiment of the invention discloses a fault detection method, which is shown in figure 1 and comprises the following steps:
step S11: and generating a step pulse signal and sending the step pulse signal to a cable to be detected so as to detect the voltage of the cable to be detected.
In this embodiment, a step pulse signal is generated and sent to a cable to be detected, so as to perform voltage detection on the cable to be detected. It can be understood that, as shown in the hardware topology diagram of fig. 2, the main hardware includes a predetermined computing area, a circuit area and a test PCB carrier. The method comprises the steps that a circuit area generates a step pulse signal, the step pulse signal is sent to a cable to be detected as a detection signal, and therefore voltage detection is conducted on the cable to be detected through transmission of the step pulse signal on the cable to be detected.
Specifically, the test PCB carrier is used for carrying a circuit area, a cable connector, and a communication cable connector. And meanwhile, the circuit area and the cable to be detected are directly connected through the cable connector.
Step S12: and receiving a reflected signal returned by the cable to be detected when the step pulse signal reaches a fault point.
In this embodiment, a step pulse signal is generated and sent to a cable to be detected, so that after voltage detection is performed on the cable to be detected, a reflected signal returned by the cable to be detected when the step pulse signal reaches a fault point is received. It can be understood that, if the step pulse signal encounters a fault point during the transmission of the cable to be detected, a reflected signal is returned, and then the transmission of the detection on the remaining cable to be detected is continued.
Step S13: and marking a time node when the reflected signal is received, and determining the position information of the fault point based on the time node.
In this embodiment, after receiving a reflected signal returned by the cable to be detected when the step pulse signal reaches the fault point, a time node when the reflected signal is received is marked, and the position information of the fault point is determined based on the time node. It is understood that the time node when the reflected signal is received is marked and then transmitted to the preset calculation area, so that the position information of the fault point is determined in the preset calculation area based on the time node and the signal transmission speed.
Therefore, the present application provides a fault detection method, including: generating a step pulse signal and sending the step pulse signal to a cable to be detected so as to detect the voltage of the cable to be detected; receiving a reflected signal returned by the cable to be detected when the step pulse signal reaches a fault point; and marking a time node when the reflected signal is received, and determining the position information of the fault point based on the time node. Therefore, the method and the device have the advantages that the step pulse signals are sent to the cable to be detected to carry out voltage detection, the time nodes are marked when the reflected signals are received, subsequent voltage detection is continued, and then the position information of the fault point is calculated through the time nodes, so that the position of the fault cable is quickly positioned, the cost is reduced, and the simplicity and the detection efficiency of operation are improved.
Referring to fig. 3, the embodiment of the present invention discloses a fault detection method, and compared with the previous embodiment, the present embodiment further describes and optimizes the technical solution.
Step S21: after the step signal circuit receives the enabling signal, the step pulse signal is generated and sent to the cable to be detected, so that voltage detection is carried out on the cable to be detected.
In this embodiment, after the step signal circuit receives the enable signal, the step pulse signal is generated, and the step pulse signal is sent to the cable to be detected, so as to perform voltage detection on the cable to be detected. It can be understood that the circuit region mainly includes a step signal generating circuit, a timing circuit, and a voltage sampling circuit, and the preset calculation region is interconnected with the circuit region, so that the calculation region sends a control enable to the step signal circuit in the circuit region, that is, the calculation region controls the step signal circuit to generate a step pulse signal. The step pulse signal is thus generated after the step signal circuit receives the enable signal.
It should be noted that the preset calculation region is interconnected with the circuit region to realize control enabling of the step signal circuit, data acquisition of the timing circuit and the voltage acquisition circuit, and initialization operation of the circuit region; meanwhile, the fault type can be judged through the acquired voltage waveform; and the position information position of the fault point can be accurately calculated by combining the acquired time mark state and the signal transmission speed.
Step S22: the rising edge triggers the timing circuit and the voltage sampling circuit to start running.
In this embodiment, after the step signal circuit receives the enable signal, the step pulse signal is generated, and after the step pulse signal is sent to the cable to be detected, a rising edge triggers the timing circuit and the voltage sampling circuit to start operating. Namely, the rising edge of the step signal circuit is used for triggering the timing circuit to start timing, after the timing circuit is triggered to start timing, the timing circuit simultaneously triggers the voltage sampling circuit to detect the voltage value on the sampling cable, and the timing stopping time of the timing circuit is set according to the length of the cable. Specifically, before the rising edge triggers the timing circuit and the voltage sampling circuit to start operating, the signal transmission speed of the step pulse signal is set, and then the timing time of the timing circuit is determined based on the signal transmission speed and the length of the cable to be detected.
Step S23: and receiving voltage detection information returned by the cable to be detected through the voltage sampling circuit, and storing the voltage detection information.
In this embodiment, after the timing circuit is triggered to start timing, and the timing circuit simultaneously triggers the voltage sampling circuit to detect the voltage value on the sampling cable, the voltage sampling circuit receives voltage detection information returned by the cable to be detected, and stores the voltage detection information. It can be understood that the voltage sampling circuit performs voltage detection on the cable to be detected, and stores and records returned voltage detection information, so as to determine whether a fault exists on the cable to be detected through the voltage detection information.
It should be noted that the voltage detection information returned by the cable to be detected is received through the voltage sampling circuit, and after the voltage detection information is stored, a target voltage wave is generated based on the voltage detection information, and the target voltage wave is sent to a preset calculation region, so that a fault type corresponding to the target voltage wave is judged in the preset calculation region based on a preset waveform fault judgment rule, that is, the judgment of the current fault type is completed through the collected voltage wave.
Step S24: and when the voltage detection information is received, judging whether the voltage detection information meets a preset voltage value change rule or not.
In this embodiment, when the voltage detection information is received, it is determined whether the voltage detection information satisfies a preset voltage value change rule. It can be understood that after the voltage detection information is received, whether the current voltage detection information meets the preset voltage value change rule is determined according to the received historical voltage detection information, for example, when the detected current voltage detection information has an abnormal rising edge or a falling edge, it is determined that the current voltage detection information does not meet the preset voltage value change rule, and the current voltage detection information is an abnormal reflected voltage.
Step S25: and if the preset voltage value change rule is not met, receiving the reflection signal corresponding to the voltage detection information and used for representing the return of the step pulse signal when the step pulse signal reaches the fault point.
In this embodiment, when the voltage detection information is received, after determining whether the voltage detection information satisfies a preset voltage value change rule, if the voltage detection information does not satisfy the preset voltage value change rule, the reflected signal corresponding to the voltage detection information and used for representing that the step pulse signal returns when reaching the fault point is received. And when the step pulse signal reaches the fault point, a reflection signal is generated and returned, so that when the current voltage detection information is judged not to meet the preset voltage value change rule, a reflection signal is received, and a marking trigger signal is generated by the voltage sampling circuit, so that the timing circuit finishes marking operation.
Step S26: and marking a time node when the reflected signal is received, and determining the position information of the fault point based on the time node.
In this embodiment, after the voltage sampling circuit generates the marker trigger signal and sends the marker trigger signal to the timing circuit, the timing circuit marks a time node when the timing circuit receives the reflected signal, and determines the position information of the fault point based on the time node. Specifically, when the timing circuit receives the flag trigger signal, the state flag is completed on the time node when the voltage sampling circuit receives the reflection signal, and the time node and the corresponding state flag information are stored in a target storage area in the timing circuit.
In one specific embodiment, as shown in FIG. 4, single cable testing is performed for high speed cable testing. And connecting the high-speed cable with the test carrier plate through the connector, and performing the detection steps, so as to judge whether a fault point exists on the high-speed cable to be detected currently according to the received voltage value and whether the reflected signal is received.
In another specific embodiment, when the system has interconnection problems, the positioning test is carried out to carry out the troubleshooting of the full link. When 2 system chips as shown in fig. 5 are connected by a high-speed cable, it is often difficult to determine whether a chip fails or a cable or cable connector fails when an interconnection problem occurs between the chips. The detection design of the scheme is respectively subjected to interconnection test with a system through a cable, the specific position of the problem is positioned, for example, the detection design in the scheme is subjected to interconnection test with the system to be detected through the cable, and the position information of the fault point is positioned, for example, the position of the fault point on the cable, the position of a connector, a PCB (printed circuit board) and a chip is detected. Specifically, as shown in fig. 6, the detection design of the present solution is connected to the high-speed cable and the digital chip 2, and the detection step is performed, and when a fault point is detected, the connection is recorded and disconnected, and then the detection step is performed by connecting to the digital chip 1 and uploading, and if a fault point is detected, the recording is performed, and if a fault point is not detected, it is indicated that the fault point in the system to be detected is not in the digital chip 1. When the high-speed cable and the digital chip 2 are connected and the uploading detection step is carried out, when the fault point is not detected, the fact that the fault point does not exist on the high-speed cable and the digital chip 2 is indicated, then the high-speed cable and the digital chip 1 are connected and the uploading detection step is carried out, the obtained fault point information is recorded, the fault location of the whole link can be completed through 2 times of measurement at most, and the quick location of the fault is achieved.
The scheme reduces the cost, simplifies the operation steps, and is concise to deploy the method for diagnosing the fault of the high-speed cable, thereby solving the problem of detecting the rapid quality defect of the high-speed cable, realizing the rapid diagnosis of the interconnection fault of the system and achieving the effect of rapidly positioning the fault module.
Therefore, in the embodiment of the application, after the step signal circuit receives the enable signal, the step pulse signal is generated and sent to the cable to be detected, so that the voltage of the cable to be detected can be detected conveniently; the rising edge triggers the timing circuit and the voltage sampling circuit to start running; receiving voltage detection information returned by the cable to be detected through the voltage sampling circuit, and storing the voltage detection information; when the voltage detection information is received, judging whether the voltage detection information meets a preset voltage value change rule or not; if the preset voltage value change rule is not met, receiving a reflection signal corresponding to the voltage detection information and used for representing the return of the step pulse signal when the step pulse signal reaches the fault point; and marking the time node when the reflected signal is received, and determining the position information of the fault point based on the time node, so that the cost is reduced, and the simplicity of operation and the detection efficiency are improved.
Referring to fig. 7, the embodiment of the present application further discloses a fault detection apparatus, which includes:
the signal sending module 11 is configured to generate a step pulse signal and send the step pulse signal to a cable to be detected, so as to perform voltage detection on the cable to be detected;
the signal receiving module 12 is configured to receive a reflected signal returned by the cable to be detected when the step pulse signal reaches a fault point;
a time node marking module 13, configured to mark a time node when the reflection signal is received;
and a position information calculation module 14, configured to determine position information of the fault point based on the time node.
As can be seen, the present application includes: generating a step pulse signal and sending the step pulse signal to a cable to be detected so as to detect the voltage of the cable to be detected; receiving a reflected signal returned by the cable to be detected when the step pulse signal reaches a fault point; and marking a time node when the reflected signal is received, and determining the position information of the fault point based on the time node. Therefore, the step pulse signal is sent to the cable to be detected so as to carry out voltage detection, the time node is marked when the reflected signal is received, subsequent voltage detection is continued, and then the position information of the fault point is calculated through the time node, so that the position of the fault cable is quickly positioned, the cost is reduced, and the simplicity and the detection efficiency of operation are improved.
In some specific embodiments, the signal sending module 11 specifically includes:
the step pulse signal sending unit is used for generating a step pulse signal after the step signal circuit receives an enabling signal and sending the step pulse signal to the cable to be detected so as to detect the voltage of the cable to be detected;
a signal transmission speed setting unit for setting a signal transmission speed of the step pulse signal;
the timing time determining unit is used for determining the timing time of the timing circuit based on the signal transmission speed and the length of the cable to be detected;
and the circuit operation triggering unit is used for triggering the timing circuit and the voltage sampling circuit to start operation by a rising edge.
In some embodiments, the signal receiving module 12 specifically includes:
the voltage detection information returning unit is used for receiving the voltage detection information returned by the cable to be detected through the voltage sampling circuit;
a voltage detection information storage unit for storing the voltage detection information;
a voltage wave generating unit for generating a target voltage wave based on the voltage detection information;
and the fault type judging unit is used for sending the target voltage wave to a preset calculating area so that the preset calculating area can judge the fault type corresponding to the target voltage wave based on a preset waveform fault judging rule.
The voltage value change judging unit is used for judging whether the voltage detection information meets a preset voltage value change rule or not when the voltage detection information is received;
the reflected signal determining unit is used for receiving the reflected signal which corresponds to the voltage detection information and is used for representing the return of the step pulse signal when the step pulse signal reaches the fault point if the preset voltage value change rule is not met;
and the marking trigger signal generating unit is used for generating a marking trigger signal through the voltage sampling circuit so that the timing circuit finishes marking operation.
In some specific embodiments, the time node marking module 13 specifically includes:
a state marking unit, configured to complete state marking on the time node when the voltage sampling circuit receives the reflected signal when the timing circuit receives the mark trigger signal;
and the information storage unit is used for storing the time nodes and the corresponding state mark information into a target storage area in the timing circuit.
In some specific embodiments, the preset calculation area 14 for the position information specifically includes:
a location information calculation unit configured to send the time node to the preset calculation area so as to determine location information of the fault point in the preset calculation area based on the time node and the signal transmission speed.
Further, the embodiment of the application also provides electronic equipment. FIG. 8 is a block diagram illustrating an electronic device 20 according to an exemplary embodiment, and nothing in the figure should be taken as a limitation on the scope of use of the present application.
Fig. 8 is a schematic structural diagram of an electronic device 20 according to an embodiment of the present disclosure. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input output interface 25, and a communication bus 26. Wherein the memory 22 is used for storing a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the fault detection method disclosed in any of the foregoing embodiments. In addition, the electronic device 20 in the present embodiment may be specifically an electronic computer.
In this embodiment, the power supply 23 is configured to provide an operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and an external device, and a communication protocol followed by the communication interface is any communication protocol applicable to the technical solution of the present application, and is not specifically limited herein; the input/output interface 25 is configured to obtain external input data or output data to the outside, and a specific interface type thereof may be selected according to specific application requirements, which is not specifically limited herein.
In addition, the storage 22 is used as a carrier for storing resources, and may be a read-only memory, a random access memory, a magnetic disk or an optical disk, etc., and the resources stored thereon may include an operating system 221, a computer program 222, etc., and the storage manner may be a transient storage manner or a permanent storage manner.
The operating system 221 is used for managing and controlling each hardware device on the electronic device 20 and the computer program 222, and may be Windows Server, netware, unix, linux, or the like. The computer program 222 may further include a computer program that can be used to perform other specific tasks in addition to the computer program that can be used to perform the failure detection method disclosed in any of the foregoing embodiments and executed by the electronic device 20.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
The method, the device and the equipment for fault detection provided by the invention are described in detail, a specific example is applied in the text to explain the principle and the implementation mode of the invention, and the description of the embodiment is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (9)
1. A method of fault detection, comprising:
generating a step pulse signal and sending the step pulse signal to a cable to be detected so as to detect the voltage of the cable to be detected;
receiving a reflected signal returned by the cable to be detected when the step pulse signal reaches a fault point;
and marking a time node when the reflected signal is received, and determining the position information of the fault point based on the time node.
2. The fault detection method according to claim 1, wherein the generating and sending the step pulse signal to the cable to be detected comprises:
after the step signal circuit receives an enabling signal, generating a step pulse signal and sending the step pulse signal to the cable to be detected;
the rising edge triggers the timing circuit and the voltage sampling circuit to start running.
3. The method of claim 2, wherein before the rising edge triggers the timing circuit and the voltage sampling circuit to start operating, the method further comprises:
setting the signal transmission speed of the step pulse signal;
and determining the timing time of the timing circuit based on the signal transmission speed and the length of the cable to be detected.
4. The method according to claim 3, wherein the receiving the reflected signal returned by the cable to be detected when the step pulse signal reaches the fault point comprises:
receiving voltage detection information returned by the cable to be detected through the voltage sampling circuit, and storing the voltage detection information;
when the voltage detection information is received, judging whether the voltage detection information meets a preset voltage value change rule or not;
and if the preset voltage value change rule is not met, receiving the reflection signal corresponding to the voltage detection information and used for representing the return of the step pulse signal when the step pulse signal reaches the fault point.
5. The method according to any one of claims 2 to 4, wherein, after receiving the reflection signal corresponding to the voltage detection information and used for characterizing the return of the step pulse signal when reaching the fault point, the method further comprises:
generating a marking trigger signal through the voltage sampling circuit so that the timing circuit completes marking operation;
correspondingly, the marking the time node when the reflected signal is received comprises:
when the timing circuit receives the mark trigger signal, completing state marking on the time node when the voltage sampling circuit receives the reflection signal;
and storing the time nodes and the corresponding state mark information into a target storage area in the timing circuit.
6. The method according to claim 4, wherein after receiving, by the voltage sampling circuit, the voltage detection information returned by the cable to be detected and storing the voltage detection information, the method further comprises:
generating a target voltage wave based on the voltage detection information;
and sending the target voltage wave to a preset calculation region so as to judge the fault type corresponding to the target voltage wave in the preset calculation region based on a preset waveform fault judgment rule.
7. The method of claim 6, wherein the determining the location information of the fault point based on the time node comprises:
and sending the time node to the preset calculation area so as to determine the position information of the fault point in the preset calculation area based on the time node and the signal transmission speed.
8. A fault detection device, comprising:
the signal transmitting module is used for generating a step pulse signal and transmitting the step pulse signal to a cable to be detected so as to detect the voltage of the cable to be detected;
the signal receiving module is used for receiving a reflected signal returned by the cable to be detected when the step pulse signal reaches a fault point;
the time node marking module is used for marking the time node when the reflected signal is received;
and the position information calculation module is used for determining the position information of the fault point based on the time node.
9. An electronic device, comprising:
a memory for storing a computer program;
a processor for executing the computer program to carry out the steps of the fault detection method according to any one of claims 1 to 7.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116626445A (en) * | 2023-07-04 | 2023-08-22 | 四川天中星航空科技有限公司 | Cable fault detection system and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116626445A (en) * | 2023-07-04 | 2023-08-22 | 四川天中星航空科技有限公司 | Cable fault detection system and method |
| CN116626445B (en) * | 2023-07-04 | 2024-02-27 | 四川天中星航空科技有限公司 | Cable fault detection system and method |
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