CN213750205U - Transmission rate testing device - Google Patents
Transmission rate testing device Download PDFInfo
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- CN213750205U CN213750205U CN202022900604.5U CN202022900604U CN213750205U CN 213750205 U CN213750205 U CN 213750205U CN 202022900604 U CN202022900604 U CN 202022900604U CN 213750205 U CN213750205 U CN 213750205U
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Abstract
The utility model provides a transmission rate testing arrangement, including a plurality of sub transmission rate testers, every sub transmission rate tester includes dual transmission mode configurator and operation function tester, wherein: the dual transmission mode configurator is provided with a configuration signal output port electrically connected with the chip to be tested and used for configuring the transmission frequency of the chip to be tested and the sub transmission rate tester into a dual transmission rate mode; the operation function tester is connected with the chip electricity that awaits measuring, including data calibrator and high-low level while data sample thief, and the data calibrator has test result output port, and high-low level while data sample thief is connected with chip and data calibrator electricity that awaits measuring respectively, and this operation function tester is used for testing the operation function of chip under the dual transmission rate mode that awaits measuring to read out the test result of operation function, the utility model provides a transmission rate testing arrangement can detect whether the function of chip under the dual transmission rate mode operation that awaits measuring is correct.
Description
Technical Field
The application relates to the technical field of communication, in particular to a transmission rate testing device.
Background
DTR (Dual Transfer Rate) is a basic function of Nor Flash with high speed, large capacity and high speed in recent years.
However, in the testing method in the prior art, because of the limitation of the physical structure and the hardware and software of the testing device, it is impossible to detect whether the function of the chip to be tested under the DTR operation is correct.
SUMMERY OF THE UTILITY MODEL
The application provides a dual transmission rate testing arrangement has solved current test equipment effectively and can't detect whether function under the DTR operation of chip that awaits measuring is correct problem.
In order to solve the above problem, the utility model provides a transmission rate testing arrangement, transmission rate testing arrangement includes a plurality of sub transmission rate testers, and every the sub transmission rate tester includes dual transmission mode configurator and operation function tester, wherein:
the dual transmission mode configurator is provided with a configuration signal output port which is used for being electrically connected with a chip to be tested;
the operation function tester is electrically connected with the chip to be tested and comprises a data checker and a high-low level simultaneous data sampler, the data checker is provided with a test result output port, and the high-low level simultaneous data sampler is electrically connected with the chip to be tested and the data checker respectively.
Further preferably, each of the sub-transmission rate testers further comprises a signal access port, and the signal access port is a start and stop command access port.
Further preferably, the transmission rate testing device further comprises an automatic testing device, the automatic testing device comprises a uART access port, the uART access port is a control port of the sub-transmission rate tester, and the uART access port is electrically connected with the signal access port of each sub-transmission rate tester.
Further preferably, the operation function tester further comprises a uART connection/exit port, the uART connection/exit port is a test result sending port, and the uART connection/exit port is electrically connected to the test result output port and the automation test device.
Further preferably, the chip to be tested comprises Nor Flash.
Further preferably, the number of chips to be tested is not less than 8.
Further preferably, the plurality of sub-transmission rate testers are connected with the plurality of chips to be tested in a one-to-one manner.
Further preferably, the dual transmission mode configurator has a configuration completion notification port, and the operation function tester has a configuration completion receiving port, and the configuration completion notification port is electrically connected to the configuration completion receiving port.
Further preferably, the dual transmission mode configurator is a setter.
The utility model has the advantages that: the utility model provides a transmission rate testing arrangement, including a plurality of sub transmission rate testers, and every sub transmission rate tester includes dual transmission mode configurator and operation function tester, wherein: the dual transmission mode configurator is provided with a configuration signal output port which is electrically connected with the chip to be tested and is used for configuring the transmission frequency of the chip to be tested and the sub transmission rate tester into a dual transmission rate mode; the operation function tester is connected with the chip electricity that awaits measuring, including data calibrator and high-low level while data sample thief, and the data calibrator has test result output port, and high-low level while data sample thief is connected with chip and data calibrator electricity that awaits measuring respectively, and this operation function tester is used for testing the operation function of chip under the dual transmission rate mode that awaits measuring to read out the test result of operation function, the utility model provides a transmission rate testing arrangement can detect whether the function of chip under the dual transmission rate mode operation that awaits measuring is correct.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the description of the embodiments according to the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a transmission rate testing apparatus according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a further structure of a transmission rate testing apparatus according to an embodiment of the present invention.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings, which are included to illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], refer to the directions of the attached drawings only. Accordingly, the directional terms used are used for describing and understanding the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals.
It should be noted that the thickness and the shape in the drawings of the present invention do not reflect the true proportion, and the purpose is only to schematically illustrate each implementation content of the present invention.
The embodiment of the utility model provides a whether correct problem of function of chip under dual transmission rate operation that can't detect to await measuring for the testing arrangement under solving prior art.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a transmission rate testing apparatus 100 according to an embodiment of the present invention, the transmission rate testing apparatus 100 is used for testing the functionality of a plurality of chips 200 under test in a dual transmission rate mode, and it can be seen from fig. 1 that the components according to the embodiment of the present invention and the relative position relationship of the components are shown.
As shown in fig. 1, the transmission rate testing apparatus 100 includes a plurality of sub-transmission rate testers 110, and each sub-transmission rate tester 110 includes a dual transmission mode configurator 111 and an operation function tester 112, wherein:
the dual transmission mode configurator 111 has a configuration signal output port 1, the configuration signal output port 1 is electrically connected to the chip 200 to be tested, and the dual transmission mode configurator 111 is used for configuring the transmission frequencies of the chip 200 to be tested and the sub transmission rate tester 110 into a dual transmission rate mode; the dual transmission mode configurator 111 may be a setting device, and is respectively connected to the dual transmission rate mode setting input terminals of the test chip 200 and the high-low level simultaneous data sampler 1122, so as to implement the dual transmission mode configuration of the test chip 200 and the high-low level simultaneous data sampler 1122.
The operation function tester 112 is electrically connected to the chip 200 to be tested, and includes a data checker 1121 and a high-low level simultaneous data sampler 1122, where the data checker 1121 has a test result output port 2, the high-low level simultaneous data sampler 1122 is electrically connected to the chip 200 to be tested and the data checker 1121, respectively, and the operation function tester 112 is configured to test an operation function of the chip 200 to be tested in the dual transmission rate mode and read a test result of the operation function.
Specifically, the data checker 1121 is configured to check the correctness of the function of the chip 200 under test operating in the dual transmission rate mode, and generate a test result, where the test result is output through the test result output port 2; the high-low level simultaneous data sampler 1122 is used to implement a high-low level simultaneous data sampling function for the operation function tester 112 before checking the correctness of the operation function.
Further, the sampling frequency of the high-low level simultaneous data sampler 1122 is determined according to the setting parameters of the sub-transmission rate tester 110 and the chip 200 under test.
Further, please refer to fig. 2, fig. 2 is a schematic diagram illustrating a further structure of the transmission rate testing apparatus 100 according to an embodiment of the present invention.
As shown in fig. 2, the transmission rate testing apparatus 100 further includes an automatic testing device 120, and the operation function tester 112 further includes a uART access port 4(uART, Universal Asynchronous Receiver/Transmitter).
Specifically, the uART access port 4 is a test result sending port, and the uART access port 4 is electrically connected to the test result output port 2 and the automated testing equipment 120, so that the test result generated by the data verifier 1121 is output through the test result output port 2, and then the test result is sent to the automated testing equipment 120 through the uART access port 4.
Further, the sub-transmission rate tester 110 further includes a signal access port 3, and the signal access port 3 is a start and stop command access port for accessing commands of the automatic testing equipment 120 to control the start and stop of the test.
Further, the automatic test equipment 120 further includes a uART access port 5, the uART access port 5 is a sub transfer rate tester control port, and the uART access port 5 is electrically connected to the signal access port 3 of each sub transfer rate tester 110 for controlling the start and stop of the sub transfer rate tester 110.
It is easy to understand that the dual transmission mode configurator 111 has a configuration completion notification port 6, the operation function tester 112 has a configuration completion receiving port 7, the configuration completion notification port 6 is electrically connected to the configuration completion receiving port 7, when the dual transmission mode configurator 111 configures the transmission frequencies of the chip 200 to be tested and the sub transmission rate tester 110 into the dual transmission rate mode, the configuration completion notification port 6 notifies the operation function tester 112, and the operation function tester 112 receives the notification through the configuration completion receiving port 7 and then tests the chip 200 to be tested.
Further, the chip 200 to be tested includes Nor Flash, which is a non-volatile Flash technology, and has high transmission efficiency and high cost efficiency at a small capacity of 1-4 MB.
Specifically, the operation function tester 112 of each sub-transmission rate tester 110 is connected to a plurality of chips 200 to be tested one-to-one, and the dual transmission mode configurator 111 of each sub-transmission rate tester 110 configures the chips 200 to be tested and the operation function tester 112, for example, in one transmission rate testing apparatus 100, 8 sub-transmission rate testers 110 can be configured, so that the number of simultaneous tests of the chips 200 to be tested can reach 8, thereby effectively improving the testing efficiency.
In this embodiment, when performing a transmission rate Test of the chip 200 to be tested, first, the transmission frequencies of the sub-transmission rate tester 110 (which may be an MCU) and the chip 200 to be tested (which may be a Nor Flash) are determined to be configured into a DTR mode (i.e., a dual transmission rate mode), then, the sampling frequency of the MCU 1122 is determined according to the setting parameters of the MCU and the Nor Flash to implement a high-low level simultaneous data sampling function, then, the correctness of the Nor Flash in the dual transmission rate mode is checked by the data checker 1121 of the MCU to obtain a Test result, and finally, the MCU returns the Test result of the Nor Flash to the Automatic Test Equipment 120 (i.e., Automatic Test Equipment, ATE) through the uART access port 4 to implement bidirectional communication.
Different from the prior art, the utility model discloses an use can realize detecting MCU (promptly the utility model provides a sub transmission rate tester 110) of operating function exactness under the DTR mode as the communication bridge between ATE and Nor Flash, will detect that the test of operating function exactness goes on between Nor Flash and MCU under the DTR mode, makes MCU and ATE can carry out the order interaction, so that ATE can open and shut MCU, MCU can report transmission test data for ATE, thereby make the utility model provides a transmission rate testing arrangement 100 can realize detecting the exactness of operating function under the DTR mode, and because MCU (being the procedure of sub transmission rate tester 110) has fine portability and commonality, this test can be used in most model Nor Flash; meanwhile, a communication connection is also established between the Nor Flash and the ATE so as to perform other existing functional tests.
Different from the prior art, the utility model provides a transmission rate testing arrangement 100, including a plurality of sub transmission rate testers 110, and every sub transmission rate tester 110 includes dual transmission mode configurator 111 and operation function tester 112, wherein: the dual transmission mode configurator 111 has a configuration signal output port 1, the configuration signal output port 1 is electrically connected with the chip 200 to be tested, the dual transmission mode configurator 111 is used for configuring the transmission frequencies of the chip 200 to be tested and the sub transmission rate tester 110 into a dual transmission rate mode; the operation function tester 112 is electrically connected to the chip 200 to be tested, including the data checker 1121 and the high-low level simultaneous data sampler 1122, and the data checker 1121 has the test result output port 2, and the high-low level simultaneous data sampler 1122 is electrically connected to the chip 200 to be tested and the data checker 1121 respectively, and this operation function tester 112 is used for testing the operation function of the chip 200 to be tested under the dual transmission rate mode, and reads out the test result of the operation function, the utility model provides a transmission rate testing arrangement 100 can detect whether the function of the chip 200 to be tested under the dual transmission rate mode operation is correct.
In addition to the above embodiments, the present invention may have other embodiments. All the technical solutions formed by adopting equivalent substitutions or equivalent substitutions fall within the protection scope of the present invention.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the scope of the appended claims.
Claims (9)
1. A transmission rate testing apparatus, comprising a plurality of sub-transmission rate testers, each of the sub-transmission rate testers comprising a dual transmission mode configurator and an operational function tester, wherein:
the dual transmission mode configurator is provided with a configuration signal output port which is used for being electrically connected with a chip to be tested;
the operation function tester is electrically connected with the chip to be tested and comprises a data checker and a high-low level simultaneous data sampler, the data checker is provided with a test result output port, and the high-low level simultaneous data sampler is electrically connected with the chip to be tested and the data checker respectively.
2. The transmission rate test apparatus according to claim 1, wherein each of the sub transmission rate testers further comprises a signal access port, the signal access port being a start and stop command access port.
3. The transfer rate testing apparatus of claim 2, further comprising an automated testing device comprising a uART access port, the uART access port being a sub-transfer rate tester control port, and the uART access port being electrically connected to the signal access port of each of the sub-transfer rate testers.
4. The transmission rate testing device according to claim 3, wherein the operation function tester further includes a uART connection port, and the uART connection port is a test result transmission port, and the uART connection port is electrically connected to the test result output port and the automated test equipment.
5. The transmission rate testing device according to claim 1, wherein the chip under test comprises Nor Flash.
6. The transmission rate testing device of claim 1, wherein the number of chips to be tested is not less than 8.
7. The transmission rate testing apparatus according to claim 1, wherein the plurality of sub-transmission rate testers are connected to the plurality of chips under test one-to-one.
8. The transmission rate testing apparatus according to claim 1, wherein the dual transfer mode configurator has a configuration completion notifying port, and the operation function tester has a configuration completion receiving port, the configuration completion notifying port being electrically connected to the configuration completion receiving port.
9. The transmission rate testing apparatus of claim 1, wherein the dual transmission mode configurator is a setter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022900604.5U CN213750205U (en) | 2020-12-03 | 2020-12-03 | Transmission rate testing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022900604.5U CN213750205U (en) | 2020-12-03 | 2020-12-03 | Transmission rate testing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN213750205U true CN213750205U (en) | 2021-07-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202022900604.5U Active CN213750205U (en) | 2020-12-03 | 2020-12-03 | Transmission rate testing device |
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| Country | Link |
|---|---|
| CN (1) | CN213750205U (en) |
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2020
- 2020-12-03 CN CN202022900604.5U patent/CN213750205U/en active Active
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Address after: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee after: Wuhan Xinxin Integrated Circuit Co.,Ltd. Country or region after: China Address before: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd. Country or region before: China |