CN115268987A

CN115268987A - Heterogeneous platform FPGA multi-version configuration file loading management method

Info

Publication number: CN115268987A
Application number: CN202210888216.0A
Authority: CN
Inventors: 洪畅; 杨阳; 翟栋梁; 丁志辉
Original assignee: 724th Research Institute of CSIC
Current assignee: 724th Research Institute of CSIC
Priority date: 2022-07-27
Filing date: 2022-07-27
Publication date: 2022-11-01

Abstract

The invention provides a heterogeneous platform FPGA multi-version configuration file loading management method. The FPGA multi-version loading mainly relates to a loading Controller (CPU), an FPGA to be loaded, a nonvolatile memory and a PC upper computer. And the upper computer issues all the configuration files of the FPGA to be loaded in the platform to each functional module through the gigabit Ethernet and stores the configuration files into the NAND FLASH on board of the functional module. And running loading control software on the CPU, and when the CPU judges that reconfiguration is needed, selecting a correct configuration file to be loaded and transmitting the configuration file to the FPGA through the PCIE bus. And running a loading configuration logic on the FPGA, receiving configuration data to start a loading transaction, and writing the data into the NOR FLASH through the SPI bus. After the writing is finished, the CPU controls the FPGA to be electrified again, and the CPU executes restarting; after restarting, the FPGA will execute the loaded functional logic. The method can realize loading of the FPGA multi-version configuration file, and improves convenience and flexibility.

Description

Heterogeneous platform FPGA multi-version configuration file loading management method

Technical Field

The present invention relates to the field of data communications.

Background

In the fields such as radar, communication, artificial intelligence and the like, the data communication and processing requirements have the characteristics of high performance, large bandwidth, strong real-time performance and the like, which brings great challenges to the computing capacity of a processor, and the performance of the processor is limited by the process, power consumption and the like by simply improving the performance of the processor, so that the processing capacity is improved by adopting the heterogeneous form of a processor CPU + a coprocessor (GPU, FPGA and the like), and the processing method is widely researched and applied.

The FPGA is used as a programmable logic device with high performance and high energy efficiency ratio, and the heterogeneous processing scheme generally shows that a CPU transmits data to the FPGA for processing, and the FPGA returns a result to the CPU after processing is finished. The characteristics of heterogeneous acceleration determine that the data communication between the CPU and the FPGA needs to have the characteristics of high speed, large bandwidth and strong robustness. The PCIE bus is used as a third-generation high-performance bus, the characteristics of high transmission rate and strong anti-interference capability completely conform to the requirements of CPU + FPGA heterogeneous processing, the PCIE Gen3 single lane transmission rate reaches 8GT/s, and the PCIE Gen4 single lane transmission rate reaches 16GT/s.

In the application field of radar and the like, a data processing module is generally implemented based on a processing blade of a VPX architecture. Usually, a plurality of processing boards with the same hardware form and different functions exist in the VPX chassis, and the same board has interchangeability, that is, when the same board is located in different slot positions, the board automatically executes the function corresponding to the slot position. The traditional mode for loading the FPGA is active loading, a downloading cable needs to be connected manually to confirm correct FPGA configuration data, the operation is complex, the loading speed is low, and the functions of the loaded modules are completely solidified without interchangeability. And another FPGA multi-version loading mode is to store a plurality of FPGA configuration data into an onboard FLASH and realize the switching and downloading of different configuration data through an internal ICAP of the FPGA. The method can meet the requirement of multiple configuration of the FPGA when the types of configuration data needing to be switched and downloaded are less and the FLASH capacity is large enough, but in practical application, the number of FPGA functional modules in a system is large, different functions are completed, particularly in a system with a localization requirement, the capacity of the domestic FLASH is small, and the FLASH capacity cannot meet the application requirement. Another drawback is that after the multi-version FPGA configuration data is solidified into FLASH, it is inconvenient to upgrade and maintain the FPGA program at a later stage.

Disclosure of Invention

In order to solve the technical problems and achieve the purpose of function reconstruction, the invention provides a loading management method of an FPGA multi-version configuration file aiming at a CPU + FPGA heterogeneous module under a VPX platform.

The invention provides a heterogeneous platform FPGA multi-version configuration file loading management method, which adopts the following technical scheme:

the device comprises four functional modules, namely an FPGA loading configuration logic module, a loading judgment software module, a loading configuration data software module and a PCIE driving module; the FPGA executes loading configuration logic, and the CPU executes loading judgment software, loading configuration data software and PCIE drive; the loading configuration logic mainly comprises PCIE BAR, clock, FIFO, FLASH read-write and other functional logics; loading judgment software acquires slot position information and judges whether a loading process needs to be started or not according to a mapping table; the configuration data loading software is responsible for sending configuration data to the FPGA through the PCIE interface; the PCIE driver realizes the functions of PCIE driver registration, equipment detection, character equipment node creation, file operation interface and the like.

Furthermore, the method is applied to the heterogeneous platform, the platform comprises a plurality of functional modules, an exchange board and a power supply, and the functional modules, the exchange board and the power supply are interconnected through a back board; the functional module is in a CPU + FPGA heterogeneous processing form; the device related to the method in the functional module comprises a CPU, an FPGA, a QSPI NOR FLASH and a NAND FLASH, wherein the CPU is a loading controller, the FPGA is a device to be loaded, the QSPI NOR FLASH is used for storing FPGA on-line configuration data, and the NAND FLASH is used for storing FPGA configuration data of all functional modules in a platform.

Further, the process of loading and configuring the logic state machine is as follows: a first state: reading a FLASH erasing register in the BAR space, entering a state II when the FLASH erasing register is 1, and otherwise, repeating the state; and a second state: according to the FLASH erasing time sequence, carrying out integral erasing on the FLASH through an SPI bus, if the erasing is successful, setting an erasing completion register to be 1, and entering a state III, otherwise, repeating the state; and a third state: reading a FLASH erasing register of a BAR space, entering a state IV after waiting for zero clearing, and otherwise, repeating the state; and a fourth state: configuring data register data to buffer in FIFO, and setting FIFO full identification register as 1 when FIFO is full; when the FIFO is not empty, the state is repeated, and data is continuously written into the FLASH through the SPI bus; when the FIFO is empty, if the sending completion register is 0, the state is repeated to wait for new data, if the sending completion register is 1, the configuration data is completely written, and the state enters a fifth state; and a fifth state: load done register set 1 enters state one.

Further, the loading decision software processing flow is as follows: the method comprises the following steps: reading a PCIE BAR slot register to obtain the information of the slot; step two: reading the slot position information file to obtain the last slot position information; step three: searching a mapping table to respectively obtain FPGA configuration data identification numbers corresponding to the mapping table and the FPGA configuration data identification numbers; step four: comparing the identification numbers, if the identification numbers are consistent, not starting the loading process, otherwise, calling the software for loading and configuring data to start the loading process; step five: and updating the slot position information file and storing the slot position information into the file.

Further, the processing flow of the software for loading configuration data is as follows: the method comprises the following steps: starting, checking the authority to ensure that the executing user has the authority; step two: opening a PCIE equipment node; step three: acquiring the total byte number of the configuration file to be loaded; step four: opening a configuration file; step five: sending a completion register set 0 and a FLASH erasing register set 1, namely sending a FLASH erasing command; step six: reading the erasure completion register, and setting the erasure register to be 0 after the erasure is completed; step seven: acquiring data blocks with the size of 1024 bytes from the configuration data file, and filling 0xff for completion when the residual data is less than 1024 bytes; step eight: reading the FIFO status register, sequentially writing the configuration data into the configuration data register when the FIFO is not full, if the FIFO is full, delaying a short time and repeatedly executing the step until all data in the data block are written; step nine, repeating the step seven and the step eight until the configuration file data is completely written; step ten: a data transmission completion register 1; step eleven: reading a loading completion register and confirming the successful loading; step twelve: the device is shut down.

The invention completes the loading of the FPGA multi-version configuration data based on the PCIE bus, realizes the function of intelligent loading of the function module FPGA when the slot position is replaced, and is beneficial to the maintenance and on-line upgrading of the logic function of the FPGA.

Drawings

FIG. 1 is a functional schematic diagram of FPGA loading;

FIG. 2 is a flow chart of a software process for loading configuration data.

Detailed Description

The present invention provides a heterogeneous platform FPGA multi-version configuration file loading management method, and for making the technical solution and the effective benefit of the present invention clearer, the following further description is made with reference to specific embodiments and drawings, and the following specific embodiments are not intended to limit the present invention.

A functional block diagram of a preferred embodiment of the present invention is shown with reference to fig. 1. The CPU and the FPGA in the functional module are directly communicated with high-speed data through PCIE X8 Gen 3; in order to not occupy the bandwidth of a data channel, the CPU loads FPGA configuration data and is realized based on accessing a PCIE BAR register; the SPI NOR FLASH is used for storing the current online configuration data of the function module FPGA; all the configuration data of the function module FPGA in an onboard SSD (NAND FLASH) storage platform, configuration files and a slot mapping table; according to the invention, an SPI configuration interface is adopted for FPGA loading, a PCIE bus is used for transmission, after the loading is finished, a CPU controls the FPGA to be electrified again for automatic configuration, and the CPU needs to be restarted to finish building a chain for the PCIE. In this embodiment, the heterogeneous platform is a chassis designed based on the VPX specification, and the platform includes a plurality of functional modules, a switch board, and a power supply inside, which are interconnected through a backplane. The external interface of the functional module comprises a gigabit network interface, so that a user can conveniently update and manage the stored FPGA configuration data and the mapping table, and the upgrading of the logic function of the FPGA in the heterogeneous platform is facilitated.

The FPGA functional logic consists of loading configuration logic and specific service logic, and each heterogeneous processing module in the case is embedded with a loading logic functional block. The loading configuration logic relates to PCIE BAR, clock, FIFO, FLASH read-write and the like; the specific business logic realizes different data processing algorithms according to different tasks. The slot address information of the heterogeneous processing module is defined according to the VPX standard, and each slot XP0 connector of the backplane includes 6 address signals, GA [4 ] + and GAP ″, wherein GAP is a parity of GA [4 ]. The GA [4 ]. And the FPGA obtains the slot position information by reading the slot position address IO port and stores the slot position information into the BAR space slot position information register.

The PCIE driver is developed based on a character device driver framework, and functions related to the invention comprise PCIE driver registration, device detection, character device node creation, a file operation interface and the like. The BAR register access mode is realized based on a file operation memory mapping interface: and the drive acquires the BAR space physical address, and maps the BAR space address to the user space by a kernel mode and user mode memory mapping method. The BAR space register used by the present invention is as follows:

referring to fig. 2, the processing flow of the software for loading configuration data in the embodiment is specifically as follows:

the method comprises the following steps: starting, checking the authority to ensure that the user executing the loading has the authority; step two: opening a device node; step three: acquiring the total byte number of the configuration file to be loaded; step four: opening a configuration file; step five: sending a finishing register set 0 and a FLASH erasing register set 1, namely sending a Flash erasing command; step six: reading an erasure completion identification register, and clearing an erasure command after the erasure is completed; step seven: acquiring data blocks with the size of 1024 bytes from the configuration data file, and filling 0xff for completion when the residual data is less than 1024 bytes; step eight: reading the FIFO status register, sequentially writing the configuration data into the configuration data register when the FIFO is not full, if the FIFO is full, delaying a short time and repeatedly executing the step until all data in the data block are written; step nine: repeating the sixth step and the seventh step until the configuration data file is completely written; step ten: the data transmission completion register 1 informs the FPGA; step eleven: reading a loading completion register and confirming the successful loading; step twelve: the device is shut down.

Claims

1. A heterogeneous platform FPGA multi-version configuration file loading management method is characterized by comprising the following steps: the system comprises four functional modules, namely an FPGA loading configuration logic module, a loading judgment software module, a loading configuration data software module and a PCIE driving module; the FPGA loading configuration logic executes loading configuration logic, and the CPU executes loading judgment software, loading configuration data software and PCIE drive; the FPGA loading configuration logic comprises PCIE BAR, a clock, FIFO and FLASH read-write function logic; loading judgment software acquires slot position information and judges whether a loading process needs to be started or not according to a mapping table; the configuration data loading software is responsible for sending configuration data to the FPGA through the PCIE interface; the PCIE driver realizes the functions of PCIE driver registration, equipment detection, character equipment node creation and file operation interface.

2. The heterogeneous platform FPGA multi-version configuration file loading management method according to claim 1, characterized in that: the functional module is in a CPU + FPGA heterogeneous processing form and comprises a CPU, an FPGA, a QSPI NOR FLASH and a NAND FLASH, wherein the CPU is a loading controller, the FPGA is a device to be loaded, the QSPI NOR FLASH is used for storing FPGA on-line configuration data, and the NAND FLASH is used for storing FPGA configuration data of all functional modules in a platform.

3. The heterogeneous platform FPGA multi-version configuration file loading management method according to claim 1, characterized in that: the state machine flow of the loading configuration logic is as follows: a first state: reading a FLASH erasing register in the BAR space, entering a state II when the FLASH erasing register is 1, and otherwise, repeating the state; and a second state: according to the FLASH erasing time sequence, carrying out integral erasing on the FLASH through an SPI bus, if the erasing is successful, setting an erasing completion register to be 1, and entering a state III, otherwise, repeating the state; and a third state: reading a FLASH erasing register of a BAR space, entering a state IV after waiting for zero clearing, and otherwise, repeating the state; and a fourth state: configuring data register data to buffer in FIFO, and setting FIFO full identification register as 1 when FIFO is full; when the FIFO is not empty, the state is repeated, and the data is continuously written into the FLASH through the SPI bus; when the FIFO is empty, if the sending completion register is 0, the state is repeated to wait for new data, if the sending completion register is 1, the configuration data is completely written, and the state enters a fifth state; and a fifth state: load done register set 1 enters state one.

4. The heterogeneous platform FPGA multi-version configuration file loading management method according to claim 1, characterized in that: the loading decision software processing flow comprises the following steps: the method comprises the following steps: reading a PCIE BAR slot register to obtain the information of the slot; step two: reading the slot position information file to obtain the last slot position information; step three: searching a mapping table to respectively obtain FPGA configuration data identification numbers corresponding to the mapping table and the FPGA configuration data identification numbers; step four: comparing the identification numbers, if the identification numbers are consistent, not starting the loading process, otherwise, calling the software for loading and configuring data to start the loading process; step five: and updating the slot position information file and storing the slot position information into the file.

5. The heterogeneous platform FPGA multi-version configuration file loading management method according to claim 1, characterized in that: the software processing flow for loading and configuring data comprises the following steps: the method comprises the following steps: starting, checking the authority to ensure that the executing user has the authority; step two: opening a PCIE equipment node; step three: acquiring the total byte number of the configuration file to be loaded; step four: opening a configuration file; step five: sending a completion register set 0 and a FLASH erasing register set 1, namely sending a FLASH erasing command; step six: reading the erasure completion register, and setting the erasure register to be 0 after the erasure is completed; step seven: acquiring data blocks with the size of 1024 bytes from the configuration data file, and filling 0xff for completion when the residual data is less than 1024 bytes; step eight: reading the FIFO status register, sequentially writing the configuration data into the configuration data register when the FIFO is not full, if the FIFO is full, delaying a short time and repeatedly executing the step until all data in the data block are written; step nine, repeating the step seven and the step eight until the configuration file data is completely written; step ten: a data transmission completion register 1; step eleven: reading a loading completion register and confirming the successful loading; step twelve: the device is shut down.