CN110018791A - Power managed control method and system based on SSD SOC - Google Patents
Power managed control method and system based on SSD SOC Download PDFInfo
- Publication number
- CN110018791A CN110018791A CN201910243366.4A CN201910243366A CN110018791A CN 110018791 A CN110018791 A CN 110018791A CN 201910243366 A CN201910243366 A CN 201910243366A CN 110018791 A CN110018791 A CN 110018791A
- Authority
- CN
- China
- Prior art keywords
- low
- power consumption
- power
- signal
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0625—Power saving in storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
- G06F3/0634—Configuration or reconfiguration of storage systems by changing the state or mode of one or more devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
Abstract
This application involves a kind of power managed control method, system, computer equipment and storage mediums based on SSD SOC, wherein the system includes: controller register, and the controller register is used for by from the register inside the Configuration Control Unit of bus configuration port；Controller control centre, the controller control centre, which is used to run by main bus from external SRAM instruction fetch code, generates low-power consumption processing signal, or handles signal according to low-power consumption is generated from the configuration of bus；Low-power consumption processing module, the low-power consumption processing module are used to receive the low-power consumption processing signal of controller control centre transmission and carry out low-power consumption processing.The present invention discharges CPU by using independent power managed controller, and flexibility is high, and area is small, itself low in energy consumption, and processing speed is fast, can replace CPU and carries out low-power consumption processing.
Description
Technical field
The present invention relates to solid state hard disk technical fields, more particularly to a kind of power managed controlling party based on SSD SOC
Method, system, computer equipment and storage medium.
Background technique
Currently, under different scenes, there is different power consumption requirements, in order to meet in the application of SSD SOC low-power consumption
This requirement, general using the power supply for reducing speed or closedown module, this just needs individual low power dissipation design.
In the conventional technology, these things are usually done using CPU, CPU cannot be closed a little, additionally due to CPU is usually
For handling complex task, therefore area is larger, and power consumption is higher, and cost is also higher.
Summary of the invention
Based on this, it is necessary in view of the above technical problems, provide a kind of may be implemented instead of CPU progress low-power consumption processing
Power managed control method, system, computer equipment and storage medium based on SSD SOC.
A kind of power managed control system based on SSD SOC, which is characterized in that the power consumption pipe based on SSD SOC
Managing control system includes:
Controller register, the controller register are used for by from posting inside the Configuration Control Unit of bus configuration port
Storage；
Controller control centre, the controller control centre are used to run by main bus from external SRAM instruction fetch code
It generates low-power consumption and handles signal, or handle signal according to low-power consumption is generated from the configuration of bus；
Low-power consumption processing module, the low-power consumption processing module are used to receive at the low-power consumption of controller control centre transmission
Reason signal simultaneously carries out low-power consumption processing.
The low-power consumption processing module is also used in one of the embodiments:
It receives by generating power down signal from bus configuration via controller register；
Receive the power down signal that the operation of main bus instruction fetch code generates；
It is generated and is interrupted to outer CPU according to the power down signal.
In one of the embodiments, the system also includes:
Debounce signaling module, the debounce signaling module is for receiving low-power consumption coherent signal, by debounce logic；
I2C main module, the I2C main module is for generating I2C main signal control external chip.
In one of the embodiments, the system also includes:
Main bus state machine, the main bus state machine are used to generate the control logic of main bus.
The controller register is also used in one of the embodiments:
By from the register inside the Configuration Control Unit of bus configuration port；The content of configuration includes that power down signal is interrupted
Control, the setting of debounce signaling module and the setting of I2C main module；
Wherein, it can be accessed, can also be accessed by outside by the main bus of power managed controller from bus.
The controller control centre is also used in one of the embodiments:
Receive the signal that the debounce signaling module generates；
I2C main signal is generated, and the I2C main signal is sent to the I2C main module.
A kind of power managed control method based on SSD SOC, applied to described in any of the above embodiments based on SSD SOC's
Power managed control system, which comprises
It obtains the power managed based on SSD SOC and controls request；
Request is controlled according to the power managed based on SSD SOC, is transported by main bus from external SRAM instruction fetch code
Row generates low-power consumption and handles signal；
Signal is handled according to the low-power consumption by low-power consumption processing module and carries out low-power consumption processing.
In one of the embodiments, after the step of power managed of the acquisition based on SSD SOC controls request
Further include:
Request is controlled according to the power managed based on SSD SOC, by out of bus configuration port Configuration Control Unit
The register in portion；
Signal is handled according to low-power consumption is generated from the configuration of bus；
Signal is handled according to the low-power consumption by low-power consumption processing module and carries out low-power consumption processing.
A kind of computer equipment can be run on a memory and on a processor including memory, processor and storage
The step of computer program, the processor realizes above-mentioned any one method when executing the computer program.
A kind of computer readable storage medium, is stored thereon with computer program, and the computer program is held by processor
The step of above-mentioned any one method is realized when row.
Above-mentioned power managed control method, system, computer equipment and storage medium based on SSD SOC, passes through design
Individual power managed control system can also pass through reception SSD main control chip for doing some configurations operations instead of CPU
Some power down signals, for it is lower electricity or power on operation；It can be with plug-in SRAM (Static RAM), for storing
Customized instruction code does necessary processing for lower electricity or before powering on.The power managed control system can replace CPU into
Row low-power consumption processing, realizes the flexibility for improving the power managed of SSD SOC, and area is smaller, low in energy consumption, the processing of itself
Speed is faster.
Detailed description of the invention
Fig. 1 is the structural block diagram of the power managed control system based on SSD SOC in one embodiment；
Fig. 2 is the structural block diagram of the power managed control system based on SSD SOC in another embodiment；
Fig. 3 is the structural block diagram of the power managed control system based on SSD SOC in further embodiment；
Fig. 4 is the complete structure schematic diagram of SSD SOC power managed controller system in one embodiment；
Fig. 5 is the flow diagram of the power managed control method based on SSD SOC in one embodiment；
Fig. 6 is the flow diagram of the power managed control method based on SSD SOC in another embodiment；
Fig. 7 is the internal structure chart of computer equipment in one embodiment.
Specific embodiment
It is with reference to the accompanying drawings and embodiments, right in order to which the objects, technical solutions and advantages of the application are more clearly understood
The application is further elaborated.It should be appreciated that specific embodiment described herein is only used to explain the application, and
It is not used in restriction the application.
In the conventional technology, in the application of SSD SOC low-power consumption, under different scenes, there are power consumption requirements, in order to meet
This requirement is general using the power supply (needing individual low power dissipation design) for reducing speed or closedown module.It is conventionally employed
CPU does these things, and CPU cannot be closed a little, and CPU is processing complex task, and area is larger, and power consumption is higher.
The present invention proposes a kind of power managed control method and system based on SSD SOC, by using independent power consumption
Management Controller discharges CPU, and flexibility is high, and area is small, itself low in energy consumption, and processing speed is fast, can replace CPU carry out it is low
Power consumption processing.
In one embodiment, as shown in Figure 1, providing a kind of power managed control system 100 based on SSD SOC,
The system includes:
Controller register 101, for by from the register inside the Configuration Control Unit of bus configuration port；
Controller control centre 102 generates low-power consumption processing for running by main bus from external SRAM instruction fetch code
Signal, or signal is handled according to low-power consumption is generated from the configuration of bus；
Low-power consumption processing module 103, for receiving the low-power consumption processing signal of controller control centre transmission and carrying out low
Power consumption processing.
In one embodiment, low-power consumption processing module 103 is also used to:
It receives by generating power down signal from bus configuration via controller register；
Receive the power down signal that the operation of main bus instruction fetch code generates；
It is generated and is interrupted to outer CPU according to power down signal.
Specifically, in conjunction with reference Fig. 4, in the present embodiment, controller register configures port from AHB, can specifically use
Register inside Configuration Control Unit.The particular content of configuration relates generally to the relevant signal of low-power consumption, interrupts control, debounce
The setting of module and the setting of I2C.
Controller controls control centre and is run by main bus to external SRAM instruction fetch code, generates the letter of low-power consumption processing
Number；Also it can receive the configuration from bus, generate the signal of low-power consumption processing.
The relevant signal of low-power consumption is received, generates and interrupts to outer CPU.Specifically, it can receive by from bus configuration,
Via controller register, the relevant signal of low-power consumption is generated, also can receive the low function that the operation of main bus instruction fetch code generates
Consume relevant signal.
In the present embodiment, CPU can replace by power managed control system, does some configuration operations, can also connects
The some power down signals for receiving SSD main control chip, for lower electricity or power on operation；It can (static random be deposited with plug-in SRAM
Reservoir), for storing customized instruction code, necessary processing is done for lower electricity or before powering on.The present embodiment also achieves
Low-power consumption process flow discharges CPU.In addition, the present embodiment can configure by using AHB (Advanced High-performance Bus) Bus Wrapper
Parameter, integrated level is good, and performance is high.
In one embodiment, as shown in Fig. 2, providing a kind of power managed control system 100 based on SSD SOC,
The system further include:
Debounce signaling module 104, for receiving low-power consumption coherent signal, by debounce logic；
I2C main module 105, for generating I2C main signal control external chip.
In one embodiment, as shown in figure 3, providing a kind of power managed control system 100 based on SSD SOC,
The system further include:
Main bus state machine 106, for generating the control logic of main bus.
In one embodiment, controller register 101 is also used to:
By from the register inside the Configuration Control Unit of bus configuration port；The content of configuration includes that power down signal is interrupted
Control, the setting of debounce signaling module and the setting of I2C main module；
Wherein, it can be accessed, can also be accessed by outside by the main bus of power managed controller from bus.
In one embodiment, controller control centre 102 is also used to:
Receive the signal that debounce signaling module 104 generates；
I2C main signal is generated, and I2C main signal is sent to I2C main module 105.
Specifically, it is whole design module frame chart and data flow diagram with reference to Fig. 4, mainly includes following module:
Controller register: port is configured from AHB, for the register inside Configuration Control Unit；Relate generally to low-power consumption
Relevant signal interrupts control, the setting of debounce module, the setting of I2C；From bus, power managed controller can be passed through
Main bus access, can also pass through outside access.
Controller controls control centre: receiving the signal that debounce module generates；Generate main I2C signal；It is arrived by main bus
The operation of external SRAM instruction fetch code, generates the signal of low-power consumption processing；Also it can receive the configuration from bus, generate at low-power consumption
The signal of reason.
Low-power consumption processing module: the relevant signal of low-power consumption is received, generates and interrupts to outer CPU；It receives by from bus
Configuration generates the relevant signal of low-power consumption via controller register；Receive the low-power consumption that the operation of main bus instruction fetch code generates
Relevant signal.
Debounce signaling module: the relevant signal of low-power consumption is received, by debounce logic.
I2C main module: I2C main signal is generated, for controlling outside, such as power supply chip.
Main bus state machine: for generating the control logic of main bus AHB.
Wherein, the instruction code structure of controller control control centre includes two kinds of instruction code structures: 32Bit instruction+32Bit
Operand/32bit instruction.The instruction of support: do-nothing operation/movement/read/write/computations: and/or/it is non-/ wait instruction/judgement
Jump instruction etc..
In one embodiment, as shown in figure 5, providing a kind of power managed control method based on SSD SOC, application
The power managed control system based on SSD SOC in above-described embodiment, this method comprises:
Step 502, it obtains the power managed based on SSD SOC and controls request；
Step 504, request is controlled according to the power managed based on SSD SOC, by main bus from external SRAM instruction fetch
Code operation generates low-power consumption and handles signal；
Step 506, signal is handled according to low-power consumption by low-power consumption processing module and carries out low-power consumption processing.
In the present embodiment, subsequent not need CPU specifically except initializing at the beginning.Specifically, firstly, using
The SRAM that CPU instructs external storage is initialized, and relates generally to power on process flow and lower electric treatment process.Then, etc.
/ lower electric signal is powered on to outside, or configuration commencing signal, power managed controller go external SRAM instruction fetch, start to process
Related procedure, until processing is completed.
In one embodiment, it as shown in fig. 6, providing a kind of power managed control method based on SSD SOC, is obtaining
After the step of taking the power managed based on SSD SOC to control request further include:
Step 602, request is controlled according to the power managed based on SSD SOC, is controlled by being configured from bus configuration port
Register inside device；
Step 604, low-power consumption processing signal is generated according to from the configuration of bus；
Step 606, signal is handled according to low-power consumption by low-power consumption processing module and carries out low-power consumption processing.
In the present embodiment, plug-in instruction SRAM is not needed, but relies on CPU.Specifically, firstly, CPU receives low function
Consume the interruption that signal generates.Then, judged according to the interrupt signal received, configuration PMU correlation setting starts to process
Electricity/lower electricity process.
Specific restriction about the power managed control method based on SSD SOC may refer to above for based on SSD
The restriction of the power managed control system of SOC, details are not described herein.
It should be understood that although each step in the flow chart of Fig. 5-6 is successively shown according to the instruction of arrow,
These steps are not that the inevitable sequence according to arrow instruction successively executes.Unless expressly stating otherwise herein, these steps
Execution there is no stringent sequences to limit, these steps can execute in other order.Moreover, at least one in Fig. 5-6
Part steps may include that perhaps these sub-steps of multiple stages or stage are not necessarily in synchronization to multiple sub-steps
Completion is executed, but can be executed at different times, the execution sequence in these sub-steps or stage is also not necessarily successively
It carries out, but can be at least part of the sub-step or stage of other steps or other steps in turn or alternately
It executes.
In one embodiment, a kind of computer equipment is provided, internal structure chart can be as shown in Figure 7.The calculating
Machine equipment includes processor, memory and the network interface connected by system bus.Wherein, the processing of the computer equipment
Device is for providing calculating and control ability.The memory of the computer equipment includes non-volatile memory medium, built-in storage.It should
Non-volatile memory medium is stored with operating system, computer program and database.The built-in storage is non-volatile memories Jie
The operation of operating system and computer program in matter provides environment.The network interface of the computer equipment is used for and external end
End passes through network connection communication.To realize a kind of power managed based on SSD SOC when the computer program is executed by processor
Control method.
It will be understood by those skilled in the art that structure shown in Fig. 7, only part relevant to application scheme is tied
The block diagram of structure does not constitute the restriction for the computer equipment being applied thereon to application scheme, specific computer equipment
It may include perhaps combining certain components or with different component layouts than more or fewer components as shown in the figure.
In one embodiment, a kind of computer equipment is provided, including memory, processor and storage are on a memory
And the computer program that can be run on a processor, processor are realized when executing computer program in above each embodiment of the method
The step of.
In one embodiment, a kind of computer readable storage medium is provided, computer program is stored thereon with, is calculated
The step in above each embodiment of the method is realized when machine program is executed by processor.
Those of ordinary skill in the art will appreciate that realizing all or part of the process in above-described embodiment method, being can be with
Relevant hardware is instructed to complete by computer program, the computer program can be stored in a non-volatile computer
In read/write memory medium, the computer program is when being executed, it may include such as the process of the embodiment of above-mentioned each method.Wherein,
To any reference of memory, storage, database or other media used in each embodiment provided herein,
Including non-volatile and/or volatile memory.Nonvolatile memory may include read-only memory (ROM), programming ROM
(PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM) or flash memory.Volatile memory may include
Random access memory (RAM) or external cache.By way of illustration and not limitation, RAM is available in many forms,
Such as static state RAM (SRAM), dynamic ram (DRAM), synchronous dram (SDRAM), double data rate sdram (DDRSDRAM), enhancing
Type SDRAM (ESDRAM), synchronization link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM
(RDRAM), direct memory bus dynamic ram (DRDRAM) and memory bus dynamic ram (RDRAM) etc..
Each technical characteristic of above embodiments can be combined arbitrarily, for simplicity of description, not to above-described embodiment
In each technical characteristic it is all possible combination be all described, as long as however, the combination of these technical characteristics be not present lance
Shield all should be considered as described in this specification.
The several embodiments of the application above described embodiment only expresses, the description thereof is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the concept of this application, various modifications and improvements can be made, these belong to the protection of the application
Range.Therefore, the scope of protection shall be subject to the appended claims for the application patent.
Claims (10)
1. a kind of power managed control system based on SSD SOC, which is characterized in that the power managed based on SSD SOC
Control system includes:
Controller register, the controller register are used for by from the deposit inside the Configuration Control Unit of bus configuration port
Device；
Controller control centre, the controller control centre are used to run by main bus from external SRAM instruction fetch code and generate
Low-power consumption handles signal, or handles signal according to low-power consumption is generated from the configuration of bus；
Low-power consumption processing module, the low-power consumption processing module are used to receive the low-power consumption processing letter of controller control centre transmission
Number and carry out low-power consumption processing.
2. the power managed control system according to claim 1 based on SSD SOC, which is characterized in that the low-power consumption
Processing module is also used to:
It receives by generating power down signal from bus configuration via controller register；
Receive the power down signal that the operation of main bus instruction fetch code generates；
It is generated and is interrupted to outer CPU according to the power down signal.
3. the power managed control system according to claim 2 based on SSD SOC, which is characterized in that the system is also
Include:
Debounce signaling module, the debounce signaling module is for receiving low-power consumption coherent signal, by debounce logic；
I2C main module, the I2C main module is for generating I2C main signal control external chip.
4. the power managed control system according to claim 3 based on SSD SOC, which is characterized in that the system is also
Include:
Main bus state machine, the main bus state machine are used to generate the control logic of main bus.
5. the power managed control system according to claim 4 based on SSD SOC, which is characterized in that the controller
Register is also used to:
By from the register inside the Configuration Control Unit of bus configuration port；The content of configuration includes that power down signal interrupts control
System, the setting of debounce signaling module and the setting of I2C main module；
Wherein, it can be accessed, can also be accessed by outside by the main bus of power managed controller from bus.
6. the power managed control system according to claim 5 based on SSD SOC, which is characterized in that the controller
Control centre is also used to:
Receive the signal that the debounce signaling module generates；
I2C main signal is generated, and the I2C main signal is sent to the I2C main module.
7. a kind of power managed control method based on SSD SOC is applied to described in any one of claims 1-6 based on SSD
The power managed control system of SOC, which is characterized in that the described method includes:
It obtains the power managed based on SSD SOC and controls request；
Request is controlled according to the power managed based on SSD SOC, is run and is produced from external SRAM instruction fetch code by main bus
Raw low-power consumption handles signal；
Signal is handled according to the low-power consumption by low-power consumption processing module and carries out low-power consumption processing.
8. the power managed control method according to claim 7 based on SSD SOC, which is characterized in that in the acquisition
Power managed based on SSD SOC controlled after the step of request further include:
Request is controlled according to the power managed based on SSD SOC, by inside the Configuration Control Unit of bus configuration port
Register；
Signal is handled according to low-power consumption is generated from the configuration of bus；
Signal is handled according to the low-power consumption by low-power consumption processing module and carries out low-power consumption processing.
9. a kind of computer equipment including memory, processor and stores the meter that can be run on a memory and on a processor
Calculation machine program, which is characterized in that the processor realizes method described in claim 7 or 8 when executing the computer program
The step of.
10. a kind of computer readable storage medium, is stored thereon with computer program, which is characterized in that the computer program
The step of method described in claim 7 or 8 is realized when being executed by processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910243366.4A CN110018791B (en) | 2019-03-28 | 2019-03-28 | SSD SOC-based power consumption management control method and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910243366.4A CN110018791B (en) | 2019-03-28 | 2019-03-28 | SSD SOC-based power consumption management control method and system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110018791A true CN110018791A (en) | 2019-07-16 |
| CN110018791B CN110018791B (en) | 2023-02-10 |
Family
ID=67190310
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910243366.4A Active CN110018791B (en) | 2019-03-28 | 2019-03-28 | SSD SOC-based power consumption management control method and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110018791B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110401939A (en) * | 2019-09-04 | 2019-11-01 | 大唐半导体科技有限公司 | A kind of low-power consumption bluetooth controller link layer device |
| CN110519390A (en) * | 2019-09-04 | 2019-11-29 | 大唐半导体科技有限公司 | A kind of low-power consumption bluetooth controller link layer implementation method |
| CN111077975A (en) * | 2019-12-17 | 2020-04-28 | 深圳忆联信息***有限公司 | Method and device for reducing Power State3 Power consumption of SSD, computer equipment and storage medium |
| CN113325998A (en) * | 2020-02-29 | 2021-08-31 | 杭州海康存储科技有限公司 | Read-write speed control method and device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101498963A (en) * | 2009-03-02 | 2009-08-05 | 北京红旗胜利科技发展有限责任公司 | Method for reducing CPU power consumption, CPU and digital chip |
| US20100325455A1 (en) * | 2007-11-15 | 2010-12-23 | Ricoh Company, Ltd. | Memory card control device and method for controlling the same |
| CN102725997A (en) * | 2011-12-09 | 2012-10-10 | 华为技术有限公司 | Method and device for realizing low power consumption of data switching equipment, and data switching equipment |
| CN102799260A (en) * | 2012-07-31 | 2012-11-28 | 福州瑞芯微电子有限公司 | Circuit and method for managing SOC chip by low-power consumption mode based on clock off |
| CN104793723A (en) * | 2015-05-13 | 2015-07-22 | 中国电子科技集团公司第四十七研究所 | Low-power-consumption control circuit based on level detection |
| CN107678532A (en) * | 2017-10-20 | 2018-02-09 | 苏州国芯科技有限公司 | A kind of low-power dissipation SOC wake module and low-power dissipation SOC |
| CN108089689A (en) * | 2017-11-17 | 2018-05-29 | 珠海慧联科技有限公司 | A kind of small-sized SoC super low-power consumptions control circuit and method |
-
2019
- 2019-03-28 CN CN201910243366.4A patent/CN110018791B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100325455A1 (en) * | 2007-11-15 | 2010-12-23 | Ricoh Company, Ltd. | Memory card control device and method for controlling the same |
| CN101498963A (en) * | 2009-03-02 | 2009-08-05 | 北京红旗胜利科技发展有限责任公司 | Method for reducing CPU power consumption, CPU and digital chip |
| CN102725997A (en) * | 2011-12-09 | 2012-10-10 | 华为技术有限公司 | Method and device for realizing low power consumption of data switching equipment, and data switching equipment |
| CN102799260A (en) * | 2012-07-31 | 2012-11-28 | 福州瑞芯微电子有限公司 | Circuit and method for managing SOC chip by low-power consumption mode based on clock off |
| CN104793723A (en) * | 2015-05-13 | 2015-07-22 | 中国电子科技集团公司第四十七研究所 | Low-power-consumption control circuit based on level detection |
| CN107678532A (en) * | 2017-10-20 | 2018-02-09 | 苏州国芯科技有限公司 | A kind of low-power dissipation SOC wake module and low-power dissipation SOC |
| CN108089689A (en) * | 2017-11-17 | 2018-05-29 | 珠海慧联科技有限公司 | A kind of small-sized SoC super low-power consumptions control circuit and method |
Non-Patent Citations (1)
| Title |
|---|
| 尚军辉: "通用SOC***的低功耗设计方法", 《中国集成电路》 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110401939A (en) * | 2019-09-04 | 2019-11-01 | 大唐半导体科技有限公司 | A kind of low-power consumption bluetooth controller link layer device |
| CN110519390A (en) * | 2019-09-04 | 2019-11-29 | 大唐半导体科技有限公司 | A kind of low-power consumption bluetooth controller link layer implementation method |
| CN110401939B (en) * | 2019-09-04 | 2023-03-24 | 大唐半导体科技有限公司 | Low-power consumption bluetooth controller link layer device |
| CN111077975A (en) * | 2019-12-17 | 2020-04-28 | 深圳忆联信息***有限公司 | Method and device for reducing Power State3 Power consumption of SSD, computer equipment and storage medium |
| CN111077975B (en) * | 2019-12-17 | 2021-07-13 | 深圳忆联信息***有限公司 | Method and device for reducing Power State3 Power consumption of SSD, computer equipment and storage medium |
| CN113325998A (en) * | 2020-02-29 | 2021-08-31 | 杭州海康存储科技有限公司 | Read-write speed control method and device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110018791B (en) | 2023-02-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110018791A (en) | Power managed control method and system based on SSD SOC | |
| US11914530B2 (en) | Memory having internal processors and data communication methods in memory | |
| US20200159279A1 (en) | Low power autonomous peripheral management | |
| US9606807B2 (en) | Direct communication with a processor internal to a memory device | |
| EP2438520B1 (en) | Communication between internal and external processors | |
| US10156884B2 (en) | Local power gate (LPG) interfaces for power-aware operations | |
| US6564313B1 (en) | System and method for efficient instruction prefetching based on loop periods | |
| CN108121672A (en) | A kind of storage array control method and device based on Nand Flash memorizer multichannel | |
| US9323306B2 (en) | Energy based time scheduler for parallel computing system | |
| EP2241969B1 (en) | Program and data annotation for hardware customization and energy optimization | |
| US8850123B2 (en) | Cache prefetch learning | |
| US20180181186A1 (en) | Buffering data from high-speed i/o to enable longer reduced power consumption state residency | |
| US9886278B2 (en) | Computing architecture and method for processing data | |
| CN108958848A (en) | Nearly memory counting system structure | |
| US9971390B1 (en) | Processor energy consumption rate limiting system | |
| CN105095138A (en) | Method and device for expanding synchronous memory bus function | |
| US7685439B2 (en) | Method for effecting the controlled shutdown of data processing units | |
| US11829619B2 (en) | Resource usage arbitration in non-volatile memory (NVM) data storage devices with artificial intelligence accelerators | |
| CN103019657B (en) | Supported data is looked ahead and the reconfigurable system of reusing | |
| CN102542525B (en) | Information processing equipment and information processing method | |
| US20210141723A1 (en) | Memory usage in managed runtime applications | |
| TWI716909B (en) | Memory control system and method for operating a memory control system | |
| CN108196849A (en) | A kind of low latency instruction scheduler | |
| CN107168708A (en) | A kind of reconfigurable system Configuration Control Unit and its Flow-shop method | |
| US20140156685A1 (en) | Loopback structure and data loopback processing method of processor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |